Mees Frensel received his M.Sc. degree from TU Delft, the Netherlands, in 2024. He has a background in computer architecture, heterogeneous computing, and genomics applications for long-read sequencing. At the Chair for Compiler Construction, Mees is working on the genomICs project that aims to accelerate sequence analysis pipelines using emerging near-memory and in-memory computing architectures. Genomics applications benefit from these architectures due to their high data volume and possibilities for massively parallel algorithms.

• Optimizing programs for hybrid CPU-PL-AIE execution on Versal FPGAs
  AMD's AI engines promise energy-efficient and high throughput compute on the same chip as the programmable logic (PL). Deep neural network inference can benefit especially from this energy efficiency, because using power-hungry GPUs is not always desired. However, constraints posed by the network-on-chip interconnect as well as limited PL<>AIE bandwidth make it nontrivial to map programs to this architecture. Even more so than on GPU, optimizing for data reuse is extremely important. Furthermore, while the AIEs are great at performing high throughput SIMD operations, the PL can be used to do scalar operations and things like reductions. We'd like to know more about what ways to optimize for this architecture can bring benefits in what areas, and this could be something from design-space exploration to polyhedral compilation or another approach.
  
  
  Requirements: knowledge of C++ and some experience with high-level synthesis (HLS) or FPGAs - RTL design skills not required
  Bonus: experience with implementing DNNs
  Related work: Charm 2.0, AIEs for dummies, and Mapping matmul to Versal ACAP