cfaed Seminar Series

cfaed Seminar Series

Dr. Marie Garcia Bardon , IMEC, Belgium

Design-technology co-optimization to push the scaling limits of digital CMOS circuits

21.03.2017 (Tuesday) , 17:00 - 18:30
BIOTEC, seminar rooms E05/E06 , Tatzberg 47-49 , 01307 Dresden


Digital circuits have followed a constant pace of scaling: every two years, a new technology generation was produced with reduced area, reduced power, increased speed. The reduction of dimensions lead us today to fundamental limits in both fabrication and device physics. To continue this road of improvements and still get the most of CMOS based technologies, numerous disruptive innovations have to be considered at device and fabrication level, but also at circuit level. We will see how both technology and circuit are modelled and co-optimized in an early development phase to downselect the materials, devices, lithography, circuit options that allows to push forward the CMOS scaling roadmap.

About the speaker:

Marie Garcia Bardon received the M.Sc. degree in electromechanical engineering from the Université Catholique de Louvain, Louvain-la-Neuve, in 2004, and the Ph.D. degree in microelectronics from the Katholieke Universiteit Leuven, in collaboration with imec, in 2010.
Her PhD was on the fabrication, characterization, and modeling of suspended-gate transistors. Since then, she has been modeling and evaluating several devices for digital logic and memory applications, including FinFETs, Nanowires, Tunnel FET, Resistive RAMs. She has specialized in holistic pre-silicon evaluation of technology and circuit options, working closely together with circuit designers, device integration specialists and imec industrial partners.

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