Coding for Racetrack Memory
AImprovements in memory and storage result from advances in the memory technologies themselves, but also from innovations by computer architects who design new systems, and from coding theorists who develop new ways of representing information.
The appeal of racetrack memory is the combination of very high storage density and very low read/write latency. Data is stored in tape-like tracks, and to read a stored bit, a current is injected to place the desired bit under the read/write port. Shift errors occur when the target bit is positioned either ahead or behind the read/write port. The problem of designing codes that are able to correct general shift errors goes back to work of Ullman, Gallager and Dobrushin in the 1960s. The problem has resisted solution, and though bounds on rate are known, exact capacities are not.
This talk will describe how to introduce delimiter bits at regular intervals to identify particular single shift errors, then how to develop extremely low complexity codes that correct the errors once identified. Separating detection from correction makes the common case, of no shift error, extremely fast and efficient. We will compare with prior work on racetrack memory in the computer architecture community, which introduced extra hardware and extra read/write operations.
This is joint work with Georgios Mappouros, Dan Sorin and Alireza Vahid