Jiahong Bi |
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Phone Fax Visitor's Address |
+49 (0)351 463 43726 +49 (0)351 463 39995 Helmholtzstrasse 18, BAR III60 |
Jiahong Bi received his Bachelor degree in Computer Science and Technology from Xidian University, China in June 2019, and his Master degree in CS from TU Dresden in December 2023. His Master Thesis is finished at the Chair for Compiler Construction, focusing on implementing and evaluating a custom FPGA back-end for a data flow model MLIR dialect, which utilizes High-Level Synthesis by CIRCT project and several AMD Xilinx tools.
Jiahong finished his research project at CCC in January 2023, then continued working as a research student till April 2023. Jiahong did research work with Chair of Adaptive Dynamic System from 2022 to 2023 as well, from which he gained knowledge of FPGA hardware and HLS technology. After these Jiahong joined the chair as research assistant in February 2024, where he will work on project “MYRTUS: Multi-layer 360° dYnamic orchestrion and interopeRable design environmenT for compute-continUum Systems”, including defining novel programming methods and compiler infrastructures to deploy optimized software onto heterogeneous computing systems in both the embedded and high-performance computing domains.
2023
- Jiahong Bi, "A Lowering for High-Level Data Flows to Reconfigurable Hardware", Master's thesis, TU Dresden, Dec 2023. [Bibtex & Downloads]
A Lowering for High-Level Data Flows to Reconfigurable Hardware
×Reference
Jiahong Bi, "A Lowering for High-Level Data Flows to Reconfigurable Hardware", Master's thesis, TU Dresden, Dec 2023.
Bibtex
@mastersthesis{bi-masters23,
title={A Lowering for High-Level Data Flows to Reconfigurable Hardware},
author={Jiahong Bi},
year={2023},
month=dec,
school={TU Dresden},
}Downloads
2312_Bi_MA [PDF]
Permalink
- Karl F. A. Friebel, Jiahong Bi, Jeronimo Castrillon, "BASE2: An IR for Binary Numeral Types", In Proceeding: 13th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2023), Association for Computing Machinery, pp. 19–26, New York, NY, USA, Jun 2023. [doi] [Bibtex & Downloads]
BASE2: An IR for Binary Numeral Types
×Reference
Karl F. A. Friebel, Jiahong Bi, Jeronimo Castrillon, "BASE2: An IR for Binary Numeral Types", In Proceeding: 13th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2023), Association for Computing Machinery, pp. 19–26, New York, NY, USA, Jun 2023. [doi]
Abstract
Custom data types and arbitrary-precision arithmetic are often key for efficient hardware designs on Field Programmable Gate Array (FPGA) platforms. Current end-to-end flows incorporating quantization are not only domain-specific, but also tightly integrated and not repurposable. Abstractions for arbitrary-precision arithmetic are generally vendor-specific, and results are hardly portable across platforms. In this work, we present a new Intermediate Representation (IR), base2, to address the programmability issues of custom data types in reconfigurable hardware. We contextualize our proposal in the greater LLVM (llvm) ecosystem, where we show how existing abstractions can be simplified and unified. We implement base2 in Multi-Level Intermediate Representation (MLIR), which allows it to be used in a variety of existing and future target-agnostic front-ends. We demonstrate the power of our model by applying it to sample kernels and evaluating the accuracy of the result. For these samples, we achieve interoperability with an existing end-to-end High-Level Synthesis (HLS) flow.
Bibtex
@InProceedings{friebel_heart23,
author = {Karl F. A. Friebel and Jiahong Bi and Jeronimo Castrillon},
booktitle = {13th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2023)},
title = {{BASE2}: An {IR} for Binary Numeral Types},
doi = {10.1145/3597031.3597048},
isbn = {9798400700439},
location = {Kusatsu, Japan},
pages = {19--26},
publisher = {Association for Computing Machinery},
series = {HEART2023},
url = {https://doi.org/10.1145/3597031.3597048},
abstract = {Custom data types and arbitrary-precision arithmetic are often key for efficient hardware designs on Field Programmable Gate Array (FPGA) platforms. Current end-to-end flows incorporating quantization are not only domain-specific, but also tightly integrated and not repurposable. Abstractions for arbitrary-precision arithmetic are generally vendor-specific, and results are hardly portable across platforms. In this work, we present a new Intermediate Representation (IR), base2, to address the programmability issues of custom data types in reconfigurable hardware. We contextualize our proposal in the greater LLVM (llvm) ecosystem, where we show how existing abstractions can be simplified and unified. We implement base2 in Multi-Level Intermediate Representation (MLIR), which allows it to be used in a variety of existing and future target-agnostic front-ends. We demonstrate the power of our model by applying it to sample kernels and evaluating the accuracy of the result. For these samples, we achieve interoperability with an existing end-to-end High-Level Synthesis (HLS) flow.},
address = {New York, NY, USA},
month = jun,
numpages = {8},
year = {2023},
}Downloads
2306_Friebel_HEART [PDF]
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