Chair News

Best Paper Award

August 02, 2018

Our paper "Column Scan Optimization by Increasing Intra-Instruction Parallelism" received the best paper award of the 2018 7th-International Conference on Data Science, Technology and Applications (DATA).

New Postdoc joined the Chair

Dr. Seetal Potluri has the joined the Chair for Processor Design in May 2018.

Steffen Märcker joins the chair

Steffen Märcker has joined the chair for Processor Design in April 2018.

Join Texas Instruments and IEEE CEDA @DATE 2018 for an Exciting Day practicing with TI’s SimpleLink Technology

The SimpleLink MCU platform from Texas Instruments is a single development environment that delivers flexible hardware, software and tool options for customers developing Internet of Things (IoT) applications. With a single software architecture, modular development kits and free software tools for every point in the design lifecycle, the SimpleLink MCU ecosystem allows great code reuse across the portfolio of microcontrollers; which supports a wide range of connectivity standards and technologies including RS-485, Bluetooth® low energy, Wi-Fi®, Sub-1 GHz, 6LoWPAN, zigbee®, Ethernet, Thread, RF4CE and proprietary RF. SimpleLink MCUs help manufacturers easily develop and seamlessly reuse resources to expand their portfolio of connected products. TI and IEEE CEDA bring you the opportunity to get the tools, training and participate in an exciting challenge all for free!

Location: ICCD, room "Konferenz 6"



Monday, 9:30 am – 12:30 pm

  • Introduction to SimpleLink Technology
  • Description of development tools
  • Hands-on exercises with TI Senior System Engineer
  • Practical information for the challenge
  • Q&A

Monday, 13:30 – 17:30

  • Participation in student challenge
  • Students will develop a cloud project using TI Development tools, including CCS cloud, GUI Composer, Sensor BoosterPack, and Launchpad boards.
  • Participants will program TI LaunchPad™ development kits to connect and send sensor data to a gateway via SubGHz RF, and then ultimately to the cloud.
  • The challenge will lead students to the ultimately find the data in the cloud, display it locally on a PC, and find the code that will unlock the prizes for the winning teams.

Material provided to the students for free

Each participant will be offered a Launchpad and Sensors Boosterpack that will allow setting up their own Wireless Sensor Network during the tutorial. Winning teams will also receive the Gateway hardware for setting up a real cloud connection.

The CC1350 is the first device in the CC13xx and CC26xx family of cost-effective, ultra-low-power wireless MCUs capable of handling both Sub-1 GHz and 2.4-GHz RF frequencies. The CC1350 device combines a flexible, very low-power RF transceiver with a powerful 48-MHz ARM® Cortex®-M3 microcontroller in a platform supporting multiple physical layers and RF standards. The combination of easy mobile phone integration, with long-range connectivity, on-chip programmability, and the varied flow of data from multiple sensors will give you the opportunity to innovate in a broad range of personal or academic projects.


All winning teams will receive the Gateway boards, as well as the sensor nodes used in the lab exercises. In addition they will receive:

  • 1st team (2 people): 2 x MetaWatch with 2 additional SensorTags
  • 2nd team (2 people): 2 x Power banks with 2 additional SensorTags
  • 3rd team (2 people): 2 x drones with 2 additional SensorTags

How to Participate

Students interested in participating can register through this link (or using the QR code below) as a team (2 participants) by March 18th, 2018. If you want to participate but you do not have a partner, just register accordingly and we will find a partner for you. Once registered, you will receive further instructions to install on your laptop the required TI tools before the challenge. Then, stop by the DATE registration on Monday morning and you will get the access to the challenge, material, coffee breaks and lunch all free.

If you have any queries about the competition, please send an email to



Dr. Tuan Duy Anh Nguyen has Joined the Chair

Tuan has a PhD degree from National University of Singapore. He joined the chair for processor design as postdoc in January 2018.

New Guest Researchers Joined Chair

01 December 2017


Mohammed Alser joined CFAED as a guest researcher in October 2017. He is funded by HiPEAC.  He is also a TUBITAK fellow and PhD candidate at AlkanLab of Bilkent University in Turkey.


Mark Wijtvliet joins Chair for Processor Design as a guest researcher, funded by HiPEAC. He is a PhD student at Technische Universiteit Eindhoven.

Best Presentation Award for Akash Kumar at SCOPES 2016

1 Jun 2016

We are proud to announce that Akash Kumar won best presentation award at the 19th International Workshop on Software and Compilers for Embedded Systems for his talk "Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms".

Upcoming: Inaugural Lecture Prof. Akash Kumar - "Design Methodologies for Reliable and Energy-Efficient Multiprocessor System"

29.04.2016 (Friday) , 15:00 - 17:00
Andreas-Pfitzmann-Bau, Room E023, Nöthnitzer Str. 46, 01187 Dresden

portrait Professor Akash Kumar

As the performance demands of applications (e.g., multimedia) are growing, multiple processing cores are integrated together to form multiprocessor systems. Energy minimization is a primary optimization objective for these systems. An emerging concern for designs at deep-submicron technology nodes (65nm and below) is the lifetime reliability, as escalating power density and hence temperature variation continues to accelerate wear-out leading to a growing prominence of device defects. As such, reliability and energy need to be incorporated in the multiprocessor design methodology.
In this talk, Prof. Kumar will present a platform-based design methodology in order to minimize temperature-related wear-outs. Concepts of approximate computing and how they can be used to address the problems shown by emerging power-wall in modern systems will also be covered.

The inaugural lecture will be followed by a small reception.

More details

New Postdoc Joined Chair

14 Oct 2015

Golsa Moayeri Pour

In the beginning of October 2015, Golsa Moayeri Pour joined the Chair for Processor Design where she holds a Postdoc position. In July 2015, the electrical engineer obtained her PhD degree at Purdue University West Lafayette, Indiana, United States.
See LinkedIn profile

Fourth Strategic cfaed Professor: Akash Kumar appointed at TU Dresden

2 Oct 2015

Professor Akash Kumar, cfaed Chair for Processor Design

On 29 September, the native of India scientist Akash Kumar received the certificate of appointment from the Technical University of Dresden. The multiprocessor systems expert is now full professor of TU Dresden and the fourth appointed Strategic Professor of cfaed where he holds the Chair for Processor Design. In summer 2015, Prof. Kumar already spent a two-month research stay at TU Dresden. This period was a useful stepping stone for him to get familiar with his future workplace and to build up first scientific contacts and networks.

Akash Kumar received his Ph.D. degree in electrical engineering in the area of embedded systems from National University of Singapore (NUS) joint with Eindhoven University of Technology, Netherlands. From 2009, he was affiliated with the Department of Electrical and Computer Engineering at NUS and starting 2011 he worked there as an Assistant Professor. During that period, Prof. Kumar has published over 60 papers in leading international electronic design automation journals and conferences.

The focus of his current research lays on designing predictable multi‐processor systems – predictable in terms of both the architecture and the applications. Multiprocessor systems‐on‐chip (MPSoCs) have been proposed as a solution to rising power of modern embedded systems. These systems are becoming increasingly heterogeneous with use of dedicated IP blocks and application domain specific processors. To achieve high performance in such systems, the limited computational resources must be shared. The concurrent execution of dynamic applications on shared resources is a potential source of interference. Modelling and analyzing this interference is a key to building cost‐effective systems which can deliver the desired performance of the applications.