CirroStrato: Synthesis and layout tools for IP protection based on reconfigurable transistors
Today's society is critically dependent on trust in electronic systems. Over the past few years, the security of these systems has repeatedly been threatened by attacks on the hardware level, which software-based security solutions can circumvent. A particular problem is the theft and unauthorized replication of integrated circuits. Inexpensive, but faulty replicas or replicas with Trojans can cause serious failures in mission-critical areas such as self-driving cars or industrial plants cause high collateral damage up to personal injury. The direct and indirect financial damage caused by piracy of intellectual property (IP for short) is estimated at several hundred billion euros annually.
CMOS-based technologies already offer various security mechanisms around the subject-specific IP ('Intellectual Property') of electronic components, which can typically be divided into the three methods' split manufacturing', 'layout camouflaging' and 'logic locking'. Such protective circuits based on classic CMOS technology have proven to be cost-inefficient in terms of the larger chip area and high power consumption. In addition, these technologies often do not provide comprehensive protection of proprietary designs along the entire value chain. Novel nanotechnologies address these problems and offer additional solutions for future fields of application, such as the Internet of Things (IoT).
Project title: CirroStrato: Synthesis and layout tools for IP protection based on reconfigurable transistors
Funding period: March 2021 - February 2024
Funding program: BMBF ZEUS
- Akash Kumar, TU Dresden