Overall Goal + Justification
The vision of our research is to prepare for the usage of future heterogeneous systems as computing platforms. Such systems could comprise, e.g., a many-core CMOS system-on-a-chip with hydrogel-based sensors or actuators for chemical processes (Chemical Information Processing - Path E), carbon nanotubes as amplifiers of wireless networking devices (Carbon – Path B), and/or extremely reliable cores built on arrays of reconfigurable silicon nanowire gates (Silicon Nanowires – Path A).
Each new technology augmenting CMOS solves application-specific tasks. If combined, we refer to such a system as wildly heterogeneous. Wild implies that units with new materials will have drastically varying properties in terms of speed, response time, bandwidth, and lifetime. The core research challenge and goal of this Path is to pave the way for highly efficient wildly heterogeneous systems: how can we support application systems to rapidly take advantage of novel heterogeneous nodes. Although complex circuits of most of the new materials cannot realistically be expected in the first phase of this cluster, it is important to plan ahead and identify and solve integration issues.
Our approach is to focus our research on a novel hardware/software stack and to use heterogeneous, CMOS-based, many-core systems as evaluation test-bed for the future integration of novel materials. By hardware/software stack, we mean the ensemble of individual layers of modern computing systems starting from processor architecture, over the systems layers all the way up to applications. We describe CPU/memory interconnects as an example to illustrate how research based on mostly industry-driven advancements of CMOS can extend to wildly heterogeneous systems and how new materials may revolutionize the computing landscape. Memory latency and bandwidth are major limiting factors for many application areas. Today, large memories are almost entirely off-chip. Bandwidth and latency are therefore limited by interconnects between cores and memory.
Now imagine an unheard amount of interconnects between vertically stacked chips, enabled by new materials, e.g., by growing arrays of metal nanoparticles through photochemical processes, or, in a more distant future, with flexibly connected metalized 3D DNA origami structures (Path D – Biomolecular-Assembled Circuits). A density of interconnects of 100 nm and below could be envisioned. Today’s latency and bandwidth limitation between cores and memories could then become obsolete. This breakthrough would lead to concentrating on efficient interaction between cores instead of cache locality, enabling a new quality of results.
However, to fully exploit these benefits, application algorithms, lower-level systems-software layers, and the underlying hardware platform must be able to adjust to this bandwidth and, more importantly, to fabrication-induced variations of the quality of available interconnects. This example illustrates the need for new programming concepts to develop application algorithms across a multitude of heterogeneous platforms and to map algorithms to heterogeneous cores to take advantage of their different properties. Scalable and adjustable coordination at the operating-system and system-management layers must be researched, and a hardware architecture that is flexible to adjust to different memory topologies and possibly also to different application characteristics.
In other words, we require a new hardware/software stack for wildly heterogeneous systems. 3D-stacked integrated chip-stacks with through-silicon-via interconnects are projected for CMOS allowing for heterogeneous technologies to be in one system. Hence, addressing CMOS challenges can start to pave the way towards wildly heterogeneous systems as well. Research on 3D chip-stacks is a main topic for the TwinLab “3D Stacked Chips” of Masdar Institute and TU Dresden.