Research Area A – Devices: Memory & Logic

Devices are one of the most important building blocks of integrated circuits. They derive their electrical characteristics from the properties of the materials they are made of and their functionality from the circuit they are embedded in. Within Research Area A we have therefore grouped projects that are devoted to the exploration of BEOL-compatible logic and memory devices based upon novel device architectures and novel materials. This work is tightly connected to Research Areas B and C in order to ensure that the resulting devices fulfill their targeted functionality in circuit blocks and are manufacturable in a reproducible way employing appropriate BEOL-compatible fabrication processes. Furthermore, fabricated devices will be used to extract parameters for Research Area B and to validate the modeling and simulation work done in Research Area C.

Intermediate Goals of Research Area A

  • Process flows for a BEOL compatible fabrication of the individual devices
  • Performance parameters that can experimentally be realized in the lab process
  • Envisioned performance parameters of the individual devices extrapolated to a scaled technology under the verified boundary conditions for BEOL integration
  • Layout constraints of the individual devices
  • Requirements for connecting to other devices in the same layer and on different layers
  • Expected heat dissipation of the individual devices in a scaled technology

Long-term Goals of Research Area A

  • Full lab based process flows to integrate the devices in reasonable combinations into the BEOL
  • Expected process flows in scaled down technologies to integrate the different devices in reasonable combinations into the BEOL
  • Lab scale demonstrators to verify and highlight the benefits of the ABEOL approach
  • Flexible process routes across the different labs involved in the TRR
  • Flexible connecting elements for two- and three-terminal devices that can be extended towards future device options
  • Effective methods for limiting local heat dissipation hot spots by design measures and methods
    for physical heat distribution

Research Area A - Projects

A01

Co-design of Area-Dependent VCM Cell Arrays and CMOS Circuits for In-Memory Computing
(R. Dittmann, S. Slesazeck)

When using memory cells to perform logic calculations or vector-matrix multiplication it is important to have an analog switching capability. This project will make analog switching elements available that can be integrated on top of a CMOS circuit. We will develop non-filamentary VCM cells with both analog switching and very low current levels. The latter is highly advantageous in terms of suppressing parasitic effects in dense structures and significantly reducing power consumption. We will co-design the devices and the CMOS circuitry at an early stage.

A02

Under Voltage Control: Nb2O5 Based Locally Active Threshold Switches
(S. Slesazeck, R. Tetzlaff)

Threshold switches allow to implement signal amplification in a two-terminal device. One possible application is to solve NP-hard problems, that are very difficult to solve using the von Neumann architecture, using coupled oscillator circuits. In Phase 1 the solution for one such example problem is guiding the research. In line with the subject of this TRR oscillator cells will be integrated into the BEOL of CMOS chips, where the reconfigurable coupling itself is to be realized by conventional transistor circuits in Phase 1. In Phase 2 the conventional transistors will be replaced by BEOL compatible transistors developed within the TRR, such as RFETs or 2D-materials based devices, and
additional applications of the threshold switches such as neurons and similar devices will be explored.

TU Dresden

A03

3D Integration of Tailored Phase-Change Memorys (PCMs)
(S. Ingebrandt, M. Wuttig)

Phase change materials offer a very versatile method to achieve resistive switching devices that are particularly well suited for storage applications and in-memory computing. At the Aachen site a world class activity on optimized phase change materials is available. The task of this project is to supply 3D integrable phase change blocks that can be used for storage and in-memory computing using tailored phase change materials optimized for the specific tasks. In Phases 2 and 3 also the possibilities of using phase change materials for heat management will be explored on top of continuing the work in connection with other devices.

A04

3D Racetrack Memory Devices
(S. Parkin, B. Rellinghaus)

Magnetic racetrack devices offer distinct potential for achieving both high speed and high density memory and storage functions. Racetrack is based on the novel concept of moving data, thereby allowing for functionalities not possible with conventional approaches. The group at the MPI-MSP has made significant advances towards practical racetrack devices over the past few years. In Phase 1 the main task is to develop a memory device that is non-volatile with SRAM type performance but requires much less real estate compared to 6T SRAM cells. In further phases, high density memory-storage capabilities will be explored based on both 2D and 3D forms of racetrack.

TU Dresden

A05

BEOL-Compatible 3D Reconfigurable Logic
(J. Knoch, J. Trommer)

Reconfigurable devices that can change their polarity between n-type and p-type during run-time show great promises for increasing the complexity of integrated circuits beyond the possibilities of traditional scaling. Since RFETs are based on Schottky-barriers the lower crystal quality of the BEOL-compatible channels is expected to have less impact on the characteristics compared to other logic devices, making them an inherently beneficial device for monolithic BEOL integration. So far, both groups in Dresden and Aachen did groundbreaking work on nanoscale Schottky-barrier FETs and specifically RFETs. On this basis the role of this project will be to go one step further and explore the third dimension while state-of-the-art devices are still bound to the FEOL integration. From Phase 2 onward the co-design with memory elements will be explored.

A06

2D Field-Effect Transistors
(X. Feng, M. Lemme)

2D materials promise further device scaling and improvement of device performance and are already considered for future electronics. The group at AMO in Aachen is a leader in the research on practical devices based on 2D materials. Since here the channel material is decoupled from the wafer, integration into the BEOL is a natural choice although some significant issues remain to be solved. Within the TRR this project will supply lateral devices with different performance levels.

TU Dresden

A07

Vertical Perovskite Field-Effect Transistors
(Y. Vaynzof, M. Mohammadi)

For high frequency applications a vertical device architecture with very small dimensions is more beneficial compared to lateral device architectures. Perovskite materials have had great success in the field of improved solar cells. However, their application to other semiconductor devices is not explored in the same way. They offer distinct benefits in terms of integration technology for the BEOL. Based on the leading activities in perovskite solar cells at TUD and the integration know-how at AMO (M. Mohammadi), here a novel, vertical device concept utilizing perovskites will be at the center of the research. Within the TRR the project will demonstrate the concept in Phase 1 and supply vertical devices with medium to high performance.

TU Dresden