Title: Xilinx University Program: Technology update for educators and researchers

Speaker: Cathal McCabe

Abstract: This talk will give an update on the Xilinx University Program, and updates on the latest Xilinx software and upcoming silicon devices.
New XUP hardware platforms for teaching, student projects and research, including the new Xilinx Kria SoM will be covered, along with the XACC research program and recent XACC Tech Talk summer series. FPGA researchers interested in High End Computing can find out how the can benefit from the XACC program and how to apply.
The winners of the 2021 Xilinx Open Hardware University Design Competition will be announced along with details for the 2022 edition of the competition.
Updates on software including Vivado and Vitis, and silicon updates will cover Zynq Ultrascale+ RFSoC and details on the recently announced Versal ACAP families.

Date: 01.09.2021

Time: 4:00 PM - 4:25 PM (CEST)

Affiliation: Xilinx University Program

Bio:  Cathal McCabe is a senior engineer in the Xilinx CTO department, where he manages the Xilinx University Program in EMEA. As part of this role, he delivers training workshops for academics on the latest Xilinx tools and technologies. Most recently he has been working on the PYNQ project – a Python-based open-source productivity environment for Xilinx platforms. He is also responsible for academic and industrial partnerships, and special initiatives in the region. Before joining Xilinx, Cathal worked for the Science and Technology Facilities Council (STFC) in the UK, where he was the Europractice manager for FPGA, Embedded, and ESL design tools and flows and responsible for training on related topics.

Cologne Chip

Title: Novel GateMate FPGA Architecture

Speaker: Michael Gude


The GateMate FPGA family of Cologne Chip is based on a completely novel architecture combining a special logic element called Cologne Programmable Element (CPE) with a smart routing engine with improved switchboxes. Furthermore, arbitrary size Multipliers are usable. Memory aware applications can use block dual-port SRAMs with bit widths from 1 to 80 bits. Even bit-wise enable is feasible. General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5 Volt. GPIOs can be configured as single-ended or LVDS differential type. Furthermore a high speed SERDES interface is available.

The new approach includes dedicated features resulting in reduced cost of ownership: Three application modes for the same device by changing core voltage, leading to low inventory. Users can choose between low power, economy or speed. Furthermore only two supply voltages are required and applicable in any order and only two signal layers on PCB are necessary. The ball grid package is optimized for low size of 15x15 mm and high pin count starting at 324 balls. GateMate FPGA is manufactured in Germany by Globalfoundries 28 nm SLP (Super Low Power) process. Due to manufacturing in Europe, there is no danger of trade restrictions or high taxation.

GateMate FPGA addresses all application requirements of small to medium size FPGAs. Very low power and speed applications are feasible. Logic capacity, power consumption, package size and PCB compatibility are combined with lowest cost in industry making the devices well suited from University projects to high volume applications. Because of the outstanding circuit size/cost ratio, even novel applications now can use the benefits of FPGAs.

Date: 02.09.2021

Time: 4:00 PM - 4:25 PM (CEST)

michael gude

Affiliation: CEO, Cologne Chip

Bio:  Michael Gude achieved a Diploma and PhD from the University of Aachen (RWTH) in electrical engineering. He was involved in research and development from the early days of microprocessors. Already in 1989 Michael used FPGAs from Actel. Michael is founder and CEO of several technology companies. One of them is Cologne Chip AG, which began its successful business in 1995. The semiconductor company is well known for its reliable telecommunication chips ever since. His strong dedication to research and development resulted in many patents worldwide. Now he and his engineering team take the next step: Introducing GateMate FPGA with a fully novel architecture. The FPGA chips are ideally suited for low power applications and offer the ideal combination of logic capacity, power consumption and package size.


Title: FPGA Architectures for a Heterogeneous World

Speaker: José Alvarez


The continuous increase in complexity, high data bandwidth requirements and low latency for a wide variety of developing applications demands FPGA solutions that provide agility, flexibility and programmability for products that are optimized for the domain, customized for specific markets and able to change with evolving requirements. Heterogenous integration in semiconductors continues to revolutionize the way FPGAs are manufactured today for configurable, customized solutions that include not just hardware but the software infrastructure to deploy in various devices across the custom logic spectrum. This talk will present updates on heterogenous integration at the semiconductor device level as well as at the system and software levels.

Date: 03.09.2021

Time: 6:30 PM - 6:55 PM (CEST)

José Alvarez

Affiliation: Sr Director CTO Office Lead, Intel PSG

Bio:  José Roberto Alvarez is Senior Director at Intel Programmable Solutions Group in San Jose, California, where he leads the Technology Strategy and Innovation CTO Office, defining and implementing long term FPGA research strategy and roadmaps. He started his career at Philips Laboratories and throughout his career he has been deeply engaged in architecting, designing and implementing technology products for a variety of industries including broadcast, embedded, consumer, post-production and computer graphics for companies including Philips, S3 Graphics, Broadcom, Maxim, Xilinx, and four successful start-ups in Silicon Valley. His research interests include FPGA advanced architectures and development tools, heterogenous system integration, optical interfaces, immersive media technologies and AI/ML domain-specific architectures. His work has been granted 53 patents.


Title: Stratus HLS: from convenience to necessity

Speaker: Souradip Sarkar

Abstract: Innovation in the field of cloud computing, high resolution multimedia, mobile networks, sensor technologies, edge AI and automotive SoCs has given rise to entirely new set of applications and industry verticals. All this rests on the pillars of hardware infrastructure and software platforms. The single most complex challenge is evolution of novel applications and requirement for continuously evolving quality of results. From an architect's, designer's and verification engineer's perspective better design reuse, flexibility and efficient design space sweeps are critical in the quest to find the optimal solution. In this talk, I shall focus on EDA infrastructure and technology (within Cadence Stratus HLS product line) in the domain of field programmable logic, that enables design flexibility, mitigate cost pressure, and enable faster time to market.

Date: 03.09.2021

Time: 4:00 PM - 4:20 PM (CEST)

Souradip Sarkar

Affiliation: Cadence Design Systems, Senior Principle Product Engineer

Bio:  Souradip Sarkar is a senior principal product engineer at Cadence Design Systems. Prior to this, he has been a research scientist at Bell Labs, Nokia. He has held researcher positions at Agilent Technologies, Intel Exascience labs (at IMEC) and Ghent University. His primary research interests lie in the areas of design and test of multiprocessor SoCs, EDA tools, on-chip and off-chip communication networks, 3D integration and signal processing for communication systems. He received his PhD degree and from the School of Electrical Engineering and Computer Science, Washington State University in 2010 and 2007 respectively.


Title: Helicopter to Venus – Importance of TMR

Speaker: Robert Efram


Radiation-induced soft errors —“glitches”— are known to cause in-flight failures in FPGAs. These radiations are commonly seen in space but of late, observed on earth surface in noisy environments as well. The voltage disturbance will most likely be transient; an unwanted transient signal is known as a single event transient (SET). However, synchronous logic—such as state machines, registers and memory—can store and propagate the transient error, which can result in design failure. Such an error is known as a single event upset.

For many years, designers working in aerospace and defence are aware of the need to protect their designs against SEUs. Today, engineers working in other market sectors are adopting techniques to guard against SEUs. We are increasingly dependent on the safe operation in automotive systems and medical equipment, but high reliability is no longer purely a safety-critical issue; it is a growing concern even for networking and industrial automation systems that demand high quality-of-service and uptime.  There are design-based techniques that engineers can use to detect and protect against soft errors in normal sequential logic FPGA structures.  The technique differ based on types of FPGAs e.g. SRAM based / flash based etc.

This presentation will discuss these challenges and the benefits of TMR, Safe FSMs, Inferred ECC Ram, and Triplicated I/O implementations in FPGAs which can help reduce the impact of radiation induced soft error.

Date: 01.09.2021

Time: 6:30 PM - 6:50 PM (CEST)

Affiliation: Staff Applications Consultant for FPGA Implementation Products, Synopsys

Bio:  Bob Efram brings over 25 years of experience in the field of FPGA design in his role as Staff Applications Consultant for FPGA Implementation products at Synopsys. Before joining Synopsys, he was an Field Applications Engineer for FPGA Products at Synplicity, Inc. He has a BSEE and MSEE in Digital Design and Signal Processing from the University of California, Santa Barbara.

Fraunhofer IPMS

Title: Multi-Protocol Automotive Communication Subsystem

Speaker: Marcus Pietzsch

Abstract: We recently see a shift in automotive communication from classical distributed local in-car sub networks towards higher integration levels and multi-protocol tunneling using backbone based architectures to match the needs of upcoming ADAS applications like situation awareness and automated driving. Therefore reliable real-time capable high-speed busses are used which support operation at certain automotive safety integrity levels (ASIL) levels providing failsafe operation. This talk introduces an automotive communication subsystem for vendor independent FPGA capable of bridging classic automotive communication protocols over time sensitive networking (TSN) capable IEEE802.X links while maintaining strict timing restrictions required by the peripheral communication nodes

Date: 02.09.2021

Time: 6:40 PM - 6:55 PM (CEST)

Marcus Pietzsch

Affiliation: Group Manager - IPCores and ASICs (IPCA), Fraunhofer IPMS

Bio:  Marcus Pietzsch is with Fraunhofer IPMS, Dresden Germany since 2006. He studied electrical engineering at the TU Dresden and gained large experience in hardware and software co-design of embedded systems as a scientist. Since 2018 he is the leader of a group for IP Cores & ASICs design at Fraunhofer IPMS.

Maxeler Technologies

Title: From FPGAs to next wave of Dataflow chips

Speaker: Tobias Becker

Abstract: With a continued trend towards unconventional compute architectures, we see the emergence of novel programmable devices. The next generation of Maxeler dataflow targets extreme FPGAs that are less configurable, but cheaper and more scalable. Static dataflow becomes a defining programming model to deliver maximum performance at scale. This model, combined with AI-oriented compute units, delivers unprecedented speed and efficiency for HPC applications.

Date: 03.09.2021

Time: 4:20 PM - 4:30 PM (CEST)

Tobias Becker

Affiliation: VP Of Research and Development, Maxeler Technologies

Bio:  Dr. Tobias Becker is the VP of Research and Development at Maxeler Technologies where he coordinates various internal and collaborative research efforts as well as managing internal teams. Before joining Maxeler he held positions as a researcher in the Department of Computing at Imperial College London, and at Xilinx, Inc. He received a Ph.D. degree in Computing from Imperial College London and a Dipl. Ing. degree in Electrical Engineering from the Karlsruhe Institute of Technology (KIT).


Title: Scaling your application on a cluster of FPGAs: The InAccel integrated platform

Speaker: Christoforos Kachris

Abstract: How can users deploy and scale their FPGA-based application instantly on the cloud and in data centers? How can we eliminate the complexity of FPGA and allow seamless deployment as easy as the CPUs? In this talk we will show how users can deploy and scale their FPGA applications on a Kubernetes cluster as easy as if it was typical processors. We will show how users can seamlessly invoke the accelerated functions on a cluster of FPGAs and how multiple users can share the available FPGA resources easier than ever. Finally we will show how users can perform DevOps on FPGAs on the cloud with an integrated framework.

Date: 01.09.2021

Time: 6:50 PM - 7:00 PM (CEST)

Christofoross Kachris

Affiliation: CEO, InAccel

Bio:  Christoforos (Chris) Kachris is the CEO and co-founder of InAccel. He is in charge of the business development, strategy and innovation for the easy deployment and scaling of FPGAs on data centers through a unique FPGA integrated orchestrator. Chris holds a Ph.D. from Delft University of Technology on Computer Engineering. He is the co-author of more than 80 scientific papers (conference, journals and book chapters) on the domain FPGAs and computer architecture and his work has been cited on more than 2000 publications. He is the editor of the book "Hardware Accelerators in Data Centers" and he brings more than 20 years of experience on the domain FPGAs. His works has been awarded on several FPGA contests (OpenHardware 2019,2017, Xilinx Design contest).