Mike Hutton (Google, USA): Accelerating Deep Learning with TPUs

Abstract:  Google introduced the first Tensor Processor in a 2017 ISCA paper.  The TPU is a domain-specific, coarse-grained VLIW processor with dedicated matrix-multiply units designed to accelerate machine learning workloads over large-scale data.  Multiple generations later, current TPUs now support both inference and training, massive compute power (more than 100 petaflops training systems) and drive all of the internal machine learning efforts at Google.  This presentation will overview the TPU and its evolution, including some of the design principles and decisions shaping the architecture.

Bio:  Mike Hutton received his BMath in Computer Science in 1989 and MMath in Computer Science in 1991, both from the University of Waterloo, and his Ph.D. in Computer Science in 1997 from the University of Toronto.   Across 20 years at Altera, Tabula and Intel, he worked on FPGA architecture, CAD and applications.  He is author of 30 published papers and 100+ US patents in these areas, has served on multiple FPGA and CAD program committees, and is a former Associate Editor for IEEE Transactions on VLSI.  In 2018 he joined Google to lead a group focused on performance modeling for the Tensor Processor (TPU) architecture.

Cecilia Metra (University of Bologna, Italy): Safety, Reliability and Resiliency Challenges to Enable Highly Autonomous Intelligent Systems

Abstract:  Intelligent systems, capable of taking autonomous decisions based on AI algorithms, are becoming more and more widespread in several application fields (autonomous robots, autonomous vehicles, smart factories, smart agriculture, etc.). This thanks to their possible adoption to replace and/or collaborate with humans in harsh environments (hospitals, mines, space, etc.) and/or in difficult jobs (goods delivery, surveillance, etc.). They are complex systems, requiring intelligence at the edge (for low-latency data acquisition and processing), in the network, and up to the cloud and related services. Since such autonomous intelligent systems are in a closed collaboration with human beings and/or the health of human beings may depend on their operation, the need to guarantee their functional safety, reliability and resiliency with respect to hazardous conditions emerges. Enabling to increase the autonomy level of such intelligent systems, thus moving towards a smarter world, mandates to satisfy stronger requirements in terms of their functional safety, reliability and resiliency. Safety, reliability and resiliency challenges to enable highly autonomous intelligent systems will be discussed.

Cecilia Metra

BioCecilia Metra is a full Professor and the Deputy President of the School of Engineering at the University of Bologna, Italy, where she has worked since 1991, and from which she received a PhD in electronic engineering and computer science. In 2002, she was visiting faculty consultant for Intel Corporation.

She was the 2019 President of the IEEE Computer Society, and she is 2021 IEEE Director-Elect/Division V Delegate-Elect (2022 and 2023 IEEE Director/Division V Delegate).

She is a member of the IEEE Young Professionals Committee (2021), the IEEE European Public Policy Committee - EPPC (2020-2021), the IEEE Smart Village Governing Board (2020-2021), the Systems Council Advisory Committee (2020-2021), the IEEE Conferences Committee (2021-2022). She is the Chair of the EPPC Working Group on ICT, and the Co-Chair of the IEEE Digital Reality Initiative Project on “Reliable, Safe, Secure and Time Deterministic Intelligent Systems”.

She was the Editor-in-Chief of the IEEE Transactions on Emerging Topics in Computing and of Computing Now, and the Associate Editor-in-Chief of IEEE Transactions on Computers. She contributed to numerous IEEE international conferences/symposia/workshops as General/Program Chair/Co-Chair and technical program committee member. She has published extensively on design for test, reliability, safety and resiliency of integrated circuits and systems.

She is an IEEE Fellow, IEEE CS Golden Core Member, and a member of the IEEE Honor Society IEEE-HKN. She has received two Meritorious Service Awards and six Certificates of Appreciation from the IEEE CS.

Michaela Blott (Xilinx Research, Ireland): Innovative FPGA Approaches to AI

Abstract:  Deep Learning is penetrating an ever-increasing number of applications such as communications. However, the associated computational complexity and memory demands are outpacing Moore’s Law ability to cater for the necessary performance scalability. Specialization of hardware architectures is one of the most successful approaches to address the sky-high requirements, and with FPGAs, this can take its most creative form. During this talk, we will take a look at some of the new emerging applications and discuss how various forms of innovative specializations in hardware architecture with FPGAs impact flexibility, performance and efficiency.
Michaela Blott

Bio: Michaela Blott is a Fellow at Xilinx Research in Dublin, Ireland, where she heads a team of international scientists driving exciting research into new application domains for Xilinx devices, such as machine learning. She earned a PhD from Trinity College Dublin and her Master’s degree from the University of Kaiserslautern, Germany, and brings over 25 years of leading edge computer architecture and advanced FPGA and board design, in research institutions (ETH Zurich and Bell Labs) and development organizations. She is highly active in the research community as industrial advisor to numerous EU projects, serves on technical program committees, and most recently received the Women in Tech Award 2019.