Asif Ali Khan




Visitor's Address

+49 (0)351 463 463 43729

+49 (0)351 463 39995

Helmholtzstrasse 18, BAR III55

Curriculum Vitae

Asif Ali Khan received his Bachelor and Master degrees in Computer Systems Engineering from Pakistan in 2012 and 2015 respectively. He has a background in Computer Architecture, embedded systems and parallel processing. At the Chair for Compiler Construction, he is working on systems with heterogeneous memories. He aims to:

  1. Realize a  multi-core architecture with heterogeneous memories that meets the multi-faceted memory requirements (such as bandwidth, latency, energy etc) of various applications.
  2. Expose this memory heterogeneity to the application programmer by providing language and compilation support.
Student Thesis Topics

I work on the intersection of optimizing compilers and emerging memory/compute architectures. If you are interested to do your Bachelor/Master/Diploma thesis in these domains, I could help you in supervising topics similar to the following. In case you have a different topic in mind that is related, please feel free to reach out and we will talk about it.

  • Compilation for unconventional architectures:

Emerging non-volatile memory technologies promise to solve the capacity, latency, and energy issues of conventional architecture. They, however, have their own limitations. In this project, you will work on developing/extending a compiler that hides/mitigate these limitations and exploit the full potential of these novel architectures. As a target system, you will work on systems with Racetrack Memories (don't worry if you do not have knowledge of the technology itself).

RTMs are sequential. New compilers are needed to minimize the latency of sequential accesses and improve performance.

Requirements: Good knowledge of C/C++
Beneficial: basic compiler knowledge, LLVM
Related work: A recent thesis (MA) and a similar publication


  • Optimizing Data Movement in the Memory Hierarchy:
Data movement in the memory hierarchy is expensive and memory systems, generally, are blind to running applications. In this project, you will analyze the applications statically to find out which hierarchy level best suits the memory requirement of the current input program (there are tools that can be used) and place it accordingly. If done correctly, you may guarantee a 100% cache hit-rate.

Requirements: Good knowledge of C/C++ 

In case of interest do not hesitate to contact me:


  • 2021

  • Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jeronimo Castrillon, Jian-Jia Chen, "BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory" (to appear), Proceedings of the 58th Annual Design Automation Conference (DAC'21), ACM, Jul 2021. [Bibtex & Downloads]
  • 2020

  • Asif Ali Khan, Hauke Mewes, Tobias Grosser, Torsten Hoefler, Jeronimo Castrillon, "Polyhedral Compilation for Racetrack Memories", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Special issue on Compilers, Architecture, and Synthesis of Embedded Systems (CASES'20), IEEE Press, vol. 39, no. 11, pp. 3968-3980, Oct 2020. [doi] [Bibtex & Downloads]
  • Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Improving the Performance of Block-based DRAM Caches via Tag-Data Decoupling", In IEEE Transactions on Computers, Oct 2020. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jeronimo Castrillon, "Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories", In ACM Transactions on Embedded Computing Systems (TECS), Association for Computing Machinery, vol. 19, no. 6, New York, NY, USA, Sep 2020. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Andrés Goens, Fazal Hameed, Jeronimo Castrillon, "Generalized Data Placement Strategies for Racetrack Memories", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 1502–1507, Mar 2020. (Video Presentation) [doi] [Bibtex & Downloads]
  • Robin Bläsing, Asif Ali Khan, Panagiotis Ch. Filippou, Chirag Garg, Fazal Hameed, Jeronimo Castrillon, Stuart S. P. Parkin, "Magnetic Racetrack Memory: From Physics to the Cusp of Applications within a Decade", In Proceedings of the IEEE, vol. 108, no. 8, pp. 1303-1321, Mar 2020. [doi] [Bibtex & Downloads]
  • 2019

  • Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jeronimo Castrillon, "ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0", In ACM Transactions on Architecture and Code Optimization (TACO), ACM, vol. 16, no. 4, pp. 56:1–56:23, New York, NY, USA, Dec 2019. [doi] [Bibtex & Downloads]
  • Joonas Multanen, Asif Ali Khan, Pekka Jääskeläinen, Fazal Hameed, Jeronimo Castrillon, "SHRIMP: Efficient Instruction Delivery with Domain Wall Memory", Proceedings of the International Symposium on Low Power Electronics and Design, ACM, pp. 6pp, New York, NY, USA, Jul 2019. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jeronimo Castrillon, "Optimizing Tensor Contractions for Embedded Devices with Racetrack Memory Scratch-Pads", Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory of Embedded Systems (LCTES), ACM, pp. 5–18, New York, NY, USA, Jun 2019. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart Parkin, Jeronimo Castrillon, "RTSim: A Cycle-accurate Simulator for Racetrack Memories", In IEEE Computer Architecture Letters, IEEE, vol. 18, no. 1, pp. 43–46, Jan 2019. [doi] [Bibtex & Downloads]
  • 2018

  • Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Performance and Energy Efficient Design of STT-RAM Last-Level-Cache", In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 26, no. 6, pp. 1059–1072, Jun 2018. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Fazal Hameed, Jeronimo Castrillon, "NVMain Extension for Multi-Level Cache Systems", Proceedings of the 10th RAPIDO Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 7:1–7:6, New York, NY, USA, Jan 2018. [doi] [Bibtex & Downloads]