Dr.-Ing. Asif Ali Khan

E-mail

Phone

Fax

Visitor's Address

asif_ali.khan@tu-dresden.de

+49 (0)351 463 43729

+49 (0)351 463 39995

Helmholtzstrasse 18, BAR III55

Curriculum Vitae

Asif Ali Khan received his Ph.D. degree from TU Dresden in 2022. He has a background in computer architecture, optimizing compilers, and emerging nonvolatile memory technologies. At the Chair for Compiler Construction, Asif has worked/is working on systems with heterogeneous memory technologies and their optimizations. More specifically, he has developed compilation and simulation tools and novel data and instruction placement strategies for racetrack memories. In the context of near-memory and in-memory computing, he has collaborated with others to accelerate real-world applications from the machine learning and bioinformatics domains. Asif has also contributed to developing software abstractions for non-von-Neumann computing paradigms.

Student Thesis Topics

I work on the intersection of optimizing compilers and emerging memory/compute architectures. If you are interested to do your Bachelor/Master/Diploma thesis in these domains, I could help you in supervising topics similar to the following. In case you have a different topic in mind that is related, please feel free to reach out and we will talk about it.

  • Compilation for non-von-Neumann architectures:

Data movement in von-Neumann computing systems consumes as high as 60% of the total system's energy. The novel compute-in-memory (CIM) paradigm completely eliminates data movement by exploiting the physical properties of the memory devices to implement various logic and compute operations in-place. Recent research has demonstrated implementing all logic operations and complex arithmetic operations like matrix-matrix multiplication and floating point arithmetic operations (see the figure below). Most often, CIM systems employ nonvolatile memory (NVM) technologies such as phase change memory (PCM), resistive RAM (RRAM), magnetic RAM (MRAM), and spintronics-based racetrack memories (RTMs). All these NVM technologies have their own strengths and limitations.

 

In this project, you will work on developing/extending a compiler that hides/mitigate these limitations and exploit the full potential of these novel architectures. As a starting point, you will use one of our in-house developed infrastructures targetting such systems.

Requirements: Good knowledge of C/C++
Beneficial:
basic compiler knowledge, LLVM, MLIR
Related work: A recent thesis (MA) and a publication

 

  • Simulation infrastructure for compute-in-memory systems

To quickly characterize and understand the various tradeoffs in CIM systems (see the description of the project above), it is imperative to have simulation tools that can model them. In this project, you will work on developing a gem5-based simulation infrastructure for CIM systems (similar to the following). The tools will enable the exploration of different NVM technologies at different memory hierarchy levels. Feel free to ping me for more details.

Requirements: Good knowledge of C/C++
Beneficial: basic computer architecture knowledge

 

  • Optimizing Data Movement in the Memory Hierarchy:
Data movement in the memory hierarchy is expensive and memory systems, generally, are blind to running applications. In this project, you will analyze the applications statically to find out which hierarchy level best suits the memory requirement of the current input program (there are tools that can be used) and place it accordingly. If done correctly, you may guarantee a 100% cache hit rate.

Requirements: Good knowledge of C/C++ 

In case of interest do not hesitate to contact me: asif_ali.khan@tu-dresden.de

Publications

  • 2023

  • Carlos Escuin, Asif Ali Khan, Pablo Ibáñez-Marín, Teresa Monreal, Jeronimo Castrillon, Víctor Viñals-Yúfera, "Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs" (to appear), In Proceeding: the 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA'23), 13 pp, Mar 2023. [Bibtex & Downloads]
  • 2022

  • Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jeronimo Castrillon, Jian-Jia Che, "ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees", In IEEE Transactions on Computers, pp. 1-14, Jul 2022. [doi] [Bibtex & Downloads]
  • Fazal Hameed, Asif Ali Khan, Sebastien Ollivier, Alex K. Jones, Jeronimo Castrillon, "DNA Pre-alignment Filter using Processing Near Racetrack Memory", In IEEE Computer Architecture Letters, IEEE, pp. 1–4, Jul 2022. [doi] [Bibtex & Downloads]
  • Carlos Escuin, Asif Ali Khan, Pablo Ibañez, Teresa Monreal, Victor Viñals, Jeronimo Castrillon, "HyCSim: A Rapid Design Space Exploration Tool for Emerging Hybrid Last-Level Caches", In Proceeding: DroneSE and RAPIDO: System Engineering for Constrained Embedded Systems, co-located with the 17th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Association for Computing Machinery, pp. 53–58, New York, NY, USA, Jun 2022. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, "Design and Code Optimization for Systems with Next-generation Racetrack Memories", PhD thesis, TU Dresden, 255 pp., Apr 2022. [Bibtex & Downloads]
  • Asif Ali Khan, Sebastien Ollivier, Stephen Longofono, Gerald Hempel, Jeronimo Castrillon, Alex K. Jones, "Brain-inspired Cognition in Next Generation Racetrack Memories", In ACM Transactions on Embedded Computing Systems (TECS), Association for Computing Machinery, New York, NY, USA, Mar 2022. [doi] [Bibtex & Downloads]
  • 2021

  • Joonas Iisakki Multanen, Kari Hepola, Asif Ali Khan, Jeronimo Castrillon, Pekka Jääskeläinen, "Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory", In IEEE Transactions on Computers, pp. 1-1, Oct 2021. [doi] [Bibtex & Downloads]
  • Adam Siemieniuk, Lorenzo Chelini, Asif Ali Khan, Jeronimo Castrillon, Andi Drebes, Henk Corporaal, Tobias Grosser, Martin Kong, "OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Press, vol. 41, no. 6, pp. 1674-1686, Aug 2021. [doi] [Bibtex & Downloads]
  • Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jeronimo Castrillon, Jian-Jia Chen, "BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory", Proceedings of the 58th Annual Design Automation Conference (DAC'21), ACM, pp. 1111–1116, Jul 2021. [doi] [Bibtex & Downloads]
  • Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "ALPHA: A Novel Algorithm-Hardware Co-design for Accelerating DNA Seed Location Filtering", In IEEE Transactions on Emerging Topics in Computing (IEEE TETC), 12 pp., Jun 2021. [doi] [Bibtex & Downloads]
  • Joonas Iisakki Multanen, Kari Hepola, Asif Ali Khan, Jeronimo Castrillon, Pekka Jaaskelainen, "Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory", In IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi] [Bibtex & Downloads]
  • 2020

  • Asif Ali Khan, Hauke Mewes, Tobias Grosser, Torsten Hoefler, Jeronimo Castrillon, "Polyhedral Compilation for Racetrack Memories", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Special issue on Compilers, Architecture, and Synthesis of Embedded Systems (CASES'20), IEEE Press, vol. 39, no. 11, pp. 3968–3980, Oct 2020. [doi] [Bibtex & Downloads]
  • Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Improving the Performance of Block-based DRAM Caches via Tag-Data Decoupling", In IEEE Transactions on Computers, vol. 70, no. 11, pp. 1914-1927, Oct 2020. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jeronimo Castrillon, "Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories", In ACM Transactions on Embedded Computing Systems (TECS), Association for Computing Machinery, vol. 19, no. 6, New York, NY, USA, Sep 2020. [doi] [Bibtex & Downloads]
  • Robin Bläsing, Asif Ali Khan, Panagiotis Ch. Filippou, Chirag Garg, Fazal Hameed, Jeronimo Castrillon, Stuart S. P. Parkin, "Magnetic Racetrack Memory: From Physics to the Cusp of Applications within a Decade", In Proceedings of the IEEE, vol. 108, no. 8, pp. 1303-1321, Mar 2020. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Andrés Goens, Fazal Hameed, Jeronimo Castrillon, "Generalized Data Placement Strategies for Racetrack Memories", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 1502–1507, Mar 2020. (Video Presentation) [doi] [Bibtex & Downloads]
  • 2019

  • Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jeronimo Castrillon, "ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0", In ACM Transactions on Architecture and Code Optimization (TACO), ACM, vol. 16, no. 4, pp. 56:1–56:23, New York, NY, USA, Dec 2019. [doi] [Bibtex & Downloads]
  • Joonas Multanen, Asif Ali Khan, Pekka Jääskeläinen, Fazal Hameed, Jeronimo Castrillon, "SHRIMP: Efficient Instruction Delivery with Domain Wall Memory", Proceedings of the International Symposium on Low Power Electronics and Design, ACM, 6pp, New York, NY, USA, Jul 2019. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jeronimo Castrillon, "Optimizing Tensor Contractions for Embedded Devices with Racetrack Memory Scratch-Pads", Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory of Embedded Systems (LCTES), ACM, pp. 5–18, New York, NY, USA, Jun 2019. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart Parkin, Jeronimo Castrillon, "RTSim: A Cycle-accurate Simulator for Racetrack Memories", In IEEE Computer Architecture Letters, IEEE, vol. 18, no. 1, pp. 43–46, Jan 2019. [doi] [Bibtex & Downloads]
  • 2018

  • Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Performance and Energy Efficient Design of STT-RAM Last-Level-Cache", In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 26, no. 6, pp. 1059–1072, Jun 2018. [doi] [Bibtex & Downloads]
  • Asif Ali Khan, Fazal Hameed, Jeronimo Castrillon, "NVMain Extension for Multi-Level Cache Systems", Proceedings of the 10th RAPIDO Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 7:1–7:6, New York, NY, USA, Jan 2018. [doi] [Bibtex & Downloads]