Fazal Hameed

portrait Sebastian Ertel




Visitor's Address


+49 (0)351 463 43729

+49 (0)351 463 39995

Georg-Schumann-Str. 7A
2nd floor, room 205
01187 Dresden


Curriculum Vitae

Fazal Hameed joined the compiler-construction group of Prof. Castrillon in March 2016. Before, he worked as a Post-doctoral researcher at the Chair of Dependable and Nano Computing (CDNC) Karlsruhe Institute of Technology (KIT), Germany. There, he mainly worked in the architecture group with a focus on memories. In the Chair of Compiler group, he is currently working on the development of a simulation framework to evaluate the performance, energy, and reliability of heterogenous multi-core system architecture. For this purpose, development of cross-layer  framework is in progress covering the entire abstraction stack including device, circuit, architectural, operating system, and upper software layers. The project includes development of system level architectures combining heterogenous logic and memory components, in particular with an increased heterogeneity within the future systems.

Fazal Hameed received his Ph.D. (Dr.-Ing.) in Computer Science from the Karlsruhe Institute of Technology (KIT) Germany in 2015. He received CODES+ISSS'13 best paper nomination for his work on DRAM cache management in multi-core systems. Mr. Hameed has also served as an external reviewer for major conferences in embedded systems and computer architecture.


Research Interests


-- Multi-core, cache, and memory architectures

-- Non-Volatile emerging memory technologies (STT-MRAM, PRAM, RRAM etc.).

-- High Performance Computing.

-- Efficient usage of heterogeneous architectures in the context of High Performance Computing and embedded systems.



  • 2018

  • Fazal Hameed, Asif Ali Khan, Jeronimo Castrillon, "Performance and Energy Efficient Design of STT-RAM Last-Level-Cache" , In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 26, no. 6, pp. 1059–1072, Jun 2018. [doi] [Bibtex & Downloads]
  • Fazal Hameed, Jeronimo Castrillon, "STT-RAM Aware Last-Level-Cache Policies for Simultaneous Energy and Performance Improvement" , Proceedings of the 9th Annual Non-Volatile Memories Workshop (NVMW 2018), Mar 2018. [Bibtex & Downloads]
  • Asif Ali Khan, Fazal Hameed, Jeronimo Castrillon, "NVMain Extension for Multi-Level Cache Systems" , Proceedings of the 10th RAPIDO Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 7:1–7:6, New York, NY, USA, Jan 2018. [doi] [Bibtex & Downloads]
  • 2017

  • Fazal Hameed, Christian Menard, Jeronimo Castrillon, "Efficient STT-RAM Last-Level-Cache Architecture to replace DRAM Cache" , Proceedings of the International Symposium on Memory Systems (MemSys 17), ACM, pp. 141–151, New York, NY, USA, Oct 2017. [doi] [Bibtex & Downloads]
  • Fazal Hameed, Jeronimo Castrillon, "Rethinking On-chip DRAM Cache for Simultaneous Performance and Energy Optimization" , Proceedings of the 2017 Design, Automation and Test in Europe conference (DATE), EDA Consortium, pp. 362–367, Mar 2017. [doi] [Bibtex & Downloads]

S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril, F. Hameed, and M. B. Tahoori, "VAET-STT: A Variation Aware STT-MRAM Analysis and Design Space Exploration Tool", in IEEE Transcactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017

2016 and Before

For my publications in the previous years, please have a look at my Google Scholar profile.