cfaed Publications

@Article{hameed_tcad22,
author = {Fazal Hameed and Jeronimo Castrillon},
title = {{BlendCache}: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture},
doi = {10.1109/TCAD.2022.3161198},
issn = {0278-0070},
issue = {12},
pages = {5288--5298},
url = {https://ieeexplore.ieee.org/document/9739802},
volume = {41},
abstract = {Racetrack memory (RTM) is a promising nonvolatile memory that provides multi-bit storage cells achieving a higher area and leakage energy efficiency compared to contemporary volatile and non-volatile memories. These features make RTM a potential candidate to be used as a Last-Level-Cache (LLC). One drawback of the multi-bit RTM cell is the serialized access to the stored data, resulting in a shift penalty to access a particular bit within the cell. This overhead is particularly critical for LLC tags, for which prior RTM designs place tags either in SRAM or in single-bit RTM cells. While this avoids shifting, these designs require large number of leaky cells incurring high energy consumption. To address this problem, this paper proposes an energy efficient RTM design called BlendCache that efficiently stores the tags in the leakage optimized multi-bit RTM cells. To reduce the RTM shift penalty of these cells, BlendCache exploits the spatial locality of programs by maximizing accesses to nearby locations in RTM. Employing 32-bit RTM cells for a single-core, BlendCache reduces the energy consumption by 20.8\% and area by 15.2\% compared to the state-of-the-art while its impact on performance is negligible. For a 4-core system, the energy improvement translates to 35.9\% with 3\% performance degradation.},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD)},
month = dec,
project = {tracesymm,cfaed},
year = {2022},
}