Here is the list of domestic and international MSc/BSc theses and SHK/WHK Studentarbeit projects carried in our chair. You can find the available positions here.

2021

  • Compiler Toolchains for Deep Learning Workloads on Embedded Platforms (Max Sponner, Infineon).
  • Light-Weight FPGA-Based Accelerator Design for Iris Recognition (Dennis Klar, TU Dresden).
  • High-Throughput Design of Approximate Operators in FPGAs (Muhammad Zaid, TU Dresden).
  • Energy efficiency optimizations on a CGRA using RFETs (Hasan Shakir, TU Dresden).
  • Parallel FPGA routing (Mohamed Bouaziz, TU Dresden/Università di Trento).
  • FPGA-based Artificial Neural Network Accelerator (Mohammad Naeim, TU Dresden/KU Leuven University).
  • Exploration of Cross-Layer Approximation for Artificial Neural Networks on FPGA (Balaji Venkataramana, BITS Pilani India).
  • Accelerated Hardware for ECG Pre-processing
    • Student: Debabrata Chaudhury, BITS Pilani, Pilani, India
    • Staff Supervisor: Dr. Siva Satyendra Sahoo
  • Designing Deep Reinforcement Learning Architecture on FPGAs
    • Student: Divyansh Choudhary, Indian Institute of Technology, Indore, India.
    • Staff Supervisor: Dr. Siva Satyendra Sahoo
  • Deep Reinforcement Learning-based Control of Smart Energy Buildings
    • Student: Nemath Ahmed, Indian Institute of Technology, Indore, India.
    • Staff Supervisor: Dr. Siva Satyendra Sahoo
  • Exploring Machine Learning for Logic Synthesis (Yasasvi V. Peruvemba, Indian Institute of Technology).
  • Hardware Trojan design in CMOS and emerging nano-technologies (Desai Mohil Sandip, BITS Pilani India).
  • Neuromorphic computing using state-of-the-art components (Ishika Bhattacharya, BITS Pilani India).

2020

  • Energy-Efficient CGRA Design for Bio-Signal Processing (Mohammad Aasim Ekhtiyar, TU Dresden).
  • Machine Learning in Heterogeneous IoT Distributed Network (Aditya Lohana, BITS Pilani India).
  • Implementation of energy-efficient DNNs for edge computing
    • Student: Suresh Nambi, BITS Pilani, Pilani, India.
    • Staff Supervisor: Salim Ullah
    • Related Publications:
      • Nambi, Suresh, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, and Akash Kumar. "Expan (n) d: Exploring posits for efficient artificial neural network design in fpga-based systems." arXiv preprint arXiv:2010.12869 (2020).
  • Deep Reinforcement Learning on FPGAs:
  • Cross-Layer Low Power Design for Heterogeneous Embedded Systems
    • Student: Nisarg Sheth, BITS Pilani, Goa, India.
    • Staff Supervisor: Dr. Siva Satyendra Sahoo
    • Related Publications:
      • Siva Satyendra Sahoo, Akash Kumar, "CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021 (accepted for publication).
  • Exploration of Prospects of Reconfigurable Nanotechnologies in Hardware Security (Abhiroop Bhattacharjee, BITS Pilani India).
  • Hyperdimensional Computing - A study of algorithms and hardware realizations (Vignesh Nagarajan, BITS Pilani India).

2019

  • Evaluation of OpenCV based hardware accelerators on PYNQ framework running on Ultra96 board by implementing image processing applications (Mizanur Rahman, TU Dresden).
  • Architecture and CAD for Emerging Technologies (Pallab Nath, Indian Institute of Technology).
  • Low bit-width Quantization Schemes for DNNs (Siddharth Gupta, Indian Institute of Technology).

2018

  • Approximate Signed Multiplier Blocks for FPGA (Hendrik Schmidl, TU Dresden).
  • Designing Reconfigurable Approximate Multipliers (Patil Siddhant Vitthal, 2018).
  • Hardware Trojan Design in Context of Emerging Reconfigurable Nanotechnology (Dipika Badri, BITS Pilani India).
  • Neural Network Design on FPGA (Namrata Chakka, India Vellore Institute of Technology).

2017

  • Designing Reconfigurable Approximate Arithmetic Architecture on FPGA (Markus Krause, TU Dresden).
  • Physical Synthesis and Design For Reconfigurable Transistors (Ansh Rupani, TU Dresden).
  • Multi-processor Emulation Platform on FPGA (Sanjeev Sripadraj Murthy, BITS Pilani India).
  • Emulation Platform for Wildly Heterogeneous Chips (Divya Jain, BITS Pilani India).
  • Buil-in Self-test for FPGA designs
    • Student: Kshitij Shrivastava, BITS Pilani, Hyderabad, India.
    • Staff Supervisor: Siva Satyendra Sahoo