Following is a list of grants acquired since the start of the chair.
- SecuReFET: Secure Circuits through inherent Reconfigurable FET
- PRÄKLIMA FASSADE: Predictive self-learning facade design for smart energy buildings
- HANS: A framework for distributed ANN inference on heterogeneous edge devices
- Labview System-on-chip design methodology, 280,000 Euros, 2019, National Instruments Industry project.
- Runtime reconfigurable approximate architecture (ReAp)
- Emulation platform for wildly heterogeneous chips, 40,000 Euro, 2017. Orchestration seed grant.
- FPGA Floorplanner for partially reconfigurable systems, 103,500 Euro, 2016. Huawei Industry project.
- Enabling very large-scale integration for novel materials, 45,000 Euro, 2016. Orchestration seed grant.
Photo: Katharina Knaut
The general theme of research in the chair is design, analysis and resource management of low-power and fault-tolerant embedded multiprocessor systems. In particular, following projects are being carried out.
Reconfigurable approximate computing systems
In this project, the intention is to develop system architectures that are able to reduce the energy consumption by a few orders of magnitude albeit with slight loss of accuracy. While this field of research, often known as inaccurate or approximate computing, is not new, in this project in particular, designing reconfigurable approximate computing architectures can be looked at. The main contribution of this work would be designing computing elements whose accuracy-energy trade-off can be tuned at run-time.
While providing a general reduction in overall energy consumption, with such reconfigurable components, the energy consumption can be further minimized when more inaccuracy can be tolerated in the system, e.g. when the input data may not have any interesting features to capture. While almost all the work done in this domain hitherto focusses only on the computation elements, studying integrated components including the memory elements has the potential of giving higher gains.
Thermal-aware design for reliable 3D architectures
Most multi-core systems are implemented in a 2D IC, which seems to become complex, inefficient and uneconomic with the advancement in the process technology due to inefficient scalability of interconnects with respect to the logic. A viable alternative to cater for such limitations of interconnects is a 3D IC, where multiple layers of logic can be stacked vertically and they can be connected by small high speed vertical interconnects. Integration of various types of cores in a 3D IC provides several advantages, but at the cost of increased power density within the chip which results in serious thermal problems, affecting performance and reliability of the system.
While there are few works that target to mitigate the thermal issues in 3D multi-core architectures, very few target real-time applications with strict timing deadlines. In this project, investigations are performed to identify a promising 3D multi-core architecture to support a set of real-time applications and to devise techniques for thermal-aware mapping of different simultaneous active applications while guaranteeing their performance (throughput) constraints.
Reliable multiprocessor systems
It is becoming a major challenge to deal with the decreasing reliability and increasing faults with decreasing transistor size, aggressive voltage scaling and higher operating frequencies. Designing systems to work despite such faults and such that they can still meet the throughput requirements of applications is a major challenge that needs to be addressed.
I like to design systems that are able to withstand faults without external user-intervention while still satisfying high performance constraints. In particular, I study fault tolerance from multiple angles, e.g. the impact of a fault on different applications, cost of re-starting an application from start, cost of check-pointing, how to check-point a multiprocessor system, how a fault-tolerant multiprocessor system platform should be designed etc. While some of these problems have been studied for uniprocessor systems, there are hardly any solutions available for multiprocessor systems. The dependency between hardware and software poses new challenges in a multiprocessor environment.
Fault-Tolerant reconfigurable heterogeneous MPSoC
Nowadays, the demand for FPGA-based embedded systems with higher performance in terms of powerful computational ability and fast processing time is rising rapidly. Employing heterogeneous platforms with different dedicated hardware accelerators and specialized processors can improve the overall performance of the system by effectively boosting up specific computational intensive and sequential tasks. Nevertheless, the number of applications that need to be supported by one system is increasing. It is impractical to integrate dedicated hardware accelerators for all applications onto a single FPGA chip because the FPGA resources are limited. More importantly, the applications are not likely to operate at the same time, which makes the accelerators under-utilized.
In this project, a partially reconfigurable heterogeneous multiprocessor system-on-chip (MPSoC) architecture is developed that can be customized at run-time depending on the application requirements. Such architecture brings together the benefits of both worlds – FPGA fabric and heterogeneous MPSoC. A tile-based heterogeneous MPSoC platform is used where some tiles consist of pure reconfigurable fabric which can be configured at run-time. While most of the tasks of an application can be performed by different types of processors available in the MPSoC, some of the tasks which take a long time in software can be speeded by configuring the programmable tiles appropriately. Another benefit which comes with such architecture is that of fault-tolerance. If some processor tiles in the MPSoC platforms are rendered unusable at any point in time, the reconfigurable tiles can be configured to replace the functionality of the existing processor.
PR-HMPSoC: a Versatile Partially Reconfigurable Heterogeneous Multiprocessor System-on-Chip for Dynamic FPGA-based Embedded Systems. The proposed architecture has three interconnect planes. One component can belong to more than one plane. The wires in dashed lines belong to Mixed Plane. The connections from Master Controller, MDM and MPMC (optional) to all Tiles are not shown for simplicity. (click to enlarge)
© IEEE. Link to full paper (PDF).