- Chair of Compiler Construction
- Chair of Emerging Electronic Technologies
- Chair of Knowledge-Based Systems
- Chair of Molecular Functional Materials
- Chair of Network Dynamics
- Chair of Organic Devices
- Chair of Processor Design
- About-News
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Here are Prof. Akash Kumar's profile pages:
Publications
- 2025
- 193. Zahra Ebrahimi, Maryam Eslami, Xun Xiao, Akash Kumar, "X-DINC: Toward Cross-Layer ApproXimation for theDistributed and In-Network ACceleration of Multi-Kernel Applications", In Future Generation Computer Systems, Elsevier BV, vol. 172, pp. 107864, Nov 2025. [doi]        [Bibtex & Downloads]
                X-DINC: Toward Cross-Layer ApproXimation for theDistributed and In-Network ACceleration of Multi-Kernel Applications×ReferenceZahra Ebrahimi, Maryam Eslami, Xun Xiao, Akash Kumar, "X-DINC: Toward Cross-Layer ApproXimation for theDistributed and In-Network ACceleration of Multi-Kernel Applications", In Future Generation Computer Systems, Elsevier BV, vol. 172, pp. 107864, Nov 2025. [doi] Bibtex@article{Ebrahimi_2025, title={X-DINC: Toward Cross-Layer ApproXimation for theDistributed and In-Network ACceleration of Multi-Kernel Applications}, volume={172}, ISSN={0167-739X}, url={http://dx.doi.org/10.1016/j.future.2025.107864}, DOI={10.1016/j.future.2025.107864}, journal={Future Generation Computer Systems}, publisher={Elsevier BV}, author={Ebrahimi, Zahra and Eslami, Maryam and Xiao, Xun and Kumar, Akash}, year={2025}, month=nov, pages={107864} }DownloadsX-DINC_FGCS [PDF] Permalink
- 192. Yuhao Liu, Salim Ullah, Akash Kumar, "BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs", In Proceeding: 2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 276-276, 2025. [doi]        [Bibtex & Downloads]
                BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs×ReferenceYuhao Liu, Salim Ullah, Akash Kumar, "BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs", In Proceeding: 2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 276-276, 2025. [doi] Bibtex@INPROCEEDINGS{11008950,
 author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
 booktitle={2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
 title={BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs},
 year={2025},
 volume={},
 number={},
 pages={276-276},
 keywords={Quantization (signal);Neuromorphic engineering;Computational modeling;Approximate computing;Artificial neural networks;Transforms;Complexity theory;Hardware acceleration;Field programmable gate arrays;fpga;hardware accelerator;approximate computing;kolmogorov-arnold network},
 doi={10.1109/FCCM62733.2025.00036}}DownloadsNo Downloads available for this publication Permalink
- 191. Max Sponner, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "PEAX - A Model Augmentation Framework for Adaptive Techniques and Embedded Applications", Proceedings of the 2025 Workshop on Compilers, Deployment, and Tooling for Edge AI, ACM, Jan 2025.        [Bibtex & Downloads]
                PEAX - A Model Augmentation Framework for Adaptive Techniques and Embedded Applications×ReferenceMax Sponner, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "PEAX - A Model Augmentation Framework for Adaptive Techniques and Embedded Applications", Proceedings of the 2025 Workshop on Compilers, Deployment, and Tooling for Edge AI, ACM, Jan 2025. Bibtex@inproceedings{Max_CODAI_2025, series={CODAI ’25}, title={PEAX - A Model Augmentation Framework for Adaptive Techniques and Embedded Applications}, url={}, DOI={}, booktitle={Proceedings of the 2025 Workshop on Compilers, Deployment, and Tooling for Edge AI}, publisher={ACM}, author={Max Sponner and Lorenzo Servadei and Bernd Waschneck and Robert Wille and Akash Kumar}, year={2025}, month=jan, pages={}, collection={CODAI ’25} }DownloadsPEAX_for_CODAI_2024-12-19 [PDF] Permalink
- 190. Yuhao Liu, Salim Ullah, Akash Kumar, "Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators", In Proceeding: 2025 26th International Symposium on Quality Electronic Design (ISQED), pp. 1-9, 2025. [doi]        [Bibtex & Downloads]
                Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators×ReferenceYuhao Liu, Salim Ullah, Akash Kumar, "Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators", In Proceeding: 2025 26th International Symposium on Quality Electronic Design (ISQED), pp. 1-9, 2025. [doi] Bibtex@INPROCEEDINGS{11014376,
 author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
 booktitle={2025 26th International Symposium on Quality Electronic Design (ISQED)},
 title={Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators},
 year={2025},
 volume={},
 number={},
 pages={1-9},
 keywords={Runtime;Quantization (signal);Accuracy;Neural networks;Memory architecture;Systolic arrays;Delays;Racetrack memory;Object tracking;Clocks},
 doi={10.1109/ISQED65160.2025.11014376}}DownloadsBitSys_ISQED [PDF] Permalink
- 2024
- 189. Maryam Eslami, Yuhao Liu, Salim Ullah, Mostafa E. Salehi, Reshad Hosseini, Seyed Ahmad Mirsalari, Akash Kumar, "MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 16, no. 4, pp. 333–336, Dec 2024. [doi]        [Bibtex & Downloads]
                MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks×ReferenceMaryam Eslami, Yuhao Liu, Salim Ullah, Mostafa E. Salehi, Reshad Hosseini, Seyed Ahmad Mirsalari, Akash Kumar, "MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 16, no. 4, pp. 333–336, Dec 2024. [doi] Bibtex@article{Eslami_2024, title={MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks}, volume={16}, ISSN={1943-0671}, url={http://dx.doi.org/10.1109/LES.2024.3444921}, DOI={10.1109/les.2024.3444921}, number={4}, journal={IEEE Embedded Systems Letters}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Eslami, Maryam and Liu, Yuhao and Ullah, Salim and Salehi, Mostafa E. and Hosseini, Reshad and Ahmad Mirsalari, Seyed and Kumar, Akash}, year={2024}, month=dec, pages={333–336} }DownloadsNo Downloads available for this publication Permalink
- 188. Behnaz Ranjbar, Paul Justen, Akash Kumar, "GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems" (to appear), In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), October 2024. [doi]        [Bibtex & Downloads]
                GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems×ReferenceBehnaz Ranjbar, Paul Justen, Akash Kumar, "GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems" (to appear), In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), October 2024. [doi] Bibtex@article{Ranjbar_2024,
 doi = {10.1109/LES.2024.3466268)},
 year = 2024,
 month = {October},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 author = {Behnaz Ranjbar and Paul Justen and Akash Kumar},
 title = {GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems},
 journal = {IEEE Embedded Systems Letters}
 }Downloads2024-LES [PDF] Permalink
- 187. H. Mehrabian, A. Kumar, "FedPoll: A Novel Robustness and Communication-Efficient Aggregation Method", In Proceeding: 2nd IEEE International Conference on Federated Learning Technologies and Applications (FLTA24), pp. 1-9, Sep 2024.        [Bibtex & Downloads]
                FedPoll: A Novel Robustness and Communication-Efficient Aggregation Method×ReferenceH. Mehrabian, A. Kumar, "FedPoll: A Novel Robustness and Communication-Efficient Aggregation Method", In Proceeding: 2nd IEEE International Conference on Federated Learning Technologies and Applications (FLTA24), pp. 1-9, Sep 2024. Bibtex@INPROCEEDINGS{mehrabian_flta24, author={Hamidreza Mehrabian and Akash Kumar}, booktitle={2nd IEEE International Conference on Federated Learning Technologies and Applications (FLTA24)}, title={FedPoll: A Novel Robustness and Communication-Efficient Aggregation Method}, year={2024}, month={sep}, volume={}, number={}, pages={1-9} }Downloads45_6717 [PDF] Permalink
- 186. Yuhao Liu, Salim Ullah, Akash Kumar, "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators", In Proceeding: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp. 220–220, May 2024. [doi]        [Bibtex & Downloads]
                BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators×ReferenceYuhao Liu, Salim Ullah, Akash Kumar, "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators", In Proceeding: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp. 220–220, May 2024. [doi] Bibtex@inproceedings{Liu_2024, title={BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators}, url={http://dx.doi.org/10.1109/fccm60383.2024.00042}, DOI={10.1109/fccm60383.2024.00042}, booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Liu, Yuhao and Ullah, Salim and Kumar, Akash}, year={2024}, month=may, pages={220–220} }DownloadsFCCM_Poster_Final_3 [PDF] Permalink
- 185. Max Sponner, Bernd Waschneck, Akash Kumar, "Adapting Neural Networks at Runtime: Current Trends in At-Runtime Optimizations for Deep Learning", In ACM Computing Surveys, Association for Computing Machinery (ACM), Apr 2024. [doi]        [Bibtex & Downloads]
                Adapting Neural Networks at Runtime: Current Trends in At-Runtime Optimizations for Deep Learning×ReferenceMax Sponner, Bernd Waschneck, Akash Kumar, "Adapting Neural Networks at Runtime: Current Trends in At-Runtime Optimizations for Deep Learning", In ACM Computing Surveys, Association for Computing Machinery (ACM), Apr 2024. [doi] Bibtex@article{Sponner_2024, title={Adapting Neural Networks at Runtime: Current Trends in At-Runtime Optimizations for Deep Learning}, ISSN={1557-7341}, url={http://dx.doi.org/10.1145/3657283}, DOI={10.1145/3657283}, journal={ACM Computing Surveys}, publisher={Association for Computing Machinery (ACM)}, author={Sponner, Max and Waschneck, Bernd and Kumar, Akash}, year={2024}, month=apr }DownloadsNo Downloads available for this publication Permalink
- 184. Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming", In ACM Transactions on Reconfigurable Technology and Systems (TRETS), pp. 1–28, April 2024.        [Bibtex & Downloads]
                AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming×ReferenceSiva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming", In ACM Transactions on Reconfigurable Technology and Systems (TRETS), pp. 1–28, April 2024. Bibtex@article{siva_trets_2024,
 title={AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming},
 author={Sahoo, Siva Satyendra and Ullah, Salim and Kumar, Akash},
 journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
 volume={},
 number={},
 pages={1--28},
 year={2024},
 month={April}
 }DownloadsNo Downloads available for this publication Permalink
- 183. Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "Utilizing Machine Learning Techniques for Worst-Case Execution Time Estimation on GPU Architectures", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–15, March 2024. [doi]        [Bibtex & Downloads]
                Utilizing Machine Learning Techniques for Worst-Case Execution Time Estimation on GPU Architectures×ReferenceVikash Kumar, Behnaz Ranjbar, Akash Kumar, "Utilizing Machine Learning Techniques for Worst-Case Execution Time Estimation on GPU Architectures", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–15, March 2024. [doi] Bibtex@article{VKumar_2024,
 doi = {10.1109/ACCESS.2024.3379018},
 year = 2024,
 month = {March},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--15},
 author = {Vikash Kumar and Behnaz Ranjbar and Akash Kumar},
 title = {Utilizing Machine Learning Techniques for Worst-Case Execution Time Estimation on GPU Architectures},
 journal = {{IEEE} Access}
 }DownloadsNo Downloads available for this publication Permalink
- 182. Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2024. [doi]        [Bibtex & Downloads]
                Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems×ReferenceVikash Kumar, Behnaz Ranjbar, Akash Kumar, "Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2024. [doi] Bibtex@INPROCEEDINGS{behnaz2024date,
 author={Kumar, Vikash and Ranjbar, Behnaz and Kumar, Akash},
 booktitle={2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
 title={Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems},
 year={2024},
 month={Mar.},
 doi = {10.23919/DATE58400.2024.10546654},
 organization={IEEE}}Downloads2024-DATE [PDF] Permalink
- 181. Paul Jungmann, Julia Poray, Akash Kumar, "Analytical Uncertainty Propagation in Neural Networks", In IEEE Transactions on Neural Networks and Learning Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–14, 2024. [doi]        [Bibtex & Downloads]
                Analytical Uncertainty Propagation in Neural Networks×ReferencePaul Jungmann, Julia Poray, Akash Kumar, "Analytical Uncertainty Propagation in Neural Networks", In IEEE Transactions on Neural Networks and Learning Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–14, 2024. [doi] Bibtex@article{Jungmann_2024, title={Analytical Uncertainty Propagation in Neural Networks}, ISSN={2162-2388}, url={http://dx.doi.org/10.1109/tnnls.2023.3347156}, DOI={10.1109/tnnls.2023.3347156}, journal={IEEE Transactions on Neural Networks and Learning Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Jungmann, Paul and Poray, Julia and Kumar, Akash}, year={2024}, pages={1–14} }DownloadsNo Downloads available for this publication Permalink
- 180. G. Noble, S. Nalesh, S. Kala, Akash Kumar, "Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects", In Alexandria Engineering Journal, vol. 91, pp. 84-94, 2024. [doi]        [Bibtex & Downloads]
                Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects×ReferenceG. Noble, S. Nalesh, S. Kala, Akash Kumar, "Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects", In Alexandria Engineering Journal, vol. 91, pp. 84-94, 2024. [doi] Bibtex@article{NOBLE202484,
 title = {Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects},
 journal = {Alexandria Engineering Journal},
 volume = {91},
 pages = {84-94},
 year = {2024},
 issn = {1110-0168},
 doi = {https://doi.org/10.1016/j.aej.2024.01.075},
 url = {https://www.sciencedirect.com/science/article/pii/S1110016824001145},
 author = {G. Noble and S. Nalesh and S. Kala and Akash Kumar},
 keywords = {Accelerator, FPGA, Outer product, Sparse matrix multiplication, SpGEMM, Quantization},
 }DownloadsNo Downloads available for this publication Permalink
- 179. Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar, "QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]        [Bibtex & Downloads]
                QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit×ReferenceNeha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar, "QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] Bibtex@article{Ashar_2024, title={QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit}, ISSN={2169-3536}, url={http://dx.doi.org/10.1109/ACCESS.2024.3379906}, DOI={10.1109/access.2024.3379906}, journal={IEEE Access}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Ashar, Neha and Raut, Gopal and Trivedi, Vasundhara and Vishvakarma, Santosh Kumar and Kumar, Akash}, year={2024}, pages={1–1} }DownloadsNo Downloads available for this publication Permalink
- 178. Nima Kavand, Armin Darjani, Giulio Galderisi, Jens Trommer, Thomas Mikolajick, Akash Kumar, "REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024.        [Bibtex & Downloads]
                REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks×ReferenceNima Kavand, Armin Darjani, Giulio Galderisi, Jens Trommer, Thomas Mikolajick, Akash Kumar, "REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024. Bibtex@inproceedings{kavand2024redcap, title={REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks}, author={Kavand, Nima and Darjani, Armin and Galderisi, Giulio and Trommer, Jens and Mikolajick, Thomas, and Kumar, Akash}, booktitle={2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, year={2024}, organization={IEEE} }DownloadsNo Downloads available for this publication Permalink
- 177. Niladri Bhattacharjee, Viktor Havel, Suruchi Kumari, Nima Kavand, Jorge Navarro Quijada, Akash Kumar, Thomas Mikolajick, Jens Trommer, "Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024.        [Bibtex & Downloads]
                Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology×ReferenceNiladri Bhattacharjee, Viktor Havel, Suruchi Kumari, Nima Kavand, Jorge Navarro Quijada, Akash Kumar, Thomas Mikolajick, Jens Trommer, "Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024. Bibtex@inproceedings{bhattacharjee2024dynamic, title={Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology}, author={Bhattacharjee, Niladri and Havel, Viktor and Kumari, Suruchi and Kavand, Nima and Navarro Quijada, Jorge and Kumar, Akash and Mikolajick, Thomas and Trommer, Jens}, booktitle={2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, year={2024}, organization={IEEE} }DownloadsNo Downloads available for this publication Permalink
- 176. Zahra Ebrahimi, Akash Kumar, "GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient ProcessiNg at the Edge", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]        [Bibtex & Downloads]
                GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient ProcessiNg at the Edge×ReferenceZahra Ebrahimi, Akash Kumar, "GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient ProcessiNg at the Edge", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] Bibtex@article{Ebrahimi_2024, title={GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient ProcessiNg at the Edge}, ISSN={1937-4151}, url={http://dx.doi.org/10.1109/TCAD.2024.3383349}, DOI={10.1109/tcad.2024.3383349}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Ebrahimi, Zahra and Kumar, Akash}, year={2024}, pages={1–1} }DownloadsGREEN_TCAD3383349_camera-ready [PDF] Permalink
- 175. Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "ESOMICS: ML-Based Timing Behaviour Analysis For Efficient Mixed-Criticality System Design", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]        [Bibtex & Downloads]
                ESOMICS: ML-Based Timing Behaviour Analysis For Efficient Mixed-Criticality System Design×ReferenceVikash Kumar, Behnaz Ranjbar, Akash Kumar, "ESOMICS: ML-Based Timing Behaviour Analysis For Efficient Mixed-Criticality System Design", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] Bibtex@article{Kumar_2024, title={ESOMICS: ML-Based Timing Behaviour Analysis For Efficient Mixed-Criticality System Design}, ISSN={2169-3536}, url={http://dx.doi.org/10.1109/ACCESS.2024.3396225}, DOI={10.1109/access.2024.3396225}, journal={IEEE Access}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Kumar, Vikash and Ranjbar, Behnaz and Kumar, Akash}, year={2024}, pages={1–1} }DownloadsNo Downloads available for this publication Permalink
- 174. Elias Trommer, Bernd Waschneck, Akash Kumar, "Smaller together: Groupwise Encoding of Sparse Neural Networks", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024.        [Bibtex & Downloads]
                Smaller together: Groupwise Encoding of Sparse Neural Networks×ReferenceElias Trommer, Bernd Waschneck, Akash Kumar, "Smaller together: Groupwise Encoding of Sparse Neural Networks", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. Bibtex@article{Elias_TCAD_2024, title={Smaller together: Groupwise Encoding of Sparse Neural Networks}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Trommer, Elias and Waschneck, Bernd and Kumar, Akash}, year={2024}, pages={1–1} }Downloadsieee_tcad_smaller_together [PDF] Permalink
- 173. Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Thwarting GNN-based attacks against logic locking", In IEEE Transactions on Information Forensics and Security, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]        [Bibtex & Downloads]
                Thwarting GNN-based attacks against logic locking×ReferenceArmin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Thwarting GNN-based attacks against logic locking", In IEEE Transactions on Information Forensics and Security, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] Bibtex@article{Darjani_2024, title={Thwarting GNN-based attacks against logic locking}, ISSN={1556-6021}, url={http://dx.doi.org/10.1109/TIFS.2024.3431991}, DOI={10.1109/tifs.2024.3431991}, journal={IEEE Transactions on Information Forensics and Security}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Darjani, Armin and Kavand, Nima and Rai, Shubham and Kumar, Akash}, year={2024}, pages={1–1} }DownloadsNo Downloads available for this publication Permalink
- 172. Elias Trommer, Bernd Waschneck, Akash Kumar, "Fast Retraining of Approximate CNNs for High Accuracy", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]        [Bibtex & Downloads]
                Fast Retraining of Approximate CNNs for High Accuracy×ReferenceElias Trommer, Bernd Waschneck, Akash Kumar, "Fast Retraining of Approximate CNNs for High Accuracy", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] Bibtex@article{Trommer_2024, title={Fast Retraining of Approximate CNNs for High Accuracy}, ISSN={1937-4151}, url={http://dx.doi.org/10.1109/TCAD.2024.3483091}, DOI={10.1109/tcad.2024.3483091}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Trommer, Elias and Waschneck, Bernd and Kumar, Akash}, year={2024}, pages={1–1} }Downloadstcad_torchapprox_submitted_version [PDF] Permalink
- 171. Max Sponner, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "Efficient Post-Training Augmentation for Adaptive Inference in Heterogeneous and Distributed IoT Environments", Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), 2024. (Best poster award)        [Bibtex & Downloads]
                Efficient Post-Training Augmentation for Adaptive Inference in Heterogeneous and Distributed IoT Environments×ReferenceMax Sponner, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "Efficient Post-Training Augmentation for Adaptive Inference in Heterogeneous and Distributed IoT Environments", Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), 2024. (Best poster award) Bibtex@InProceedings{max_samos24,
 author = {Max Sponner and Lorenzo Servadei and Bernd Waschneck and Robert Wille and Akash Kumar},
 title = {Efficient Post-Training Augmentation for Adaptive Inference in Heterogeneous and Distributed IoT Environments},
 booktitle = {Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)},
 year = {2024},
 volume = {},
 pages = {},
 organization = {IEEE},
 doi = {},
 
 }Downloads2403 [07957V1] Permalink
- 170. Max Sponner, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "Leveraging Temporal Patterns: Automated Augmentation to Create Temporal Early Exit Networks for Efficient Edge AI", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]        [Bibtex & Downloads]
                Leveraging Temporal Patterns: Automated Augmentation to Create Temporal Early Exit Networks for Efficient Edge AI×ReferenceMax Sponner, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "Leveraging Temporal Patterns: Automated Augmentation to Create Temporal Early Exit Networks for Efficient Edge AI", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] Bibtex@article{Sponner_2024, title={Leveraging Temporal Patterns: Automated Augmentation to Create Temporal Early Exit Networks for Efficient Edge AI}, ISSN={2169-3536}, url={http://dx.doi.org/10.1109/ACCESS.2024.3497158}, DOI={10.1109/access.2024.3497158}, journal={IEEE Access}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sponner, Max and Servadei, Lorenzo and Waschneck, Bernd and Wille, Robert and Kumar, Akash}, year={2024}, pages={1–1} }DownloadsNo Downloads available for this publication Permalink
- 2023
- 169. Rohit Agrawal, Kapil Ahuja, Dhaarna Maheshwari, Mohd Ubaid Shaikh, Mohamed Bouaziz, Akash Kumar, "Parallel FPGA Routers with Lagrange Relaxation", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, November 2023. [doi]        [Bibtex & Downloads]
                Parallel FPGA Routers with Lagrange Relaxation×ReferenceRohit Agrawal, Kapil Ahuja, Dhaarna Maheshwari, Mohd Ubaid Shaikh, Mohamed Bouaziz, Akash Kumar, "Parallel FPGA Routers with Lagrange Relaxation", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, November 2023. [doi] Bibtex@article{Agrawal_2023,
 doi = {10.1109/access.2023.3328769},
 url = {https://doi.org/10.1109%2Faccess.2023.3328769},
 year = 2023,
 month={November},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Rohit Agrawal and Kapil Ahuja and Dhaarna Maheshwari and Mohd Ubaid Shaikh and Mohamed Bouaziz and Akash Kumar},
 title = {Parallel {FPGA} Routers with Lagrange Relaxation},
 journal = {{IEEE} Access}
 }DownloadsManuscript[2] [PDF] Permalink
- 168. Mark Wijtvliet, Henk Corporaal, Akash Kumar, "Blocks: Auf dem Weg zu Energieeffizienten, Grobkörnigen, Rekonfigurierbaren Architekturen (CGRA)", Springer International Publishing, November 2023. [doi]        [Bibtex & Downloads]
                Blocks: Auf dem Weg zu Energieeffizienten, Grobkörnigen, Rekonfigurierbaren Architekturen (CGRA)×ReferenceMark Wijtvliet, Henk Corporaal, Akash Kumar, "Blocks: Auf dem Weg zu Energieeffizienten, Grobkörnigen, Rekonfigurierbaren Architekturen (CGRA)", Springer International Publishing, November 2023. [doi] Bibtex@book{Wijtvliet_2023,
 doi = {10.1007/978-3-031-36650-5},
 url = {https://doi.org/10.1007%2F978-3-031-36650-5},
 year = 2023,
 month={November},
 publisher = {Springer International Publishing},
 author = {Mark Wijtvliet and Henk Corporaal and Akash Kumar},
 title = {Blocks: Auf dem Weg zu Energieeffizienten, Grobkörnigen, Rekonfigurierbaren Architekturen ({CGRA})}
 }DownloadsNo Downloads available for this publication Permalink
- 167. Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations", Chapter in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer International Publishing, pp. 89–119, Oct 2023. [doi]        [Bibtex & Downloads]
                Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations×ReferenceSalim Ullah, Siva Satyendra Sahoo, Akash Kumar, "Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations", Chapter in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer International Publishing, pp. 89–119, Oct 2023. [doi] Bibtex@incollection{Ullah_2023,
 doi = {10.1007/978-3-031-19568-6_4},
 url = {https://doi.org/10.1007%2F978-3-031-19568-6_4},
 year = 2023,
 month = {oct},
 publisher = {Springer International Publishing},
 pages = {89--119},
 author = {Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
 title = {Designing Resource-Efficient Hardware Arithmetic for {FPGA}-Based Accelerators Leveraging Approximations and Mixed Quantizations},
 booktitle = {Embedded Machine Learning for Cyber-Physical, {IoT}, and Edge Computing}
 }DownloadsNo Downloads available for this publication Permalink
- 166. Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators", In ACM Trans. Embed. Comput. Syst., Association for Computing Machinery, vol. 22, no. 5s, New York, NY, USA, Sep 2023. [doi]        [Bibtex & Downloads]
                AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators×ReferenceSiva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators", In ACM Trans. Embed. Comput. Syst., Association for Computing Machinery, vol. 22, no. 5s, New York, NY, USA, Sep 2023. [doi] Bibtex@article{10.1145/3609096,
 author = {Sahoo, Siva Satyendra and Ullah, Salim and Kumar, Akash},
 title = {AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators},
 year = {2023},
 issue_date = {October 2023},
 publisher = {Association for Computing Machinery},
 address = {New York, NY, USA},
 volume = {22},
 number = {5s},
 issn = {1539-9087},
 url = {https://doi.org/10.1145/3609096},
 doi = {10.1145/3609096},
 journal = {ACM Trans. Embed. Comput. Syst.},
 month = sep,
 articleno = {101},
 numpages = {26},
 keywords = {Monte Carlo Tree Search, AI-based exploration, Approximate computing, circuit synthesis, automated hardware design, arithmetic operator design, computer arithmetic}
 }DownloadsAxOTreeS-cases-esweek-tecs-2023 [PDF] Permalink
- 165. Max Sponner, Julius Ott, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "Temporal Patience: Efficient Adaptive Deep Learning for Embedded Radar Data Processing", In ACM Workshop on Compilers, Deployment, and Tooling for Edge AI (CODAI), September 2023.        [Bibtex & Downloads]
                Temporal Patience: Efficient Adaptive Deep Learning for Embedded Radar Data Processing×ReferenceMax Sponner, Julius Ott, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "Temporal Patience: Efficient Adaptive Deep Learning for Embedded Radar Data Processing", In ACM Workshop on Compilers, Deployment, and Tooling for Edge AI (CODAI), September 2023. Bibtex@article{sponner2023temporal,
 title={Temporal Patience: Efficient Adaptive Deep Learning for Embedded Radar Data Processing},
 author={Max Sponner and Julius Ott and Lorenzo Servadei and Bernd Waschneck and Robert Wille and Akash Kumar},
 journal={ACM Workshop on Compilers, Deployment, and Tooling for Edge AI (CODAI)},
 year={2023},
 month={September}
 }Downloadstemporal [PDF] Permalink
- 164. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers", In IEEE Embedded Systems Letters, pp. 1-1, 2023. [doi]        [Bibtex & Downloads]
                High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers×ReferenceYuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers", In IEEE Embedded Systems Letters, pp. 1-1, 2023. [doi] Bibtex@ARTICLE{10261986,
 author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
 journal={IEEE Embedded Systems Letters},
 title={High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers},
 year={2023},
 volume={},
 number={},
 pages={1-1},
 doi={10.1109/LES.2023.3298736}}DownloadsESL_LB_CASES_2023 Camera ready [PDF] Permalink
- 163. Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi]        [Bibtex & Downloads]
                NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories×ReferenceYuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi] Bibtex@article{Zhao_2023,
 doi = {10.1109/les.2023.3299202},
 url = {https://doi.org/10.1109%2Fles.2023.3299202},
 year = 2023,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Yuankang Zhao and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
 title = {{NvMISC}: Towards an {FPGA}-Based Emulation Platform for {RISC}-V and Non-Volatile Memories},
 journal = {{IEEE} Embedded Systems Letters}
 }DownloadsNvMISC_Towards_an_FPGA-Based_Emulation_Platform_for_RISC-V_and_Non-Volatile_Memories_ESL [PDF] Permalink
- 162. Behnaz Ranjbar, Alireza Ejlali, Akash Kumar, "Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems", Springer, September 2023.        [Bibtex & Downloads]
                Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems×ReferenceBehnaz Ranjbar, Alireza Ejlali, Akash Kumar, "Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems", Springer, September 2023. Bibtex@book{Ranjbar2023Book,
 title={Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems},
 author={Ranjbar, Behnaz and Ejlali, Alireza and Kumar, Akash},
 year={2023},
 month = {September},
 url={https://doi.org/10.1007/978-3-031-38960-3},
 publisher={Springer}
 }DownloadsNo Downloads available for this publication Permalink
- 161. Behnaz Ranjbar, Ali Hosseinghorban, Akash Kumar, "ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi]        [Bibtex & Downloads]
                ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems×ReferenceBehnaz Ranjbar, Ali Hosseinghorban, Akash Kumar, "ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi] Bibtex@inproceedings{Ranjbar_DAC_2023,
 year = 2023,
 month = {July},
 author = {Behnaz Ranjbar and Ali Hosseinghorban and Akash Kumar},
 title = {ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems},
 booktitle = {Design Automation Conference (DAC)},
 pages={1-6},
 doi={10.1109/DAC56929.2023.10248007}
 }Downloads1215_Camera_Ready_Paper [PDF] Permalink
- 160. Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Discerning the Limitations of GNN-Based Attacks on Logic Locking", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi]        [Bibtex & Downloads]
                Discerning the Limitations of GNN-Based Attacks on Logic Locking×ReferenceArmin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Discerning the Limitations of GNN-Based Attacks on Logic Locking", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi] Bibtex@inproceedings{Darjani_DAC_2023,
 year = 2023,
 month = {July},
 author = {Armin Darjani and Nima Kavand and Shubham Rai and Akash Kumar},
 title = {Discerning the Limitations of GNN-Based Attacks on Logic Locking},
 booktitle = {Design Automation Conference (DAC)},
 pages={1-6},
 doi={10.1109/DAC56929.2023.10247847}
 }DownloadsDAC2023_Cirrostrato [PDF] Permalink
- 159. Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators", Proceedings of the Great Lakes Symposium on VLSI 2023, ACM, Jun 2023. [doi]        [Bibtex & Downloads]
                CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators×ReferenceSalim Ullah, Siva Satyendra Sahoo, Akash Kumar, "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators", Proceedings of the Great Lakes Symposium on VLSI 2023, ACM, Jun 2023. [doi] Bibtex@inproceedings{Ullah_2023,
 doi = {10.1145/3583781.3590222},
 url = {https://doi.org/10.1145%2F3583781.3590222},
 year = 2023,
 month = {jun},
 publisher = ,
 author = {Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
 title = {{CoOAx}: Correlation-aware Synthesis of {FPGA}-based Approximate Operators},
 booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023}
 }DownloadsApplication_specific_AI_inference_on_FPGAs-5 [PDF] Permalink
- 158. Raghul Saravanan, Sathwika Bavikadi, Shubham Rai, Akash Kumar, Sai Manoj Pudukotai Dinakarrao, "Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications", In Proceeding: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2023.        [Bibtex & Downloads]
                Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications×ReferenceRaghul Saravanan, Sathwika Bavikadi, Shubham Rai, Akash Kumar, Sai Manoj Pudukotai Dinakarrao, "Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications", In Proceeding: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2023. Bibtex@inproceedings{Rai_2023,
 year = 2023,
 month = {may},
 publisher = ,
 author = {Raghul Saravanan and Sathwika Bavikadi and Shubham Rai and Akash Kumar and Sai Manoj Pudukotai Dinakarrao},
 title = {Reconfigurable {FET} Approximate Computing-Based Accelerator for Deep Learning Applications},
 booktitle = {IEEE International Symposium on Circuits and Systems ({ISCAS})}
 }DownloadsNo Downloads available for this publication Permalink
- 157. Elias Trommer, Bernd Waschneck, Akash Kumar, "Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks", In Proceeding: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, May 2023.        [Bibtex & Downloads]
                Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks×ReferenceElias Trommer, Bernd Waschneck, Akash Kumar, "Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks", In Proceeding: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, May 2023. Bibtex@inproceedings{Trommer_DDECS,
 year = 2023,
 month = {may},
 publisher = ,
 author = {Elias Trommer and Bernd Waschneck and Akash Kumar},
 title = {Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks},
 booktitle = {International Symposium on Design and Diagnostics of Electronic Circuits and Systems ({DDECS})}
 }DownloadsNo Downloads available for this publication Permalink
- 156. Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers", In IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, May 2023. [doi]        [Bibtex & Downloads]
                Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers×ReferenceNima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers", In IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, May 2023. [doi] Bibtex@ARTICLE{Kavand2023,
 author={Kavand, Nima and Darjani, Armin and Rai, Shubham and Kumar, Akash},
 journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
 title={Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers},
 year={2023},
 month = {May},
 volume={},
 number={},
 pages={1-1},
 doi={10.1109/TCSII.2023.3275983}}DownloadsRFET_Compressor_TCASII_brief (5) [PDF] Permalink
- 155. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi]        [Bibtex & Downloads]
                NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs×ReferenceYuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi] Bibtex@INPROCEEDINGS{10196610,
 author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
 booktitle={2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
 title={NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs},
 year={2023},
 volume={},
 number={},
 pages={85-92},
 doi={10.1109/IPDPSW59300.2023.00026}}DownloadsRAW2023-NetPU-M [PDF] Permalink
- 154. Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed Elkacem Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski, Maciej Wiatr, "Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors", In Proceeding: Design, Automation and Test in Europe Conference (DATE), IEEE/ACM, April 2023.        [Bibtex & Downloads]
                Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors×ReferenceJens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed Elkacem Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski, Maciej Wiatr, "Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors", In Proceeding: Design, Automation and Test in Europe Conference (DATE), IEEE/ACM, April 2023. Bibtex@inproceedings{Rai_DATE_2023,
 year = 2023,
 month = {April},
 publisher = ,
 author = {Jens Trommer and Niladri Bhattacharjee and Thomas Mikolajick and Sebastian Huhn and Marcel Merten and Mohammed Elkacem Djeridane and Muhammad Hassan and Rolf Drechsler and Shubham Rai and Nima Kavand and Armin Darjani and Akash Kumar and Violetta Sessi and Maximilian Drescher and Sabine Kolodinski and Maciej Wiatr},
 title = {Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors},
 booktitle = {Design, Automation and Test in Europe Conference ({DATE})}
 }DownloadsDATE_2023_Cirrostrato [PDF] Permalink
- 153. Behnaz Ranjbar, Amit Kumar Singh, Siva Satyendra Sahoo, Piotr Dziurzanski, Akash Kumar, "Power Management of Multicore Systems", Chapter in Handbook of Computer Architecture, Springer Nature Singapore, pp. 1–33, 2023. [doi]        [Bibtex & Downloads]
                Power Management of Multicore Systems×ReferenceBehnaz Ranjbar, Amit Kumar Singh, Siva Satyendra Sahoo, Piotr Dziurzanski, Akash Kumar, "Power Management of Multicore Systems", Chapter in Handbook of Computer Architecture, Springer Nature Singapore, pp. 1–33, 2023. [doi] Bibtex@incollection{Ranjbar_2023,
 doi = {10.1007/978-981-15-6401-7_55-1},
 url = {https://doi.org/10.1007%2F978-981-15-6401-7_55-1},
 year = 2023,
 publisher = {Springer Nature Singapore},
 pages = {1--33},
 author = {Behnaz Ranjbar and Amit Kumar Singh and Siva Satyendra Sahoo and Piotr Dziurzanski and Akash Kumar},
 title = {Power Management of Multicore Systems},
 booktitle = {Handbook of Computer Architecture}
 }DownloadsNo Downloads available for this publication Permalink
- 152. Behnaz Ranjbar, Florian Klemme, Paul R. Genssler, Hussam Amrouch, Jinhyo Jung, Shail Dave, Hwisoo So, Kyongwoo Lee, Aviral Shrivastava, Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Francky Catthoor, Dwaipayan Biswas, Akash Kumar, "Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level", In Proceeding: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-10, April 2023. [doi]        [Bibtex & Downloads]
                Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level×ReferenceBehnaz Ranjbar, Florian Klemme, Paul R. Genssler, Hussam Amrouch, Jinhyo Jung, Shail Dave, Hwisoo So, Kyongwoo Lee, Aviral Shrivastava, Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Francky Catthoor, Dwaipayan Biswas, Akash Kumar, "Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level", In Proceeding: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-10, April 2023. [doi] Bibtex@inproceedings{Ranjbar_SS_DATE_2023,
 year = 2023,
 month = {April},
 pages={1-10},
 author = {Behnaz Ranjbar and Florian Klemme and Paul R. Genssler and Hussam Amrouch and Jinhyo Jung and Shail Dave and Hwisoo So and Kyongwoo Lee and Aviral Shrivastava and Ji-Yung Lin and Pieter Weckx and Subrat Mishra and Francky Catthoor and Dwaipayan Biswas and Akash Kumar},
 title = {Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level},
 booktitle = {Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
 doi={10.23919/DATE56975.2023.10137182}
 }DownloadsNo Downloads available for this publication Permalink
- 151. Behnaz Ranjbar, Ali Hosseinghorban, Akash Kumar, "Motivating Agent-Based Learning For Bounding Time in Mixed-Criticality Systems", In Proceeding: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-2, April 2023. [doi]        [Bibtex & Downloads]
                Motivating Agent-Based Learning For Bounding Time in Mixed-Criticality Systems×ReferenceBehnaz Ranjbar, Ali Hosseinghorban, Akash Kumar, "Motivating Agent-Based Learning For Bounding Time in Mixed-Criticality Systems", In Proceeding: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-2, April 2023. [doi] Bibtex@inproceedings{Ranjbar_DATE_2023,
 year = 2023,
 month = {April},
 pages={1-2},
 author = {Behnaz Ranjbar and Ali Hosseinghorban and Akash Kumar},
 title = {Motivating Agent-Based Learning For Bounding Time in Mixed-Criticality Systems},
 booktitle = {Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
 doi={10.23919/DATE56975.2023.10137189}
 }Downloads2023-DATE [PDF] Permalink
- 150. Zahra Ebrahimi, Muhammad Zaid, Mark Wijtvliet, Akash Kumar, "RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 712–725, Mar 2023. [doi]        [Bibtex & Downloads]
                RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency×ReferenceZahra Ebrahimi, Muhammad Zaid, Mark Wijtvliet, Akash Kumar, "RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 712–725, Mar 2023. [doi] Bibtex@article{Ebrahimi_2023,
 doi = {10.1109/tcad.2022.3184928},
 url = {https://doi.org/10.1109%2Ftcad.2022.3184928},
 year = 2023,
 month = {mar},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 volume = {42},
 number = {3},
 pages = {712--725},
 author = {Zahra Ebrahimi and Muhammad Zaid and Mark Wijtvliet and Akash Kumar},
 title = {{RAPID}: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
 }DownloadsTCAD_RAPID_long_version [PDF] Permalink
- 149. Shubham Rai, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 914–927, Mar 2023. [doi]        [Bibtex & Downloads]
                Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits×ReferenceShubham Rai, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 914–927, Mar 2023. [doi] Bibtex@article{Rai_2023,
 doi = {10.1109/tcad.2022.3184633},
 url = {https://doi.org/10.1109%2Ftcad.2022.3184633},
 year = 2023,
 month = {mar},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 volume = {42},
 number = {3},
 pages = {914--927},
 author = {Shubham Rai and Alessandro Tempia Calvino and Heinz Riener and Giovanni De Micheli and Akash Kumar},
 title = {Utilizing {XMG}-Based Synthesis to Preserve Self-Duality for {RFET}-Based Circuits},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
 }DownloadsTCAD_2022 [PDF] Permalink
- 148. Mehdi Moghaddamfar, Norman May, Christian Färber, Wolfgang Lehner, Akash Kumar, "A Study of Early Aggregation in Database Query Processing on FPGAs", Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ACM, Feb 2023. [doi]        [Bibtex & Downloads]
                A Study of Early Aggregation in Database Query Processing on FPGAs×ReferenceMehdi Moghaddamfar, Norman May, Christian Färber, Wolfgang Lehner, Akash Kumar, "A Study of Early Aggregation in Database Query Processing on FPGAs", Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ACM, Feb 2023. [doi] Bibtex@inproceedings{Moghaddamfar_2023,
 doi = {10.1145/3543622.3573194},
 url = {https://doi.org/10.1145%2F3543622.3573194},
 year = 2023,
 month = {feb},
 publisher = ,
 author = {Mehdi Moghaddamfar and Norman May and Christian Färber and Wolfgang Lehner and Akash Kumar},
 title = {A Study of Early Aggregation in Database Query Processing on {FPGAs}},
 booktitle = {Proceedings of the 2023 {ACM}/{SIGDA} International Symposium on Field Programmable Gate Arrays}
 }DownloadsNo Downloads available for this publication Permalink
- 147. Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks", Proceedings of the 28th Asia and South Pacific Design Automation Conference, ACM, Jan 2023. [doi]        [Bibtex & Downloads]
                SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks×ReferenceRohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks", Proceedings of the 28th Asia and South Pacific Design Automation Conference, ACM, Jan 2023. [doi] Bibtex@inproceedings{Ranjan_2023,
 doi = {10.1145/3566097.3567891},
 url = {https://doi.org/10.1145%2F3566097.3567891},
 year = 2023,
 month = {jan},
 publisher = ,
 author = {Rohit Ranjan and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
 title = {{SyFAxO}-{GeN}: Synthesizing FPGA-based Approximate Operators with Generative Networks},
 booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference}
 }DownloadsNo Downloads available for this publication Permalink
- 146. Paul Jungmann, Jeffrey B. Johnson, Eduardo C. Silva, William Taylor, Abdul Hanan Khan, Akash Kumar, "TCAD-enabled Machine Learning - An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication", In IEEE Transactions on Semiconductor Manufacturing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi]        [Bibtex & Downloads]
                TCAD-enabled Machine Learning - An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication×ReferencePaul Jungmann, Jeffrey B. Johnson, Eduardo C. Silva, William Taylor, Abdul Hanan Khan, Akash Kumar, "TCAD-enabled Machine Learning - An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication", In IEEE Transactions on Semiconductor Manufacturing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi] Bibtex@article{Jungmann_2023,
 doi = {10.1109/tsm.2023.3240033},
 url = {https://doi.org/10.1109%2Ftsm.2023.3240033},
 year = 2023,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Paul Jungmann and Jeffrey B. Johnson and Eduardo C. Silva and William Taylor and Abdul Hanan Khan and Akash Kumar},
 title = {{TCAD}-enabled Machine Learning - An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication},
 journal = {{IEEE} Transactions on Semiconductor Manufacturing}
 }DownloadsNo Downloads available for this publication Permalink
- 145. Steffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, Akash Kumar, "Formal Analysis of Camouflaged Reconfigurable Circuits" (to appear), Proceedings 21st International NEWCAS Conference, pp. 1–4, 2023.        [Bibtex & Downloads]
                Formal Analysis of Camouflaged Reconfigurable Circuits×ReferenceSteffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, Akash Kumar, "Formal Analysis of Camouflaged Reconfigurable Circuits" (to appear), Proceedings 21st International NEWCAS Conference, pp. 1–4, 2023. Bibtex@inproceedings{mrt+23,
 author = {M\"arcker, Steffen and Raitza, Michael and Rai, Shubham and Galderisi, Giulio and Mikolajick, Thomas and Trommer, Jens and Kumar, Akash},
 title = {Formal Analysis of Camouflaged Reconfigurable Circuits},
 year = {2023},
 volume = {},
 number = {},
 pages = {1--4},
 booktitle = {Proceedings 21st International NEWCAS Conference}
 }Downloadsnewcas23-camouflaging [PDF] Related PathsPermalink
- 144. Siva Satyendra Sahoo, Anup Das, Akash Kumar, "Fault Tolerant Architectures", Chapter in Handbook of Computer Architecture, Springer Nature Singapore, pp. 1–44, 2023. [doi]        [Bibtex & Downloads]
                Fault Tolerant Architectures×ReferenceSiva Satyendra Sahoo, Anup Das, Akash Kumar, "Fault Tolerant Architectures", Chapter in Handbook of Computer Architecture, Springer Nature Singapore, pp. 1–44, 2023. [doi] Bibtex@incollection{Sahoo_2023,
 doi = {10.1007/978-981-15-6401-7_11-1},
 url = {https://doi.org/10.1007%2F978-981-15-6401-7_11-1},
 year = 2023,
 publisher = {Springer Nature Singapore},
 pages = {1--44},
 author = {Siva Satyendra Sahoo and Anup Das and Akash Kumar},
 title = {Fault Tolerant Architectures},
 booktitle = {Handbook of Computer Architecture}
 }DownloadsNo Downloads available for this publication Permalink
- 143. Salim Ullah, Akash Kumar, "Approximate Arithmetic Circuit Architectures for FPGA-based Systems", Springer International Publishing, 2023. [doi]        [Bibtex & Downloads]
                Approximate Arithmetic Circuit Architectures for FPGA-based Systems×ReferenceSalim Ullah, Akash Kumar, "Approximate Arithmetic Circuit Architectures for FPGA-based Systems", Springer International Publishing, 2023. [doi] Bibtex@book{Ullah_2023,
 doi = {10.1007/978-3-031-21294-9},
 url = {https://doi.org/10.1007%2F978-3-031-21294-9},
 year = 2023,
 publisher = {Springer International Publishing},
 author = {Salim Ullah and Akash Kumar},
 title = {Approximate Arithmetic Circuit Architectures for {FPGA}-based Systems}
 }DownloadsNo Downloads available for this publication Permalink
- 142. Nima Kavand, Armin Darjani, Jens Trommer, Giulio Galderisi, Thomas Mikolajick, Nicolai Mueller, Amir Moradi, Chongzhou Fang, Ning Miao, Han Wang, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Benjamin Hettwer, Luca Parrini, Akash Kumar, "Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches", Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis, pp. 8–17, 2023.        [Bibtex & Downloads]
                Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches×ReferenceNima Kavand, Armin Darjani, Jens Trommer, Giulio Galderisi, Thomas Mikolajick, Nicolai Mueller, Amir Moradi, Chongzhou Fang, Ning Miao, Han Wang, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Benjamin Hettwer, Luca Parrini, Akash Kumar, "Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches", Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis, pp. 8–17, 2023. Bibtex@inproceedings{kavand2023special,
 title={Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches},
 author={Kavand, Nima and Darjani, Armin and Trommer, Jens and Galderisi, Giulio and Mikolajick, Thomas and Mueller, Nicolai and Moradi, Amir and Fang, Chongzhou and Miao, Ning and Wang, Han and Pudukotai Dinakarrao, Sai Manoj and Homayoun, Houman and Hettwer, Benjamin and Parrini, Luca and Kumar, Akash},
 booktitle={Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis},
 pages={8--17},
 year={2023}
 }DownloadsNo Downloads available for this publication Permalink
- 2022
- 141. Seetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu, "SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 16 August 2022. [doi]        [Bibtex & Downloads]
                SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation×ReferenceSeetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu, "SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 16 August 2022. [doi] Bibtex@article{Potluri_2022,
 doi = {10.1109/tcad.2022.3199153},
 url = {https://doi.org/10.1109%2Ftcad.2022.3199153},
 year = 2022,
 month={16 August},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Seetal Potluri and Shamik Kundu and Akash Kumar and Kanad Basu and Aydin Aysu},
 title = {{SeqL}+: Secure Scan-Obfuscation with Theoretical and Empirical Validation},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
 }DownloadsSeqL_Secure_Scan-Obfuscation_with_Theoretical_and_Empirical_Validation [PDF] Permalink
- 140. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi]        [Bibtex & Downloads]
                NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture×ReferenceYuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi] Bibtex@INPROCEEDINGS{9974206,
 
 author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
 
 booktitle={2022 International Conference on Field-Programmable Technology (ICFPT)},
 
 title={NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture},
 
 year={2022},
 month = {dec},
 pages={1-1},
 doi={10.1109/ICFPT56656.2022.9974206}}DownloadsNetPU_Prototyping_a_Generic_Reconfigurable_Neural_Network_Accelerator_Architecture [PDF] Permalink
- 139. Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Securing Hardware through Reconfigurable Nano-structures", In Proceeding: International Conference on Computer-Aided Design (ICCAD), ACM/IEEE, Nov 2022.        [Bibtex & Downloads]
                Securing Hardware through Reconfigurable Nano-structures×ReferenceNima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Securing Hardware through Reconfigurable Nano-structures", In Proceeding: International Conference on Computer-Aided Design (ICCAD), ACM/IEEE, Nov 2022. Bibtex@inproceedings{Kavand_ICCAD,
 year = 2022,
 month = {nov},
 publisher = ,
 author = {Nima Kavand and Armin Darjani and Shubham Rai and Akash Kumar},
 title = {Securing Hardware through Reconfigurable Nano-structures},
 booktitle = {International Conference on Computer-Aided Design ({ICCAD})}
 }DownloadsICCAD_2022_Special_Session [PDF] Permalink
- 138. Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 10, pp. 3239-3251, October 2022. [doi]        [Bibtex & Downloads]
                BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems×ReferenceBehnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 10, pp. 3239-3251, October 2022. [doi] Bibtex@article{Ranjbar_2022_tcad,
 year = 2022,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 month ={October},
 author = {Behnaz Ranjbar and Ali Hosseinghorban and Siva Satyendra Sahoo and Alireza Ejlali and Akash Kumar},
 title = {BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
 year={2022},
 volume={41},
 number={10},
 pages={3239-3251},
 doi={10.1109/TCAD.2021.3127867}
 }DownloadsBehnaz_TCAD_DATE2021_Extension_Camera_ready [PDF] Permalink
- 137. Mozhgan Navardi, Behnaz Ranjbar, Nezam Rohbani, Alireza Ejlali, Akash Kumar, "Peak-Power Aware Life-time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems", In IEEE Open Journal of Circuits and Systems, vol. 3, pp. 199-215, September 2022. [doi]        [Bibtex & Downloads]
                Peak-Power Aware Life-time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems×ReferenceMozhgan Navardi, Behnaz Ranjbar, Nezam Rohbani, Alireza Ejlali, Akash Kumar, "Peak-Power Aware Life-time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems", In IEEE Open Journal of Circuits and Systems, vol. 3, pp. 199-215, September 2022. [doi] Bibtex@ARTICLE{9896164,
 author={Navardi, Mozhgan and Ranjbar, Behnaz and Rohbani, Nezam and Ejlali, Alireza and Kumar, Akash},
 journal={IEEE Open Journal of Circuits and Systems},
 title={Peak-Power Aware Life-time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems},
 year={2022},
 month={September},
 volume={3},
 number={},
 pages={199-215},
 doi={10.1109/OJCAS.2022.3207598}}DownloadsOJCAS2022-ACCEPTED [PDF] Permalink
- 136. Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, "ERMES: Efficient Racetrack Memory Emulation System based on FPGA", In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022.        [Bibtex & Downloads]
                ERMES: Efficient Racetrack Memory Emulation System based on FPGA×ReferenceFanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, "ERMES: Efficient Racetrack Memory Emulation System based on FPGA", In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022. Bibtex@INPROCEEDINGS{ERMES,
 author={Fanny Spagnolo and Salim Ullah and Pasquale Corsonello and Akash Kumar},
 booktitle={2022 International Conference on Field-Programmable Logic and Applications (FPL)},
 title={ERMES: Efficient Racetrack Memory Emulation System based on FPGA},
 year={2022},
 month={aug},
 volume={},
 number={},
 pages={1-6}
 }DownloadsRTM_Emulator_FPL [PDF] Permalink
- 135. Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022.        [Bibtex & Downloads]
                PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML×ReferenceAmritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022. Bibtex@InProceedings{posax,
 author = {Amritha Immaneni and Salim Ullah and Suresh Nambi and Siva Satyendra Sahoo and Akash Kumar},
 title = {PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML},
 booktitle = {Euromicro Conference on Digital System Design (DSD)},
 year = {2022},
 month = {Aug},
 pages={1-6},
 }DownloadsPosAx_O [PDF] Permalink
- 134. Mohammed Bawatna, Behnaz Ranjbar, Akash Kumar, "A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 181-188, Aug 2022. [doi]        [Bibtex & Downloads]
                A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems×ReferenceMohammed Bawatna, Behnaz Ranjbar, Akash Kumar, "A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 181-188, Aug 2022. [doi] Bibtex@InProceedings{medo_dsd22,
 author = {Mohammed Bawatna and Behnaz Ranjbar and Akash Kumar},
 title = {A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems},
 booktitle = { Euromicro Conference on Digital System Design (DSD)},
 year = {2022},
 month = {Aug},
 pages={181-188},
 doi={10.1109/DSD57027.2022.00033}
 }Downloads2022-DSD [PDF] Permalink
- 133. Nishant Gupta, Mohil Desai, Mark Wijtvliet, Shubham Rai, Akash Kumar, "DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,", In Proceeding: 2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear), pp. 1-6, 7/2022.        [Bibtex & Downloads]
                DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,×ReferenceNishant Gupta, Mohil Desai, Mark Wijtvliet, Shubham Rai, Akash Kumar, "DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,", In Proceeding: 2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear), pp. 1-6, 7/2022. Bibtex@INPROCEEDINGS{dac-2022-delta,
 author={Gupta, Nishant and Desai, Mohil and Wijtvliet, Mark and Rai, Shubham and Kumar, Akash},
 booktitle={2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear)},
 title={DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,},
 year={2022},
 month=7,
 pages={1-6}
 }DownloadsNishant_Trojan-1 [PDF] Permalink
- 132. Max Sponner, Bernd Waschneck, Akash Kumar, "AI-Driven Performance Modeling for AI Inference Workloads", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 15, pp. 7, Jul 2022. [doi]        [Bibtex & Downloads]
                AI-Driven Performance Modeling for AI Inference Workloads×ReferenceMax Sponner, Bernd Waschneck, Akash Kumar, "AI-Driven Performance Modeling for AI Inference Workloads", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 15, pp. 7, Jul 2022. [doi] Bibtex@article{Sponner_2022,
 doi = {10.3390/electronics11152316},
 url = {https://doi.org/10.3390/electronics11152316},
 year = 2022,
 month = {jul},
 publisher = {{MDPI} {AG}},
 volume = {11},
 number = {15},
 pages = {7},
 author = {Max Sponner and Bernd Waschneck and Akash Kumar},
 title = {AI-Driven Performance Modeling for AI Inference Workloads},
 journal = {Journal of Low Power Electronics and Applications}
 }Downloadselectronics-11-02316 [PDF] Permalink
- 131. Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu, "SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture", In Proceeding: 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2022. [doi]        [Bibtex & Downloads]
                SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture×ReferenceNikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu, "SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture", In Proceeding: 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2022. [doi] Bibtex@inproceedings{Rangarajan_2022,
 doi = {10.1109/isvlsi54635.2022.00067},
 url = {https://doi.org/10.1109%2Fisvlsi54635.2022.00067},
 year = 2022,
 month = {jul},
 publisher = ,
 author = {Nikhil Rangarajan and Satwik Patnaik and Mohammed Nabeel and Mohammed Ashraf and Shubham Rai and Gopal Raut and Heba Abunahla and Baker Mohammad and Santosh Kumar Vishvakarma and Akash Kumar and Johann Knechtel and Ozgur Sinanoglu},
 title = {{SCRAMBLE}: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture},
 booktitle = {2022 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
 }DownloadsNo Downloads available for this publication Permalink
- 130. Armin Darjani, Nima Kavand, Shubham Rai, Mark Wijtvliet, Akash Kumar, "ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks", In Proceeding: ACM Great Lakes Symposium on VLSI (GLSVLSI), 6/2022. [doi]        [Bibtex & Downloads]
                ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks×ReferenceArmin Darjani, Nima Kavand, Shubham Rai, Mark Wijtvliet, Akash Kumar, "ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks", In Proceeding: ACM Great Lakes Symposium on VLSI (GLSVLSI), 6/2022. [doi] Bibtex@INPROCEEDINGS{DARJANI2022,
 author = {Armin Darjani and Nima Kavand and Shubham Rai and Mark Wijtvliet and Akash Kumar},
 title = {ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks},
 booktitle={ACM Great Lakes Symposium on VLSI (GLSVLSI)},
 doi = {10.1145/3526241.3530371},
 year = 2022,
 month = 6
 }Downloadsauthor-prepared-GLSVLSI_2022_ArminDarjani [PDF] Permalink
- 129. Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), vol. 39, no. 3, pp. 73–81, Jun 2022. [doi]        [Bibtex & Downloads]
                Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy×ReferenceAditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), vol. 39, no. 3, pp. 73–81, Jun 2022. [doi] Bibtex@article{Lohana_2022,
 doi = {10.1109/mdat.2021.3063373},
 url = {https://doi.org/10.1109%2Fmdat.2021.3063373},
 year = 2022,
 month = {jun},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 volume = {39},
 number = {3},
 pages = {73--81},
 author = {Aditya Lohana and Ansh Rupani and Shubham Rai and Akash Kumar},
 title = {Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy},
 journal = {{IEEE} Design {\&} Test}
 }DownloadsDandT [PDF] Permalink
- 128. Behnaz Ranjbar, Hamidreza Alikhani, Bardia Safaei, Alireza Ejlali, Akash Kumar, "Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems", In Computers, vol. 11, no. 7, June 2022. [doi]        [Bibtex & Downloads]
                Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems×ReferenceBehnaz Ranjbar, Hamidreza Alikhani, Bardia Safaei, Alireza Ejlali, Akash Kumar, "Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems", In Computers, vol. 11, no. 7, June 2022. [doi] Bibtex@Article{computers11070101,
 AUTHOR = {Ranjbar, Behnaz and Alikhani, Hamidreza and Safaei, Bardia and Ejlali, Alireza and Kumar, Akash},
 TITLE = {Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems},
 JOURNAL = {Computers},
 VOLUME = {11},
 YEAR = {2022},
 NUMBER = {7},
 MONTH = {June},
 ARTICLE-NUMBER = {101},
 URL = {https://www.mdpi.com/2073-431X/11/7/101},
 ISSN = {2073-431X},
 DOI = {10.3390/computers11070101}
 }DownloadsNo Downloads available for this publication Permalink
- 127. Behnaz Ranjbar, Ali Hosseinghorban, Mohammad Salehi, Alireza Ejlali, Akash Kumar, "Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 5, pp. 1509-1522, May 2022. [doi]        [Bibtex & Downloads]
                Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems×ReferenceBehnaz Ranjbar, Ali Hosseinghorban, Mohammad Salehi, Alireza Ejlali, Akash Kumar, "Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 5, pp. 1509-1522, May 2022. [doi] Bibtex@article{Ranjbar_2021,
 doi = {10.1109/tcad.2021.3082495},
 url = {https://doi.org/10.1109%2Ftcad.2021.3082495},
 year = 2022,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 month = May,
 volume={41},
 number={5},
 pages={1509-1522},
 author = {Behnaz Ranjbar and Ali Hosseinghorban and Mohammad Salehi and Alireza Ejlali and Akash Kumar},
 title = {Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}
 }DownloadsTree-PPMFTMCS- Arxiv [PDF] Permalink
- 126. T. Mikolajick, G. Galderisi, S. Rai, M. Simon, R. Böckle, M. Sistani, C. Cakirlar, N. Bhattacharjee, T. Mauersberger, A. Heinzig, A. Kumar, W.M. Weber, J. Trommer, "Reconfigurable Field Effect Transistors: A Technology Enablers Perspective", In Solid-State Electronics, Elsevier BV, pp. 108381, May 2022. [doi]        [Bibtex & Downloads]
                Reconfigurable Field Effect Transistors: A Technology Enablers Perspective×ReferenceT. Mikolajick, G. Galderisi, S. Rai, M. Simon, R. Böckle, M. Sistani, C. Cakirlar, N. Bhattacharjee, T. Mauersberger, A. Heinzig, A. Kumar, W.M. Weber, J. Trommer, "Reconfigurable Field Effect Transistors: A Technology Enablers Perspective", In Solid-State Electronics, Elsevier BV, pp. 108381, May 2022. [doi] Bibtex@article{Mikolajick_2022,
 doi = {10.1016/j.sse.2022.108381},
 url = {https://doi.org/10.1016%2Fj.sse.2022.108381},
 year = 2022,
 month = {may},
 publisher = {Elsevier {BV}},
 pages = {108381},
 author = {T. Mikolajick and G. Galderisi and S. Rai and M. Simon and R. Böckle and M. Sistani and C. Cakirlar and N. Bhattacharjee and T. Mauersberger and A. Heinzig and A. Kumar and W.M. Weber and J. Trommer},
 title = {Reconfigurable Field Effect Transistors: A Technology Enablers Perspective},
 journal = {Solid-State Electronics}
 }DownloadsSSE_Review_Full_Version [PDF] Permalink
- 125. Zahra Ebrahimi, Dennis Klar, Mohammad Aasim Ekhtiyar, Akash Kumar, "Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider" (to appear), In ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), vol. 27, no. 2, pp. 1–33, Mar 2022. [doi]        [Bibtex & Downloads]
                Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider×ReferenceZahra Ebrahimi, Dennis Klar, Mohammad Aasim Ekhtiyar, Akash Kumar, "Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider" (to appear), In ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), vol. 27, no. 2, pp. 1–33, Mar 2022. [doi] Bibtex@article{Ebrahimi_2022,
 doi = {10.1145/3486616},
 url = {https://doi.org/10.1145%2F3486616},
 year = 2022,
 month = {mar},
 publisher = {Association for Computing Machinery ({ACM})},
 volume = {27},
 number = {2},
 pages = {1--33},
 author = {Zahra Ebrahimi and Dennis Klar and Mohammad Aasim Ekhtiyar and Akash Kumar},
 title = {Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient {SIMD} Soft Multiplier-divider},
 journal = {{ACM} Transactions on Design Automation of Electronic Systems}
 }Downloadszahra_plasticine_todaes [PDF] Related Pathsother Permalink
- 124. M. Thümmler, S. Rai, A. Kumar, "Improving Technology Mapping for And-Inverter-Cones", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), March 2022.        [Bibtex & Downloads]
                Improving Technology Mapping for And-Inverter-Cones×ReferenceM. Thümmler, S. Rai, A. Kumar, "Improving Technology Mapping for And-Inverter-Cones", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), March 2022. Bibtex@InProceedings{Thuemmler2022,
 Title = {Improving Technology Mapping for And-Inverter-Cones},
 Author = {M. Th{\"{u}}mmler and S. Rai and A. Kumar},
 Booktitle = {2022 Design, Automation Test in Europe Conference Exhibition (DATE)},
 Year = {2022},
 Month = {March},
 Owner = {shubham},
 Timestamp = {2018.04.26}
 }DownloadsMartin_thuemmler_AIC(1) [PDF] Permalink
- 123. Michael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar, "Exploring Standard-Cell Designs for Reconfigurable
Nanotechnologies: A Formal Approach", In Proceeding: 2022 Design, Automation   Test in Europe Conference   Exhibition (DATE), Mar 2022.        [Bibtex & Downloads]
                Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach×ReferenceMichael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar, "Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2022. Bibtex@INPROCEEDINGS{9474132,
 author={Raitza, Michael and M{\"a}rcker, Steffen and Rai, Shubham and Kumar, Akash},
 booktitle={2022 Design, Automation Test in Europe Conference Exhibition (DATE)},
 title={Exploring Standard-Cell Designs for Reconfigurable
 Nanotechnologies: A Formal Approach},
 year={2022},
 month = mar,
 volume={},
 number={}
 }DownloadsDATE_SS_2022 [PDF] Permalink
- 122. Ali Hosseinghorban, Akash Kumar, "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications", In Electronics, vol. 11, Mar 2022. [doi]        [Bibtex & Downloads]
                A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications×ReferenceAli Hosseinghorban, Akash Kumar, "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications", In Electronics, vol. 11, Mar 2022. [doi] Bibtex@Article{ali-mdpi-electronics-2022,
 AUTHOR = {Hosseinghorban, Ali and Kumar, Akash},
 TITLE = {A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications},
 JOURNAL = {Electronics},
 VOLUME = {11},
 YEAR = {2022},
 month={mar},
 ARTICLE-NUMBER = {978},
 URL = {https://www.mdpi.com/2079-9292/11/7/978},
 ISSN = {2079-9292},
 DOI = {10.3390/electronics11070978}
 }DownloadsLTE_on_Chip_MDPI-author-prepared [PDF] Permalink
- 121. Stefano Corda, Bram Veenboer, Ahsan Javed Awan, John W. Romein, Roel Jordans, Akash Kumar, Albert-Jan Boonstra, Henk Corporaal, "Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 10, pp. 22819–22843, 2022. [doi]        [Bibtex & Downloads]
                Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware×ReferenceStefano Corda, Bram Veenboer, Ahsan Javed Awan, John W. Romein, Roel Jordans, Akash Kumar, Albert-Jan Boonstra, Henk Corporaal, "Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 10, pp. 22819–22843, 2022. [doi] Bibtex@article{Corda_2022,
 doi = {10.1109/access.2022.3150861},
 url = {https://doi.org/10.1109%2Faccess.2022.3150861},
 year = 2022,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 volume = {10},
 pages = {22819--22843},
 author = {Stefano Corda and Bram Veenboer and Ahsan Javed Awan and John W. Romein and Roel Jordans and Akash Kumar and Albert-Jan Boonstra and Henk Corporaal},
 title = {Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware},
 journal = {{IEEE} Access}
 }DownloadsIEEE-Access-final-version-Stefano [PDF] Permalink
- 120. Negar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar, "Multi-Precision Deep Neural Network Acceleration on FPGAs" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022.        [Bibtex & Downloads]
                Multi-Precision Deep Neural Network Acceleration on FPGAs×ReferenceNegar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar, "Multi-Precision Deep Neural Network Acceleration on FPGAs" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022. Bibtex@InProceedings{mehdi_2022_aspdac,
 author = {Negar Neda and Salim Ullah and Azam Ghanbari and Hoda Mahdiani and Mehdi Modarressi and Akash Kumar},
 booktitle = {Asia and South Pacific Design Automation Conference (ASPDAC)},
 title = {Multi-Precision Deep Neural Network Acceleration on {FPGAs}},
 year = {2022},
 month=1,
 organization = {IEEE},
 }DownloadsNo Downloads available for this publication Permalink
- 119. Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli, "A Versatile Mapping Approach for Technology Mapping and Graph Optimization" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022.        [Bibtex & Downloads]
                A Versatile Mapping Approach for Technology Mapping and Graph Optimization×ReferenceAlessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli, "A Versatile Mapping Approach for Technology Mapping and Graph Optimization" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022. Bibtex@InProceedings{alessandro_2022_aspdac,
 author = {Alessandro Tempia Calvino and Heinz Riener and Shubham Rai and Akash Kumar and Giovanni De Micheli},
 booktitle = {Asia and South Pacific Design Automation Conference (ASPDAC)},
 title = {A Versatile Mapping Approach for Technology Mapping and Graph Optimization},
 year = {2022},
 month = {1},
 organization = {IEEE},
 }DownloadsASP_DAC22 [PDF] Permalink
- 118. Mark Wijtvliet, Akash Kumar, Henk Corporaal, "Blocks: challenging SIMDs and VLIWs with a reconfigurable architecture", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–14, 1/2022. [doi]        [Bibtex & Downloads]
                Blocks: challenging SIMDs and VLIWs with a reconfigurable architecture×ReferenceMark Wijtvliet, Akash Kumar, Henk Corporaal, "Blocks: challenging SIMDs and VLIWs with a reconfigurable architecture", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–14, 1/2022. [doi] Bibtex@article{mark-tcad-2021,
 doi = {10.1109/tcad.2021.3120541},
 url = {https://doi.org/10.1109%2Ftcad.2021.3120541},
 year = 2022,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--14},
 month = 1,
 author = {Mark Wijtvliet and Akash Kumar and Henk Corporaal},
 title = {Blocks: challenging {SIMDs} and {VLIWs} with a reconfigurable architecture},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
 }DownloadsTCAD3120541 [PDF] Permalink
- 117. Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022.        [Bibtex & Downloads]
                AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems×ReferenceSalim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022. Bibtex@article{ullah2022appaxo,
 title={AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems},
 author={Ullah, Salim and Sahoo, Siva Satyendra and Ahmed, Nemath and Chaudhury, Debabrata and Kumar, Akash},
 journal={ACM Transactions on Embedded Computing Systems (TECS)},
 volume={},
 number={},
 pages={1--31},
 year={2022},
 month={January}
 }DownloadsAppAxO [PDF] Permalink
- 116. Mark Wijtvliet, Henk Corporaal, Akash Kumar, "Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures", Springer International Publishing, 2022. [doi]        [Bibtex & Downloads]
                Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures×ReferenceMark Wijtvliet, Henk Corporaal, Akash Kumar, "Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures", Springer International Publishing, 2022. [doi] Bibtex@book{Wijtvliet_2022,
 doi = {10.1007/978-3-030-79774-4},
 url = {https://doi.org/10.1007%2F978-3-030-79774-4},
 year = 2022,
 publisher = {Springer International Publishing},
 author = {Mark Wijtvliet and Henk Corporaal and Akash Kumar},
 title = {Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures}
 }DownloadsNo Downloads available for this publication Permalink
- 115. Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi]        [Bibtex & Downloads]
                END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator×ReferenceShubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi] Bibtex@incollection{Rai_2022,
 doi = {10.1007/978-3-031-16818-5_9},
 url = {https://doi.org/10.1007%2F978-3-031-16818-5_9},
 year = 2022,
 publisher = {Springer Nature Switzerland},
 pages = {175--203},
 author = {Shubham Rai and Nishant Gupta and Abhiroop Bhattacharjee and Ansh Rupani and Michael Raitza and Jens Trommer and Thomas Mikolajick and Akash Kumar},
 title = {{END}-{TRUE}: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator},
 booktitle = {{VLSI}-{SoC}: Technology Advancement on {SoC} Design}
 }DownloadsNo Downloads available for this publication Permalink
- 114. Cecilia De la Parra, Taha Soliman, Andre Guntoro, Akash Kumar, Norbert Wehn, "Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation" (to appear), In IEEE Micro, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2022. [doi]        [Bibtex & Downloads]
                Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation×ReferenceCecilia De la Parra, Taha Soliman, Andre Guntoro, Akash Kumar, Norbert Wehn, "Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation" (to appear), In IEEE Micro, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2022. [doi] Bibtex@article{Cecilia_micro22,
 doi = {MicroSI-2022-03-0032},
 url = {https://cfaed.tu-dresden.de/cpd-publications},
 year = 2022,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Cecilia De la Parra and Taha Soliman and Andre Guntoro and Akash Kumar and Norbert Wehn},
 title = {Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation},
 journal = {{IEEE} Micro}
 }DownloadsIEEE_MICRO_camera_ready [PDF] Permalink
- 113. Jorge Navarro Quijada, Tim Baldauf, Shubham Rai, Andre Heinzig, Akash Kumar, Walter M. Weber, Thomas Mikolajick, Jens Trommer, "A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation", In IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–8, 2022. [doi]        [Bibtex & Downloads]
                A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation×ReferenceJorge Navarro Quijada, Tim Baldauf, Shubham Rai, Andre Heinzig, Akash Kumar, Walter M. Weber, Thomas Mikolajick, Jens Trommer, "A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation", In IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–8, 2022. [doi] Bibtex@article{Quijada_2022,
 doi = {10.1109/tnano.2022.3221836},
 url = {https://doi.org/10.1109%2Ftnano.2022.3221836},
 year = 2022,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--8},
 author = {Jorge Navarro Quijada and Tim Baldauf and Shubham Rai and Andre Heinzig and Akash Kumar and Walter M. Weber and Thomas Mikolajick and Jens Trommer},
 title = {A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation},
 journal = {{IEEE} Transactions on Nanotechnology}
 }DownloadsGeNW_RFET_VerilogA-TNANO [PDF] Permalink
- 2021
- 112. Najdet Charaf, Christoph Tietz, Michael Raitza, Akash Kumar, Diana Gohringer, "AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs", In Proceeding: 2021 International Conference on Field-Programmable Technology (ICFPT), IEEE, Dec 2021. [doi]        [Bibtex & Downloads]
                AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs×ReferenceNajdet Charaf, Christoph Tietz, Michael Raitza, Akash Kumar, Diana Gohringer, "AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs", In Proceeding: 2021 International Conference on Field-Programmable Technology (ICFPT), IEEE, Dec 2021. [doi] Bibtex@inproceedings{Charaf_2021,
 doi = {10.1109/icfpt52863.2021.9609948},
 url = {https://doi.org/10.1109%2Ficfpt52863.2021.9609948},
 year = 2021,
 month = {dec},
 publisher = ,
 author = {Najdet Charaf and Christoph Tietz and Michael Raitza and Akash Kumar and Diana Gohringer},
 title = {{AMAH}-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on {FPGAs}},
 booktitle = {2021 International Conference on Field-Programmable Technology ({ICFPT})}
 }DownloadsFPT-2021-AMAH-Flex_A_Modular_and_Highly_Flexible_Tool_for_Generating_Relocatable_Systems_on_FPGAs [PDF] Permalink
- 111. T. Mikolajick, G. Galderisi, M. Simon, S. Rai, A. Kumar, A. Heinzig, W.M. Weber, J. Trommer, "20 Years of reconfigurable field-effect transistors: From concepts to future applications", In Solid-State Electronics, Elsevier BV, vol. 186, pp. 108036, Dec 2021. [doi]        [Bibtex & Downloads]
                20 Years of reconfigurable field-effect transistors: From concepts to future applications×ReferenceT. Mikolajick, G. Galderisi, M. Simon, S. Rai, A. Kumar, A. Heinzig, W.M. Weber, J. Trommer, "20 Years of reconfigurable field-effect transistors: From concepts to future applications", In Solid-State Electronics, Elsevier BV, vol. 186, pp. 108036, Dec 2021. [doi] Bibtex@article{Mikolajick_2021,
 doi = {10.1016/j.sse.2021.108036},
 url = {https://doi.org/10.1016%2Fj.sse.2021.108036},
 year = 2021,
 month = {dec},
 publisher = {Elsevier {BV}},
 volume = {186},
 pages = {108036},
 author = {T. Mikolajick and G. Galderisi and M. Simon and S. Rai and A. Kumar and A. Heinzig and W.M. Weber and J. Trommer},
 title = {20 Years of reconfigurable field-effect transistors: From concepts to future applications},
 journal = {Solid-State Electronics}
 }DownloadsSolid_state_electronics_2021 [PDF] Permalink
- 110. Elias Trommer, Bernd Waschneck, Akash Kumar, "dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021.        [Bibtex & Downloads]
                dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference×ReferenceElias Trommer, Bernd Waschneck, Akash Kumar, "dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021. Bibtex@INPROCEEDINGS{Trommer2021,
 author={Trommer, Elias and Waschneck, Bernd and Kumar, Akash},
 booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
 title={dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference},
 month={Nov},
 year={2021},
 volume={},
 number={}}DownloadsNo Downloads available for this publication Permalink
- 109. Andreas Krinke, Shubham Rai, Akash Kumar, Jens Lienig, "Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021.        [Bibtex & Downloads]
                Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies×ReferenceAndreas Krinke, Shubham Rai, Akash Kumar, Jens Lienig, "Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021. Bibtex@INPROCEEDINGS{krinke2021,
 author={Krinke, Andreas and Rai, Shubham and Kumar, Akash and Lienig, Jens},
 booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
 title={Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies},
 month={Nov},
 year={2021},
 volume={},
 number={}}Downloadsiccad_2021_2 [PDF] Permalink
- 108. Yasasvi V. Peruvemba, Shubham Rai, Kapil Ahuja, Akash Kumar, "RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021.        [Bibtex & Downloads]
                RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis×ReferenceYasasvi V. Peruvemba, Shubham Rai, Kapil Ahuja, Akash Kumar, "RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021. Bibtex@INPROCEEDINGS{peruvemba2021,
 author={Peruvemba, Yasasvi V. and Rai, Shubham and Ahuja, Kapil and Kumar, Akash},
 booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
 title={RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis},
 month={Nov},
 year={2021},
 volume={},
 number={}}Downloads101_Final_ICCAD_Paper (1) [PDF] Permalink
- 107. Siva Satyendra Sahoo, Akash Kumar, "Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021.        [Bibtex & Downloads]
                Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems×ReferenceSiva Satyendra Sahoo, Akash Kumar, "Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. Bibtex@INPROCEEDINGS{siva-vlsisoc2021-mctsclr,
 author={Siva Satyendra Sahoo and Akash Kumar},
 booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC)},
 title={Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems},
 year={2021},
 month={Oct},
 volume={},
 number={}}DownloadsMCTS_CLRIntegTMap [PDF] Permalink
- 106. Siva Satyendra Sahoo, Akash Kumar, "CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021.        [Bibtex & Downloads]
                CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems×ReferenceSiva Satyendra Sahoo, Akash Kumar, "CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. Bibtex@INPROCEEDINGS{siva-vlsisoc2021-cleocode,
 author={Siva Satyendra Sahoo and Akash Kumar},
 booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC)},
 title={CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems},
 year={2021},
 month={Oct},
 volume={},
 number={}}DownloadsCLEOCoDe [PDF] Permalink
- 105. Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi]        [Bibtex & Downloads]
                Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput×ReferenceAbhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi] Bibtex@inproceedings{Bhattacharjee_2021,
 doi = {10.1109/vlsi-soc53125.2021.9607015},
 url = {https://doi.org/10.1109%2Fvlsi-soc53125.2021.9607015},
 year = 2021,
 month = {oct},
 publisher = ,
 author = {Abhiroop Bhattacharjee and Shubham Rai and Ansh Rupani and Michael Raitza and Akash Kumar},
 title = {Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput},
 booktitle = {2021 {IFIP}/{IEEE} 29th International Conference on Very Large Scale Integration ({VLSI}-{SoC})}
 }DownloadsVLSI-SOC_2021 [PDF] Permalink
- 104. Behnaz Ranjbar, Tuan D. A. Nguyen, Alireza Ejlali, Akash Kumar, "Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 40, no. 10, pp. 2009-2023, October 2021. [doi]        [Bibtex & Downloads]
                Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform×ReferenceBehnaz Ranjbar, Tuan D. A. Nguyen, Alireza Ejlali, Akash Kumar, "Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 40, no. 10, pp. 2009-2023, October 2021. [doi] Bibtex@article{Ranjbar_2020,
 doi = {10.1109/tcad.2020.3033374},
 url = {https://doi.org/10.1109%2Ftcad.2020.3033374},
 year = 2021,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {2009-2023},
 volume={40},
 number={10},
 month ={October},
 author = {Behnaz Ranjbar and Tuan D. A. Nguyen and Alireza Ejlali and Akash Kumar},
 title = {Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}
 }DownloadsTCAD3033374-power-aware-accepted [PDF] Permalink
- 103. Stefano Corda, Madhurya Kumaraswamy, Ahsan Javed Awan, Roel Jordans, Akash Kumar, Henk Corporaal, "NMPO: Near-Memory Computing Profiling and Offloading", In Proceeding: 2021 24th Euromicro Conference on Digital System Design (DSD), IEEE, Sep 2021. [doi]        [Bibtex & Downloads]
                NMPO: Near-Memory Computing Profiling and Offloading×ReferenceStefano Corda, Madhurya Kumaraswamy, Ahsan Javed Awan, Roel Jordans, Akash Kumar, Henk Corporaal, "NMPO: Near-Memory Computing Profiling and Offloading", In Proceeding: 2021 24th Euromicro Conference on Digital System Design (DSD), IEEE, Sep 2021. [doi] Bibtex@inproceedings{Corda_2021,
 doi = {10.1109/dsd53832.2021.00048},
 url = {https://doi.org/10.1109%2Fdsd53832.2021.00048},
 year = 2021,
 month = {sep},
 publisher = ,
 author = {Stefano Corda and Madhurya Kumaraswamy and Ahsan Javed Awan and Roel Jordans and Akash Kumar and Henk Corporaal},
 title = {{NMPO}: Near-Memory Computing Profiling and Offloading},
 booktitle = {2021 24th Euromicro Conference on Digital System Design ({DSD})}
 }DownloadsNo Downloads available for this publication Permalink
- 102. Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel C. B. Wong, Geoff V. Merrett, Yinyuan Zhao, Jiachen Wang, Xiaohang Wang, Amit Kumar Singh, "Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives", Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis, ACM, Sep 2021. [doi]        [Bibtex & Downloads]
                Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives×ReferenceSiva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel C. B. Wong, Geoff V. Merrett, Yinyuan Zhao, Jiachen Wang, Xiaohang Wang, Amit Kumar Singh, "Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives", Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis, ACM, Sep 2021. [doi] AbstractModern embedded systems need to cater for several needs depending upon the application domain in which they are deployed. For example, mixed-critically needs to be considered for real-time and safety-critical systems and energy for battery-operated systems. At the same time, many of these systems demand for their reliability and security as well. With electronic systems being used for increasingly varying type of applications, novel challenges have emerged. For example, with the use of embedded systems in increasingly complex applications that execute tasks with varying priorities, mixed-criticality systems present unique challenges to designing reliable systems. The large design space involved in implementing cross-layer reliability in heterogeneous systems, particularly for mixed-critical systems, poses new research problems. Further, malicious security attacks on these systems pose additional extraordinary challenges in the system design. In this paper, we cover both the industry and academia perspectives of the challenges posed by these emergent aspects of system design towards designing high-performance, energy-efficient, reliable and/or secure embedded systems. We also provide our views on paths forward. Bibtex@inproceedings{Sahoo_2021,
 doi = {10.1145/3478684.3479246},
 url = {https://doi.org/10.1145%2F3478684.3479246},
 year = 2021,
 month = {sep},
 publisher = ,
 author = {Siva Satyendra Sahoo and Akash Kumar and Martin Decky and Samuel C. B. Wong and Geoff V. Merrett and Yinyuan Zhao and Jiachen Wang and Xiaohang Wang and Amit Kumar Singh},
 title = {Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives},
 booktitle = {Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis}
 }DownloadsESWEEK_2021_SS [PDF] Related PathsPermalink
- 101. Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi]        [Bibtex & Downloads]
                ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems×ReferenceSuresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi] Bibtex@article{Nambi_2021,
 doi = {10.1109/access.2021.3098730},
 url = {https://doi.org/10.1109%2Faccess.2021.3098730},
 year = 2021,
 month = {July},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Suresh Nambi and Salim Ullah and Siva Satyendra Sahoo and Aditya Lohana and Farhad Merchant and Akash Kumar},
 title = {{ExPAN}(N)D: Exploring Posits for Efficient Artificial Neural Network Design in {FPGA}-based Systems},
 journal = {{IEEE} Access}
 }DownloadsExPANND_Exploring_Posits_for_Efficient_Artificial_Neural_Network_Design_in_FPGA-based_Systems [PDF] Related PathsPermalink
- 100. Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 9, pp. 91564–91574, 2021. [doi]        [Bibtex & Downloads]
                A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies×ReferenceShubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 9, pp. 91564–91574, 2021. [doi] Bibtex@article{Rai_2021,
 doi = {10.1109/access.2021.3092167},
 url = {https://doi.org/10.1109%2Faccess.2021.3092167},
 year = 2021,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 volume = {9},
 pages = {91564--91574},
 author = {Shubham Rai and Pallab Nath and Ansh Rupani and Santosh Kumar Vishvakarma and Akash Kumar},
 title = {A Survey of {FPGA} Logic Cell Designs in the Light of Emerging Technologies},
 journal = {{IEEE} Access}
 }Downloadssurvey_FPGA_IEEE_access [PDF] Permalink
- 99. S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021.        [Bibtex & Downloads]
                CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems×ReferenceS. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021. Bibtex@INPROCEEDINGS{clapped,
 author={S. {Ullah} and S. S. {Sahoo} and A. {Kumar}},
 booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)},
 title={CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems},
 year={2021},
 month={jul},
 volume={},
 number={},
 pages={1-6}
 }DownloadsCLAppED_A_Design_Framework_for_Implementing_Cross-Layer_Approximation_in_FPGA-based_Embedded_Systems [PDF] Permalink
- 98. Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi]        [Bibtex & Downloads]
                Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators×ReferenceSalim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi] Bibtex@article{Ullah_2021,
 doi = {10.1109/les.2020.2995053},
 url = {https://doi.org/10.1109%2Fles.2020.2995053},
 year = 2021,
 month = {jun},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 volume = {13},
 number = {2},
 pages = {41--44},
 author = {Salim Ullah and Tuan Duy Anh Nguyen and Akash Kumar},
 title = {Energy-Efficient Low-Latency Signed Multiplier for {FPGA}-Based Hardware Accelerators},
 journal = {{IEEE} Embedded Systems Letters}
 }DownloadsESL_acc_multiplier [PDF] Permalink
- 97. Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi]        [Bibtex & Downloads]
                MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems×ReferenceSiva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi] Bibtex@inproceedings{10.1145/3453688.3461533,
 author = {Sahoo, Siva Satyendra and Baranwal, Akhil Raj and Ullah, Salim and Kumar, Akash},
 title = {MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems},
 year = {2021},
 month={June},
 isbn = {9781450383936},
 publisher = {Association for Computing Machinery},
 address = {New York, NY, USA},
 url = {https://doi.org/10.1145/3453688.3461533},
 doi = {10.1145/3453688.3461533},
 pages = {339–346},
 numpages = {8},
 keywords = {memory-centric computing, fpga, energy-efficient computing, high-level synthesis, hardware accelerators},
 location = {Virtual Event, USA},
 series = {GLSVLSI '21}
 }DownloadsNo Downloads available for this publication Permalink
- 96. Mark Wijtvliet, Akash Kumar, Henk Corporaal, "CGRA-EAM - Rapid energy and area estimation for coarse-grained reconfigurable architectures" (to appear), ACM, New York, NY, USA, June 2021.        [Bibtex & Downloads]
                CGRA-EAM - Rapid energy and area estimation for coarse-grained reconfigurable architectures×ReferenceMark Wijtvliet, Akash Kumar, Henk Corporaal, "CGRA-EAM - Rapid energy and area estimation for coarse-grained reconfigurable architectures" (to appear), ACM, New York, NY, USA, June 2021. Bibtex@article{wijtvliet_trets,
 author={Wijtvliet, Mark and Kumar, Akash and Corporaal, Henk},
 booktitle={Transactions on Reconfigurable Technology and Systems},
 title={CGRA-EAM - Rapid energy and area estimation for coarse-grained reconfigurable architectures},
 publisher={ACM},
 month={June},
 address={New York, NY, USA},
 year={2021},}DownloadsNo Downloads available for this publication Permalink
- 95. Mehdi Moghaddamfar, Christian Färber, Wolfgang Lehner, Norman May, Akash Kumar, "Resource-Efficient Database Query Processing on FPGAs", Proceedings of the 17th International Workshop on Data Management on New Hardware (DaMoN 2021), ACM, Jun 2021. [doi]        [Bibtex & Downloads]
                Resource-Efficient Database Query Processing on FPGAs×ReferenceMehdi Moghaddamfar, Christian Färber, Wolfgang Lehner, Norman May, Akash Kumar, "Resource-Efficient Database Query Processing on FPGAs", Proceedings of the 17th International Workshop on Data Management on New Hardware (DaMoN 2021), ACM, Jun 2021. [doi] Bibtex@inproceedings{Moghaddamfar_2021,
 doi = {10.1145/3465998.3466006},
 url = {https://doi.org/10.1145%2F3465998.3466006},
 year = 2021,
 month = {jun},
 publisher = ,
 author = {Mehdi Moghaddamfar and Christian Färber and Wolfgang Lehner and Norman May and Akash Kumar},
 title = {Resource-Efficient Database Query Processing on {FPGAs}},
 booktitle = {Proceedings of the 17th International Workshop on Data Management on New Hardware ({DaMoN} 2021)}
 }DownloadsNo Downloads available for this publication Permalink
- 94. Maartje Roosmalen, Anna Herrmann, Akash Kumar, "A review of prefabricated self-sufficient facades with integrated decentralised HVAC and renewable energy generation and storage", In Energy and Buildings, Elsevier BV, pp. 111107, May 2021. [doi]        [Bibtex & Downloads]
                A review of prefabricated self-sufficient facades with integrated decentralised HVAC and renewable energy generation and storage×ReferenceMaartje Roosmalen, Anna Herrmann, Akash Kumar, "A review of prefabricated self-sufficient facades with integrated decentralised HVAC and renewable energy generation and storage", In Energy and Buildings, Elsevier BV, pp. 111107, May 2021. [doi] Bibtex@article{Roosmalen_2021,
 doi = {10.1016/j.enbuild.2021.111107},
 url = {https://doi.org/10.1016%2Fj.enbuild.2021.111107},
 year = 2021,
 month = {may},
 publisher = {Elsevier {BV}},
 pages = {111107},
 author = {Maartje Roosmalen and Anna Herrmann and Akash Kumar},
 title = {A review of prefabricated self-sufficient facades with integrated decentralised {HVAC} and renewable energy generation and storage},
 journal = {Energy and Buildings}
 }DownloadsSoA_Intelli_Facade_black [PDF] Permalink
- 93. Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro, "Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.        [Bibtex & Downloads]
                Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design×ReferenceCecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro, "Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. Bibtex@inproceedings{De_la_Parra_2021,
 year = 2021,
 month = may,
 author = {Cecilia De la Parra and Ahmed El-Yamany and Taha Soliman and Akash Kumar and Norbert Wehn and Andre Guntoro},
 title = {Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design},
 booktitle = {2021 {IEEE} International Symposium on Circuits and Systems ({ISCAS})}
 }Downloadsiscas-2021-cecilia [PDF] Permalink
- 92. Zahra Ebrahimi, Akash Kumar, "BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2021. [doi]        [Bibtex & Downloads]
                BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge×ReferenceZahra Ebrahimi, Akash Kumar, "BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2021. [doi] Bibtex@inproceedings{Ebrahimi_2021,
 doi = {10.1109/iscas51556.2021.9401461},
 url = {https://doi.org/10.1109%2Fiscas51556.2021.9401461},
 year = 2021,
 month = {may},
 publisher = ,
 author = {Zahra Ebrahimi and Akash Kumar},
 title = {{BioCare}: An Energy-Efficient {CGRA} for Bio-Signal Processing at the Edge},
 booktitle = {2021 {IEEE} International Symposium on Circuits and Systems ({ISCAS})}
 }DownloadsISCAS_BioCare_2021 [PDF] Permalink
- 91. Max Sponner, Bernd Waschneck, Akash Kumar, "Compiler Toolchains for Deep Learning Workloads on Embedded Platforms", April 2021.        [Bibtex & Downloads]
                Compiler Toolchains for Deep Learning Workloads on Embedded Platforms×ReferenceMax Sponner, Bernd Waschneck, Akash Kumar, "Compiler Toolchains for Deep Learning Workloads on Embedded Platforms", April 2021. Bibtex@misc{sponner2021compiler,
 title={Compiler Toolchains for Deep Learning Workloads on Embedded Platforms},
 author={Max Sponner and Bernd Waschneck and Akash Kumar},
 year={2021},
 month={April},
 eprint={2104.04576},
 archivePrefix={arXiv},
 primaryClass={cs.PL},
 }Downloadscompiler_tool_chain [PDF] Permalink
- 90. Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 264-269, Feb. 2021. [doi]        [Bibtex & Downloads]
                Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem×ReferenceBehnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 264-269, Feb. 2021. [doi] Bibtex@INPROCEEDINGS{behnaz2021date,
 author={Ranjbar, Behnaz and Hosseinghorban, Ali and Sahoo, Siva Satyendra and Ejlali, Alireza and Kumar, Akash},
 booktitle={2021 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
 title={Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem},
 year={2021},
 month={Feb.},
 volume={},
 number={},
 pages={264-269},
 organization={IEEE},
 doi={10.23919/DATE51398.2021.9474263}}DownloadsImproving_Timing_DATE21 [PDF] Permalink
- 89. Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. de Abreu, Isac de Souza Campos, Augusto Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit O. Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]        [Bibtex & Downloads]
                Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization×ReferenceShubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. de Abreu, Isac de Souza Campos, Augusto Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit O. Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] Bibtex@inproceedings{Rai_2021,
 doi = {10.23919/date51398.2021.9473972},
 url = {https://doi.org/10.23919%2Fdate51398.2021.9473972},
 year = 2021,
 month = {feb},
 publisher = ,
 author = {Shubham Rai and Walter Lau Neto and Yukio Miyasaka and Xinpei Zhang and Mingfei Yu and Qingyang Yi and Masahiro Fujita and Guilherme B. Manske and Matheus F. Pontes and Leomar S. da Rosa and Marilton S. de Aguiar and Paulo F. Butzen and Po-Chun Chien and Yu-Shan Huang and Hoa-Ren Wang and Jie-Hong R. Jiang and Jiaqi Gu and Zheng Zhao and Zixuan Jiang and David Z. Pan and Brunno A. de Abreu and Isac de Souza Campos and Augusto Berndt and Cristina Meinhardt and Jonata T. Carvalho and Mateus Grellert and Sergio Bampi and Aditya Lohana and Akash Kumar and Wei Zeng and Azadeh Davoodi and Rasit O. Topaloglu and Yuan Zhou and Jordan Dotzel and Yichi Zhang and Hanyu Wang and Zhiru Zhang and Valerio Tenace and Pierre-Emmanuel Gaillardon and Alan Mishchenko and Satrajit Chatterjee},
 title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
 booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
 }DownloadsDATE_version_IWLS [PDF] Permalink
- 88. Shubham Rai, Mengyun Liu, Anteneh Gebregiorgis, Debjyoti Bhattacharjee, Krishnendu Chakrabarty, Said Hamdioui, Anupam Chattopadhyay, Jens Trommer, Akash Kumar, "Perspectives on Emerging Computation-in-Memory Paradigms" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]        [Bibtex & Downloads]
                Perspectives on Emerging Computation-in-Memory Paradigms×ReferenceShubham Rai, Mengyun Liu, Anteneh Gebregiorgis, Debjyoti Bhattacharjee, Krishnendu Chakrabarty, Said Hamdioui, Anupam Chattopadhyay, Jens Trommer, Akash Kumar, "Perspectives on Emerging Computation-in-Memory Paradigms" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] Bibtex@inproceedings{Rai_2021,
 doi = {10.23919/date51398.2021.9473976},
 url = {https://doi.org/10.23919%2Fdate51398.2021.9473976},
 year = 2021,
 month = {feb},
 publisher = ,
 author = {Shubham Rai and Mengyun Liu and Anteneh Gebregiorgis and Debjyoti Bhattacharjee and Krishnendu Chakrabarty and Said Hamdioui and Anupam Chattopadhyay and Jens Trommer and Akash Kumar},
 title = {Perspectives on Emerging Computation-in-Memory Paradigms},
 booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
 }DownloadsDATE_2021_SS_In_Memory_Computing [PDF] Permalink
- 87. Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]        [Bibtex & Downloads]
                Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies×ReferenceShubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] Bibtex@inproceedings{Rai_2021,
 doi = {10.23919/date51398.2021.9474112},
 url = {https://doi.org/10.23919%2Fdate51398.2021.9474112},
 year = 2021,
 month = {feb},
 publisher = ,
 author = {Shubham Rai and Heinz Riener and Giovanni De Micheli and Akash Kumar},
 title = {Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies},
 booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
 }DownloadsDATE_2021_preserving [PDF] Permalink
- 86. Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar, "Vertical IP Protection of the Next-Generation Devices: Quo Vadis?" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]        [Bibtex & Downloads]
                Vertical IP Protection of the Next-Generation Devices: Quo Vadis?×ReferenceShubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar, "Vertical IP Protection of the Next-Generation Devices: Quo Vadis?" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] Bibtex@inproceedings{Rai_2021,
 doi = {10.23919/date51398.2021.9474132},
 url = {https://doi.org/10.23919%2Fdate51398.2021.9474132},
 year = 2021,
 month = {feb},
 publisher = ,
 author = {Shubham Rai and Siddharth Garg and Christian Pilato and Vladimir Herdt and Elmira Moussavi and Dominik Sisejkovic and Ramesh Karri and Rolf Drechsler and Farhad Merchant and Akash Kumar},
 title = {Vertical {IP} Protection of the Next-Generation Devices: Quo Vadis?},
 booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
 }DownloadsDATE_2021_SS_Security_Emerging(5) [PDF] Permalink
- 85. Sadia Moriam, Elke Franz, Paul Walther, Akash Kumar, Thorsten Strufe, Gerhard Fettweis, "Efficient Communication Protection of Many-Core Systems against Active Attackers", In Electronics, MDPI AG, vol. 10, no. 3, pp. 238, Jan 2021. [doi]        [Bibtex & Downloads]
                Efficient Communication Protection of Many-Core Systems against Active Attackers×ReferenceSadia Moriam, Elke Franz, Paul Walther, Akash Kumar, Thorsten Strufe, Gerhard Fettweis, "Efficient Communication Protection of Many-Core Systems against Active Attackers", In Electronics, MDPI AG, vol. 10, no. 3, pp. 238, Jan 2021. [doi] Bibtex@article{Moriam_2021,
 doi = {10.3390/electronics10030238},
 url = {https://doi.org/10.3390%2Felectronics10030238},
 year = 2021,
 month = {jan},
 publisher = {{MDPI} {AG}},
 volume = {10},
 number = {3},
 pages = {238},
 author = {Sadia Moriam and Elke Franz and Paul Walther and Akash Kumar and Thorsten Strufe and Gerhard Fettweis},
 title = {Efficient Communication Protection of Many-Core Systems against Active Attackers},
 journal = {Electronics}
 }Downloadselectronics-10-00238-v2 [PDF] Related PathsPermalink
- 84. Siva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar, "Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 1, pp. 7, Jan 2021. [doi]        [Bibtex & Downloads]
                Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper×ReferenceSiva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar, "Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 1, pp. 7, Jan 2021. [doi] Bibtex@article{Sahoo_2021,
 doi = {10.3390/jlpea11010007},
 url = {https://doi.org/10.3390%2Fjlpea11010007},
 year = 2021,
 month = {jan},
 publisher = {{MDPI} {AG}},
 volume = {11},
 number = {1},
 pages = {7},
 author = {Siva Satyendra Sahoo and Behnaz Ranjbar and Akash Kumar},
 title = {Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper},
 journal = {Journal of Low Power Electronics and Applications}
 }Downloadsjlpea-11-00007 [PDF] Permalink
- 83. Cecilia De la Parra, Xuyi Wu, Akash Kumar, Andre Guntoro, "Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021.        [Bibtex & Downloads]
                Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks×ReferenceCecilia De la Parra, Xuyi Wu, Akash Kumar, Andre Guntoro, "Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. Bibtex@INPROCEEDINGS{cecilia_2021_date,
 author={Cecilia De la Parra and Xuyi Wu and Akash Kumar and Andre Guntoro},
 booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
 title= {Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks},
 year= {2021},
 organization={IEEE},
 }DownloadsKnowledge_Distillation_DATE21 [PDF] Permalink
- 82. Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling", In Proceeding: 2021 Asia and South Pacific Design Automation Conference (ASPDAC), 2021.        [Bibtex & Downloads]
                Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling×ReferenceCecilia De la Parra, Andre Guntoro, Akash Kumar, "Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling", In Proceeding: 2021 Asia and South Pacific Design Automation Conference (ASPDAC), 2021. Bibtex@INPROCEEDINGS{cecilia_2021_aspdac,
 author={Cecilia De la Parra and Andre Guntoro and Akash Kumar},
 booktitle={2021 Asia and South Pacific Design Automation Conference (ASPDAC)},
 title={Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling},
 year={2021},
 organization={IEEE},
 }DownloadsApprox_Neural_Network_ASPDAC [PDF] Permalink
- 81. Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Herrmann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer, "Nano Security: From Nano-Electronics To Secure Systems", In Proceeding: 2021 Design and Automation & Test in Europe Conference & Exhibition (DATE), 2021.        [Bibtex & Downloads]
                Nano Security: From Nano-Electronics To Secure Systems×ReferenceIlia Polian, Frank Altmann, Tolga Arul, Christian Boit, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Herrmann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer, "Nano Security: From Nano-Electronics To Secure Systems", In Proceeding: 2021 Design and Automation & Test in Europe Conference & Exhibition (DATE), 2021. Bibtex@InProceedings{akash2021date-ss5,
 author= {Ilia Polian and Frank Altmann and Tolga Arul and Christian Boit and Lucas Davi and Rolf Drechsler and Nan Du and Thomas Eisenbarth and Tim Güneysu and Sascha Herrmann and Matthias Hiller and Rainer Leupers and Farhad Merchant and Thomas Mussenbrock and Stefan Katzenbeisser and Akash Kumar and Wolfgang Kunz and Thomas Mikolajick and Vivek Pachauri and Jean-Pierre Seifert and Frank Sill Torres and Jens Trommer},
 booktitle= {2021 Design and Automation & Test in Europe Conference & Exhibition (DATE)},
 title= {Nano Security: From Nano-Electronics To Secure Systems},
 year= {2021},
 organization = {IEEE},
 }DownloadsDATE_21_Nano_Security [PDF] Permalink
- 80. Salim Ullah, Semeen Rehman, Muhammad Shafique, Akash Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi]        [Bibtex & Downloads]
                High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators×ReferenceSalim Ullah, Semeen Rehman, Muhammad Shafique, Akash Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi] Bibtex@article{Ullah_2021,
 doi = {10.1109/tcad.2021.3056337},
 url = {https://doi.org/10.1109%2Ftcad.2021.3056337},
 year = 2021,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Salim Ullah and Semeen Rehman and Muhammad Shafique and Akash Kumar},
 title = {High-Performance Accurate and Approximate Multipliers for {FPGA}-based Hardware Accelerators},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
 }Downloadsacc_app_TCAD [PDF] Related Pathsother Permalink
- 79. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "RECON: Resource-Efficient CORDIC-Based Neuron Architecture", In IEEE Open Journal of Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 2, pp. 170–181, 2021. [doi]        [Bibtex & Downloads]
                RECON: Resource-Efficient CORDIC-Based Neuron Architecture×ReferenceGopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "RECON: Resource-Efficient CORDIC-Based Neuron Architecture", In IEEE Open Journal of Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 2, pp. 170–181, 2021. [doi] Bibtex@article{Raut_2021,
 doi = {10.1109/ojcas.2020.3042743},
 url = {https://doi.org/10.1109%2Fojcas.2020.3042743},
 year = 2021,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 volume = {2},
 pages = {170--181},
 author = {Gopal Raut and Shubham Rai and Santosh Kumar Vishvakarma and Akash Kumar},
 title = {{RECON}: Resource-Efficient {CORDIC}-Based Neuron Architecture},
 journal = {{IEEE} Open Journal of Circuits and Systems}
 }DownloadsRecon [PDF] Permalink
- 2020
- 78. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi]        [Bibtex & Downloads]
                ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems×ReferenceAkhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] Bibtex@article{Baranwal_2020,
 doi = {10.1109/tcad.2020.3028350},
 url = {https://doi.org/10.1109%2Ftcad.2020.3028350},
 year = 2020,
 month={28 October},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Akhil Raj Baranwal and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
 title = {{ReLAccS}: A Multi-level Approach to Accelerator Design for Reinforcement Learning on {FPGA}-based Systems},
 journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
 }DownloadsReLAccS_TCAD_Author-prepared [PDF] Permalink
- 77. Arlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors", In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi]        [Bibtex & Downloads]
                An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors×ReferenceArlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors", In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi] Bibtex@inproceedings{John_2020,
 doi = {10.1109/icecs49266.2020.9294859},
 url = {https://doi.org/10.1109%2Ficecs49266.2020.9294859},
 year = 2020,
 month = {nov},
 publisher = ,
 author = {Arlene John and Salim Ullah and Akash Kumar and Barry Cardiff and Deepu John},
 title = {An Approximate Binary Classifier for Data Integrity Assessment in {IoT} Sensors},
 booktitle = {2020 27th {IEEE} International Conference on Electronics, Circuits and Systems ({ICECS})}
 }DownloadsApproximate_binary_classifier [PDF] Permalink
- 76. Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi]        [Bibtex & Downloads]
                Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits×ReferenceShubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi] Bibtex@article{Rai_2020,
 doi = {10.1109/tetc.2020.3039375},
 url = {https://doi.org/10.1109%2Ftetc.2020.3039375},
 year = 2020,
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Shubham Rai and Satwik Patnaik and Ansh Rupani and Johann Knechtel and Ozgur Sinanoglu and Akash Kumar},
 title = {Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits},
 journal = {{IEEE} Transactions on Emerging Topics in Computing}
 }DownloadsTETC_Security_author-copy [PDF] Permalink
- 75. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems", In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020.        [Bibtex & Downloads]
                Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems×ReferenceSiva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems", In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020. Bibtex@InProceedings{SahooVK020,
 author = {Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
 title = ,
 booktitle = {2020 {IEEE} {International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020}},
 year = {2020},
 month = {October},
 }DownloadsNo Downloads available for this publication Permalink
- 74. Behnaz Ranjbar, Bardia Safaei, Alireza Ejlali, Akash Kumar, "FANTOM: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, October 2020. [doi]        [Bibtex & Downloads]
                FANTOM: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems×ReferenceBehnaz Ranjbar, Bardia Safaei, Alireza Ejlali, Akash Kumar, "FANTOM: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, October 2020. [doi] Bibtex@article{Ranjbar_2020,
 doi = {10.1109/access.2020.3031039},
 url = {https://doi.org/10.1109%2Faccess.2020.3031039},
 year = 2020,
 month = {October},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 pages = {1--1},
 author = {Behnaz Ranjbar and Bardia Safaei and Alireza Ejlali and Akash Kumar},
 title = {{FANTOM}: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems},
 journal = {{IEEE} Access}
 }DownloadsACCESS3031039-author-accepted [PDF] Related PathsPermalink
- 73. Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Full Approximation of Deep Neural Networks through Efficient Optimization", In Proceeding: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Oct 2020. [doi]        [Bibtex & Downloads]
                Full Approximation of Deep Neural Networks through Efficient Optimization×ReferenceCecilia De la Parra, Andre Guntoro, Akash Kumar, "Full Approximation of Deep Neural Networks through Efficient Optimization", In Proceeding: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Oct 2020. [doi] Bibtex@inproceedings{De_la_Parra_2020,
 doi = {10.1109/iscas45731.2020.9181236},
 url = {https://doi.org/10.1109%2Fiscas45731.2020.9181236},
 year = 2020,
 month = {oct},
 publisher = ,
 author = {Cecilia De la Parra and Andre Guntoro and Akash Kumar},
 title = {Full Approximation of Deep Neural Networks through Efficient Optimization},
 booktitle = {2020 {IEEE} International Symposium on Circuits and Systems ({ISCAS})}
 }Downloadsiscas-2020-camera-ready [PDF] Permalink
- 72. Zahra Ebrahimi, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", Proceedings of the 2020 on Great Lakes Symposium on VLSI, ACM, Sep 2020. [doi]        [Bibtex & Downloads]
                SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy×ReferenceZahra Ebrahimi, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", Proceedings of the 2020 on Great Lakes Symposium on VLSI, ACM, Sep 2020. [doi] Bibtex@inproceedings{Ebrahimi_2020,
 doi = {10.1145/3386263.3406907},
 url = {https://doi.org/10.1145%2F3386263.3406907},
 year = 2020,
 month = {sep},
 publisher = ,
 author = {Zahra Ebrahimi and Salim Ullah and Akash Kumar},
 title = {{SIMDive}: Approximate {SIMD} Soft Multiplier-Divider for {FPGAs} with Tunable Accuracy},
 booktitle = {Proceedings of the 2020 on Great Lakes Symposium on {VLSI}}
 }DownloadsSIMDive_GLSVLSI_2020 [PDF] Related PathsPermalink
- 71. S. S. Sahoo, B. Veeravalli, A. Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems", In Proceeding: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2020. [doi]        [Bibtex & Downloads]
                CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems×ReferenceS. S. Sahoo, B. Veeravalli, A. Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems", In Proceeding: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2020. [doi] Bibtex@INPROCEEDINGS{9218747,
 author={S. S. {Sahoo} and B. {Veeravalli} and A. {Kumar}},
 booktitle={2020 57th ACM/IEEE Design Automation Conference (DAC)},
 title={CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems},
 year={2020},
 volume={},
 number={},
 pages={1-6},
 doi={10.1109/DAC18072.2020.9218747}}DownloadsCLRIntegTMap_DAC2020_CameraReady(1) [PDF] Related PathsPermalink
- 70. Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Improving approximate neural networks for perception tasks through specialized optimization", In Future Generation Computer Systems, vol. 113, pp. 597 - 606, July 2020. [doi]        [Bibtex & Downloads]
                Improving approximate neural networks for perception tasks through specialized optimization×ReferenceCecilia De la Parra, Andre Guntoro, Akash Kumar, "Improving approximate neural networks for perception tasks through specialized optimization", In Future Generation Computer Systems, vol. 113, pp. 597 - 606, July 2020. [doi] AbstractApproximate Computing has been proven successful in reducing the energy consumption of Deep Neural Networks (DNNs) implemented in embedded systems. For efficient DNN approximation at software and hardware levels, a specialized simulation environment and optimization methodology are required, to reduce execution and optimization times, as well as to maximize energy savings. Traditional frameworks for cross-layer approximate computation of DNNs are generally built only for simulation of convolutional and fully-connected layers, limiting the DNN types to be optimized through approximations. In this work, we present a specialized simulation environment for approximate DNNs, which allows for optimization of several DNN architectures built with more complex DNN layers such as depthwise convolutions and Recurrent Neural Units (RNNs) for time series processing. Low execution time overhead is achieved hereby through efficient GPU acceleration. Additionally, we deliver an analysis of approximate DNN and RNN robustness against quantization noise and different approximation levels. Finally, through specialized approximate retraining, we achieve promising energy savings and negligible accuracy losses with highly complex DNNs for image classification with ImageNet, such as MobileNet, and RNNs for keyword spotting with the Speech Commands Dataset. Bibtex@article{DELAPARRA2020597,
 title = "Improving approximate neural networks for perception tasks through specialized optimization",
 journal = "Future Generation Computer Systems",
 volume = "113",
 pages = "597 - 606",
 year = "2020",
 month = "July",
 issn = "0167-739X",
 doi = "https://doi.org/10.1016/j.future.2020.07.031",
 url = "http://www.sciencedirect.com/science/article/pii/S0167739X20301576",
 author = "Cecilia {De la Parra} and Andre Guntoro and Akash Kumar",
 keywords = "Approximate neural networks, Approximate computing, Approximate multipliers, Neural network optimization",
 abstract = "Approximate Computing has been proven successful in reducing the energy consumption of Deep Neural Networks (DNNs) implemented in embedded systems. For efficient DNN approximation at software and hardware levels, a specialized simulation environment and optimization methodology are required, to reduce execution and optimization times, as well as to maximize energy savings. Traditional frameworks for cross-layer approximate computation of DNNs are generally built only for simulation of convolutional and fully-connected layers, limiting the DNN types to be optimized through approximations. In this work, we present a specialized simulation environment for approximate DNNs, which allows for optimization of several DNN architectures built with more complex DNN layers such as depthwise convolutions and Recurrent Neural Units (RNNs) for time series processing. Low execution time overhead is achieved hereby through efficient GPU acceleration. Additionally, we deliver an analysis of approximate DNN and RNN robustness against quantization noise and different approximation levels. Finally, through specialized approximate retraining, we achieve promising energy savings and negligible accuracy losses with highly complex DNNs for image classification with ImageNet, such as MobileNet, and RNNs for keyword spotting with the Speech Commands Dataset.",
 }DownloadsElsevier_Approx_DNN [PDF] Permalink
- 69. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications", In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2020. [doi]        [Bibtex & Downloads]
                A CORDIC Based Configurable Activation Function for ANN Applications×ReferenceGopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications", In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2020. [doi] AbstractAn efficient ASIC-based hardware design of activation function (AF) in neural networks faces the challenge of offering functional configurability and limited chip area. Therefore an area-efficient configurable architecture for an AF is imperative to fully harness the parallel processing capacity of an ASIC in contrast to a general-purpose processor. To address this, we propose a configurable AF based on the shift-and-add algorithm, collectively known as Co-ordinate Rotation Digital Computer(CORDIC) algorithm. The proposed versatile configurable activation function is designed using CORDIC architecture and implements both tan hyperbolic and sigmoid function. The derived model is synthesized and verified at 45nm technology. Further, in order to address leakage issues at lower technology nodes, we exploit the power-gating technique for the proposed AF based on CORDIC architecture. Our circuit design is extracted in cadence virtuoso and simulated for all physical parameters. With respect to the state-of-the-art, our design architecture shows improvement by 29% in area, 42% in power dissipation and 20% in latency. The used power gating technique saves 30% static power with minimal area overhead. The Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that mean and σ deviation are 180.73µW and 51.7µW respectively which is 60% of the state-of-the-art. Bibtex@inproceedings{Raut_2020,
 doi = {10.1109/isvlsi49217.2020.00024},
 url = {https://doi.org/10.1109%2Fisvlsi49217.2020.00024},
 year = 2020,
 month = {jul},
 publisher = ,
 author = {Gopal Raut and Shubham Rai and Santosh Kumar Vishvakarma and Akash Kumar},
 title = {A {CORDIC} Based Configurable Activation Function for {ANN} Applications},
 booktitle = {2020 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
 }DownloadsISVLSI 2020 Paper [PDF] Permalink
- 68. M. Raitza, S. Märcker, J. Trommer, A. Heinzig, S. Klüppelholz, C. Baier, A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates", In IEEE Access, pp. 1-1, June 2020.        [Bibtex & Downloads]
                Quantitative Characterization of Reconfigurable Transistor Logic Gates×ReferenceM. Raitza, S. Märcker, J. Trommer, A. Heinzig, S. Klüppelholz, C. Baier, A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates", In IEEE Access, pp. 1-1, June 2020. Bibtex@ARTICLE{9113477,
 author={M. {Raitza} and S. {Märcker} and J. {Trommer} and A. {Heinzig} and S. {Klüppelholz} and C. {Baier} and A. {Kumar}},
 journal={IEEE Access},
 title={Quantitative Characterization of Reconfigurable Transistor Logic Gates},
 year={2020},
 month={June},
 volume={},
 number={},
 pages={1-1},}Downloads09113477 [PDF] Related PathsPermalink
- 67. S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks", In IEEE Access, vol. 8, pp. 118899-118911, June 2020.        [Bibtex & Downloads]
                ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks×ReferenceS. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks", In IEEE Access, vol. 8, pp. 118899-118911, June 2020. Bibtex@ARTICLE{9126777,
 author={S. {Gupta} and S. {Ullah} and K. {Ahuja} and A. {Tiwari} and A. {Kumar}},
 journal={IEEE Access},
 title={ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks},
 year={2020},
 month={June},
 volume={8},
 number={},
 pages={118899-118911},}DownloadsALigN [PDF] Permalink
- 66. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020.        [Bibtex & Downloads]
                Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures×ReferenceS. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020. Bibtex@ARTICLE{9072581,
 author={S. {Ullah} and H. {Schmidl} and S. S. {Sahoo} and S. {Rehman} and A. {Kumar}},
 journal={IEEE Transactions on Computers},
 title={Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures},
 year={2020},
 month={April},}DownloadsTC_2019_Accurate_Approx_Multiplier [PDF] Permalink
- 65. S. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020.        [Bibtex & Downloads]
                L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS×ReferenceS. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. Bibtex@INPROCEEDINGS{date_salim,
 author={S. Ullah and S. Gupta and K. Ahuja and A. Tiwari and A. Kumar},
 booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
 title={L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS},
 year={2020},
 month={March},}DownloadsL2L_Date_2020 [PDF] Permalink
- 64. C. D. L. Parra, A. Guntoro, A. Kumar, "PROXSIM: SIMULATION FRAMEWORK FOR CROSS-LAYER APPROXIMATE DNN OPTIMIZATION", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. (Best paper nominee)        [Bibtex & Downloads]
                PROXSIM: SIMULATION FRAMEWORK FOR CROSS-LAYER APPROXIMATE DNN OPTIMIZATION×ReferenceC. D. L. Parra, A. Guntoro, A. Kumar, "PROXSIM: SIMULATION FRAMEWORK FOR CROSS-LAYER APPROXIMATE DNN OPTIMIZATION", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. (Best paper nominee) Bibtex@INPROCEEDINGS{date_Cecilia,
 author={C. D. L. Parra and A. Guntoro and A. Kumar},
 booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
 title={PROXSIM: SIMULATION FRAMEWORK FOR CROSS-LAYER APPROXIMATE DNN OPTIMIZATION},
 year={2020},
 month={March},
 }Downloadsdate_framework [PDF] Permalink
- 63. S. Potluri, A. Aysu, A. Kumar, "SeqL: Secure Scan-Locking for IP Protection", In Proceeding: 21st International Symposium on Quality Electronic Design (ISQED), March 2020.        [Bibtex & Downloads]
                SeqL: Secure Scan-Locking for IP Protection×ReferenceS. Potluri, A. Aysu, A. Kumar, "SeqL: Secure Scan-Locking for IP Protection", In Proceeding: 21st International Symposium on Quality Electronic Design (ISQED), March 2020. Bibtex@INPROCEEDINGS{date_Seetal,
 author={S. Potluri and A. Aysu and A. Kumar},
 booktitle={21st International Symposium on Quality Electronic Design (ISQED)},
 title={SeqL: Secure Scan-Locking for IP Protection},
 year={2020},
 month={March},}DownloadsSeqL_ISQED2020_CamReady [PDF] Permalink
- 62. Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi]        [Bibtex & Downloads]
                DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies×ReferenceShubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi] Bibtex@inproceedings{Rai_2020,
 doi = {10.23919/date48585.2020.9116216},
 url = {https://doi.org/10.23919%2Fdate48585.2020.9116216},
 year = 2020,
 month = {mar},
 publisher = ,
 author = {Shubham Rai and Michael Raitza and Siva Satyendra Sahoo and Akash Kumar},
 title = {{DiSCERN}: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies},
 booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
 }DownloadsDiSCERN_DATE_2020 [PDF] Permalink
- 61. Tuan D. A. Nguyen, Akash Kumar, "Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment", In Proceeding: 28th International Symposium on Field-Programmable Gate Arrays, February 2020.        [Bibtex & Downloads]
                Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment×ReferenceTuan D. A. Nguyen, Akash Kumar, "Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment", In Proceeding: 28th International Symposium on Field-Programmable Gate Arrays, February 2020. Bibtex@INPROCEEDINGS{tuanFPGA,
 author={Tuan D. A. Nguyen and Akash Kumar},
 booktitle={28th International Symposium on Field-Programmable Gate Arrays},
 title={Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment},
 year={2020},
 month={February},}Downloadsserviceability-fpga-058-2020-camera_ready [PDF] Permalink
- 60. Zahra Ebrahimi, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, Jan 2020. [doi]        [Bibtex & Downloads]
                LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy×ReferenceZahra Ebrahimi, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, Jan 2020. [doi] Bibtex@inproceedings{Ebrahimi_2020,
 doi = {10.1109/asp-dac47756.2020.9045171},
 url = {https://doi.org/10.1109%2Fasp-dac47756.2020.9045171},
 year = 2020,
 month = {jan},
 publisher = ,
 author = {Zahra Ebrahimi and Salim Ullah and Akash Kumar},
 title = {{LeAp}: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy},
 booktitle = {2020 25th Asia and South Pacific Design Automation Conference ({ASP}-{DAC})}
 }DownloadsLeAp- [PDF] Permalink
- 59. Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies", [Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)], no. CONF, 2020.        [Bibtex & Downloads]
                XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies×ReferenceShubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies", [Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)], no. CONF, 2020. Bibtex@inproceedings{rai2020xmg,
 title={XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies},
 author={Rai, Shubham and Riener, Heinz and De Micheli, Giovanni and Kumar, Akash},
 booktitle={[Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)]},
 number={CONF},
 year={2020}
 }DownloadsXMG__Logic_Synthesis_Primitives_Exploring_Self_Duality [PDF] Permalink
- 2019
- 58. Rohit Agrawal, Kapil Ahuja, Chin Hau Hoo, Tuan Duy Anh Nguyen, Akash Kumar, "ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method", In Electronics, vol. 8, no. 12, December 2019. [doi]        [Bibtex & Downloads]
                ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method×ReferenceRohit Agrawal, Kapil Ahuja, Chin Hau Hoo, Tuan Duy Anh Nguyen, Akash Kumar, "ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method", In Electronics, vol. 8, no. 12, December 2019. [doi] AbstractIn the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it. In a recent work by Hoo et al., the authors have developed a linear programming (LP)-based framework that parallelizes this routing process to achieve significant speed-ups (the resulting algorithm is termed as ParaLaR). However, this approach has certain weaknesses. Namely, the constraints violation by the solution and a standard routing metric could be improved. We address these two issues here. In this paper, we use the LP framework of ParaLaR and solve it using the primal–dual sub-gradient method that better exploits the problem properties. We also propose a better way to update the size of the step taken by this iterative algorithm. We call our algorithm as ParaLarPD. We perform experiments on a set of standard benchmarks, where we show that our algorithm outperforms not just ParaLaR but the standard existing algorithm VPR as well. We perform experiments with two different configurations. We achieve 20 % average improvement in the constraints violation and the standard metric of the minimum channel width (both of which are related) when compared with ParaLaR. When compared to VPR, we get average improvements of 28 % in the minimum channel width (there is no constraints violation in VPR). We obtain the same value for the total wire length as by ParaLaR, which is 49 % better on an average than that obtained by VPR. This is the original metric to be minimized, for which ParaLaR was proposed. Next, we look at the third and easily measurable metric of critical path delay. On an average, ParaLarPD gives 2 % larger critical path delay than ParaLaR and 3 % better than VPR. We achieve maximum relative speed-ups of up to seven times when running a parallel version of our algorithm using eight threads as compared to the sequential implementation. These speed-ups are similar to those as obtained by ParaLaR. Bibtex@Article{electronics8121439,
 AUTHOR = {Agrawal, Rohit and Ahuja , Kapil and Hau Hoo, Chin and Duy Anh Nguyen, Tuan and Kumar, Akash},
 TITLE = {ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method},
 JOURNAL = {Electronics},
 VOLUME = {8},
 YEAR = {2019},
 MONTH={December},
 NUMBER = {12},
 ARTICLE-NUMBER = {1439},
 URL = {https://www.mdpi.com/2079-9292/8/12/1439},
 ISSN = {2079-9292},
 ABSTRACT = {In the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it. In a recent work by Hoo et al., the authors have developed a linear programming (LP)-based framework that parallelizes this routing process to achieve significant speed-ups (the resulting algorithm is termed as ParaLaR). However, this approach has certain weaknesses. Namely, the constraints violation by the solution and a standard routing metric could be improved. We address these two issues here. In this paper, we use the LP framework of ParaLaR and solve it using the primal–dual sub-gradient method that better exploits the problem properties. We also propose a better way to update the size of the step taken by this iterative algorithm. We call our algorithm as ParaLarPD. We perform experiments on a set of standard benchmarks, where we show that our algorithm outperforms not just ParaLaR but the standard existing algorithm VPR as well. We perform experiments with two different configurations. We achieve 20 % average improvement in the constraints violation and the standard metric of the minimum channel width (both of which are related) when compared with ParaLaR. When compared to VPR, we get average improvements of 28 % in the minimum channel width (there is no constraints violation in VPR). We obtain the same value for the total wire length as by ParaLaR, which is 49 % better on an average than that obtained by VPR. This is the original metric to be minimized, for which ParaLaR was proposed. Next, we look at the third and easily measurable metric of critical path delay. On an average, ParaLarPD gives 2 % larger critical path delay than ParaLaR and 3 % better than VPR. We achieve maximum relative speed-ups of up to seven times when running a parallel version of our algorithm using eight threads as compared to the sequential implementation. These speed-ups are similar to those as obtained by ParaLaR.},
 DOI = {10.3390/electronics8121439}
 }Downloadselectronics-08-01439 [PDF] Permalink
- 57. M. Mousavi, H. R. Pourshaghaghi, H. Corporaal, A. Kumar, "Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory", In Proceeding: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1-6, Oct 2019. [doi]        [Bibtex & Downloads]
                Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory×ReferenceM. Mousavi, H. R. Pourshaghaghi, H. Corporaal, A. Kumar, "Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory", In Proceeding: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1-6, Oct 2019. [doi] Bibtex@INPROCEEDINGS{8875431,
 author={M. {Mousavi} and H. R. {Pourshaghaghi} and H. {Corporaal} and A. {Kumar}},
 booktitle={2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)},
 title={Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory},
 year={2019},
 volume={},
 number={},
 pages={1-6},
 keywords={Field programmable gate arrays;Redundancy;Single event upsets;Maintenance engineering;Indexes;Fault tolerant systems;FPGA;fault tolerance;SEU;scrubbing;configuration memory},
 doi={10.1109/DFT.2019.8875431},
 ISSN={},
 month={Oct},}Downloads08875431 [PDF] Related PathsPermalink
- 56. Nusrat Jahan Lisa, Tuan D. A. Nguyen, Dirk Habich, Akash Kumar, Wolfgang Lehner, "High-Throughput Bit Packing Compression", In Proceeding: Euromicro DSD, August 2019.        [Bibtex & Downloads]
                High-Throughput Bit Packing Compression×ReferenceNusrat Jahan Lisa, Tuan D. A. Nguyen, Dirk Habich, Akash Kumar, Wolfgang Lehner, "High-Throughput Bit Packing Compression", In Proceeding: Euromicro DSD, August 2019. Bibtex@InProceedings{nusrat19high,
 author = {Nusrat Jahan Lisa and Tuan D. A. Nguyen and Dirk Habich and Akash Kumar and Wolfgang Lehner},
 title = {High-Throughput Bit Packing Compression},
 booktitle = {Euromicro DSD},
 year = {2019},
 month = {August},
 owner = {Ranjbar},
 }Downloadsdsd2019_fpga_crc [PDF] Permalink
- 55. Behnaz Ranjbar, Tuan D. A. Nguyen, A. Ejlali, A. Kumar, "Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 546-553, August 2019. [doi]        [Bibtex & Downloads]
                Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems×ReferenceBehnaz Ranjbar, Tuan D. A. Nguyen, A. Ejlali, A. Kumar, "Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 546-553, August 2019. [doi] Bibtex@InProceedings{ranjbar19online,
 author = {Behnaz Ranjbar and Tuan D. A. Nguyen and A. Ejlali and A. Kumar},
 title = {Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems},
 booktitle = { Euromicro Conference on Digital System Design (DSD)},
 year = {2019},
 month = {August},
 pages={546-553},
 doi={10.1109/DSD.2019.00084},
 owner = {Ranjbar},
 }DownloadsPermalink
- 54. Ansh Rupani, Shubham Rai, Akash Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: 2019 22nd Euromicro Conference on Digital System Design (DSD), IEEE, Aug 2019. [doi]        [Bibtex & Downloads]
                Exploiting Emerging Reconfigurable Technologies for Secure Devices×ReferenceAnsh Rupani, Shubham Rai, Akash Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: 2019 22nd Euromicro Conference on Digital System Design (DSD), IEEE, Aug 2019. [doi] Bibtex@inproceedings{Rupani_2019,
 doi = {10.1109/dsd.2019.00107},
 url = {https://doi.org/10.1109%2Fdsd.2019.00107},
 year = 2019,
 month = {aug},
 publisher = ,
 author = {Ansh Rupani and Shubham Rai and Akash Kumar},
 title = {Exploiting Emerging Reconfigurable Technologies for Secure Devices},
 booktitle = {2019 22nd Euromicro Conference on Digital System Design ({DSD})}
 }DownloadsDSD_final [PDF] Permalink
- 53. Shubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2019. [doi]        [Bibtex & Downloads]
                Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies×ReferenceShubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2019. [doi] Bibtex@inproceedings{Rai_2019,
 doi = {10.1109/isvlsi.2019.00123},
 url = {https://doi.org/10.1109%2Fisvlsi.2019.00123},
 year = 2019,
 month = {jul},
 publisher = ,
 author = {Shubham Rai and Ansh Rupani and Pallab Nath and Akash Kumar},
 title = {Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies},
 booktitle = {2019 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
 }DownloadsISVLSI [PDF] Permalink
- 52. S. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems", Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019. [doi]        [Bibtex & Downloads]
                A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems×ReferenceS. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems", Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019. [doi] Bibtex@inproceedings{SahooVK019_1,
 author = {S. S. Sahoo and B. Veeravalli and A. Kumar},
 title = ,
 booktitle = ,
 series = {DAC '19},
 year = {2019},
 month={june},
 isbn = {978-1-4503-6725-7/19/06},
 location = {Las Vegas, NV, USA},
 numpages = {6},
 url = {http://doi.acm.org/10.1145/3316781.3317746},
 doi = {10.1145/3316781.3317746},
 acmid = {3317746},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {Cross-layer Reliability, Run-time Resource Management, Embedded Systems, Reinforcement Learning},
 }Downloadsa38-Sahoo [PDF] Permalink
- 51. Adarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks", Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi]        [Bibtex & Downloads]
                Design Methodology for Embedded Approximate Artificial Neural Networks×ReferenceAdarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks", Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi] Bibtex@inproceedings{Balaji:2019:DME:3299874.3319490,
 author = {Balaji, Adarsha and Ullah, Salim and Das, Anup and Kumar, Akash},
 title = {Design Methodology for Embedded Approximate Artificial Neural Networks},
 booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI},
 series = {GLSVLSI '19},
 year = {2019},
 month={May},
 isbn = {978-1-4503-6252-8},
 location = {Tysons Corner, VA, USA},
 pages = {489--494},
 numpages = {6},
 url = {http://doi.acm.org/10.1145/3299874.3319490},
 doi = {10.1145/3299874.3319490},
 acmid = {3319490},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {approximate computing, artificial neural networks (anns), fpga},
 }Downloadsp489-balaji [PDF] Permalink
- 50. Mohammed Alser, Hasan Hassan, Akash Kumar, Onur Mutlu, Can Alkan, "Shouji: a fast and efficient pre-alignment filter for sequence alignment", In Bioinformatics, vol. 35, no. 21, pp. 4255-4263, 03/2019. [doi]        [Bibtex & Downloads]
                Shouji: a fast and efficient pre-alignment filter for sequence alignment×ReferenceMohammed Alser, Hasan Hassan, Akash Kumar, Onur Mutlu, Can Alkan, "Shouji: a fast and efficient pre-alignment filter for sequence alignment", In Bioinformatics, vol. 35, no. 21, pp. 4255-4263, 03/2019. [doi] AbstractThe ability to generate massive amounts of sequencing data continues to overwhelm the processing capability of existing algorithms and compute infrastructures. In this work, we explore the use of hardware/software co-design and hardware acceleration to significantly reduce the execution time of short sequence alignment, a crucial step in analyzing sequenced genomes. We introduce Shouji, a highly parallel and accurate pre-alignment filter that remarkably reduces the need for computationally-costly dynamic programming algorithms. The first key idea of our proposed pre-alignment filter is to provide high filtering accuracy by correctly detecting all common subsequences shared between two given sequences. The second key idea is to design a hardware accelerator that adopts modern field-programmable gate array (FPGA) architectures to further boost the performance of our algorithm.Shouji significantly improves the accuracy of pre-alignment filtering by up to two orders of magnitude compared to the state-of-the-art pre-alignment filters, GateKeeper and SHD. Our FPGA-based accelerator is up to three orders of magnitude faster than the equivalent CPU implementation of Shouji. Using a single FPGA chip, we benchmark the benefits of integrating Shouji with five state-of-the-art sequence aligners, designed for different computing platforms. The addition of Shouji as a pre-alignment step reduces the execution time of the five state-of-the-art sequence aligners by up to 18.8×. Shouji can be adapted for any bioinformatics pipeline that performs sequence alignment for verification. Unlike most existing methods that aim to accelerate sequence alignment, Shouji does not sacrifice any of the aligner capabilities, as it does not modify or replace the alignment step.https://github.com/CMU-SAFARI/Shouji.Supplementary data are available at Bioinformatics online. Bibtex@article{10.1093/bioinformatics/btz234,
 author = {Alser, Mohammed and Hassan, Hasan and Kumar, Akash and Mutlu, Onur and Alkan, Can},
 title = "{Shouji: a fast and efficient pre-alignment filter for sequence alignment}",
 journal = {Bioinformatics},
 volume = {35},
 number = {21},
 pages = {4255-4263},
 year = {2019},
 month = {03},
 abstract = "{The ability to generate massive amounts of sequencing data continues to overwhelm the processing capability of existing algorithms and compute infrastructures. In this work, we explore the use of hardware/software co-design and hardware acceleration to significantly reduce the execution time of short sequence alignment, a crucial step in analyzing sequenced genomes. We introduce Shouji, a highly parallel and accurate pre-alignment filter that remarkably reduces the need for computationally-costly dynamic programming algorithms. The first key idea of our proposed pre-alignment filter is to provide high filtering accuracy by correctly detecting all common subsequences shared between two given sequences. The second key idea is to design a hardware accelerator that adopts modern field-programmable gate array (FPGA) architectures to further boost the performance of our algorithm.Shouji significantly improves the accuracy of pre-alignment filtering by up to two orders of magnitude compared to the state-of-the-art pre-alignment filters, GateKeeper and SHD. Our FPGA-based accelerator is up to three orders of magnitude faster than the equivalent CPU implementation of Shouji. Using a single FPGA chip, we benchmark the benefits of integrating Shouji with five state-of-the-art sequence aligners, designed for different computing platforms. The addition of Shouji as a pre-alignment step reduces the execution time of the five state-of-the-art sequence aligners by up to 18.8×. Shouji can be adapted for any bioinformatics pipeline that performs sequence alignment for verification. Unlike most existing methods that aim to accelerate sequence alignment, Shouji does not sacrifice any of the aligner capabilities, as it does not modify or replace the alignment step.https://github.com/CMU-SAFARI/Shouji.Supplementary data are available at Bioinformatics online.}",
 issn = {1367-4803},
 doi = {10.1093/bioinformatics/btz234},
 url = {https://doi.org/10.1093/bioinformatics/btz234},
 eprint = {https://academic.oup.com/bioinformatics/article-pdf/35/21/4255/30330769/btz234.pdf},
 }DownloadsNo Downloads available for this publication Permalink
- 49. Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 27, no. 3, pp. 560–572, Mar 2019. [doi]        [Bibtex & Downloads]
                Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors×ReferenceShubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 27, no. 3, pp. 560–572, Mar 2019. [doi] Bibtex@article{Rai_2019,
 doi = {10.1109/tvlsi.2018.2884646},
 url = {https://doi.org/10.1109%2Ftvlsi.2018.2884646},
 year = 2019,
 month = {mar},
 publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
 volume = {27},
 number = {3},
 pages = {560--572},
 author = {Shubham Rai and Jens Trommer and Michael Raitza and Thomas Mikolajick and Walter M. Weber and Akash Kumar},
 title = {Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors},
 journal = {{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}
 }Downloads08580544 [PDF] Related PathsPermalink
- 48. Gerhard Fettweis, Meik Dörpinghaus, Jeronimo Castrillon, Akash Kumar, Christel Baier, Karlheinz Bock, Frank Ellinger, Andreas Fery, Frank H. P. Fitzek, Hermann Härtig, Kambiz Jamshidi, Thomas Kissinger, Wolfgang Lehner, Michael Mertig, Wolfgang E. Nagel, Giang T. Nguyen, Dirk Plettemeier, Michael Schröter, Thorsten Strufe, "Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy-Efficient Computing", In Proceedings of the IEEE, vol. 107, no. 1, pp. 204–231, Jan 2019. [doi]        [Bibtex & Downloads]
                Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy-Efficient Computing×ReferenceGerhard Fettweis, Meik Dörpinghaus, Jeronimo Castrillon, Akash Kumar, Christel Baier, Karlheinz Bock, Frank Ellinger, Andreas Fery, Frank H. P. Fitzek, Hermann Härtig, Kambiz Jamshidi, Thomas Kissinger, Wolfgang Lehner, Michael Mertig, Wolfgang E. Nagel, Giang T. Nguyen, Dirk Plettemeier, Michael Schröter, Thorsten Strufe, "Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy-Efficient Computing", In Proceedings of the IEEE, vol. 107, no. 1, pp. 204–231, Jan 2019. [doi] Bibtex@Article{fettweis_ieeeproc19,
 author = {Gerhard Fettweis and Meik D{\"o}rpinghaus and Jeronimo Castrillon and Akash Kumar and Christel Baier and Karlheinz Bock and Frank Ellinger and Andreas Fery and Frank H. P. Fitzek and Hermann H{\"a}rtig and Kambiz Jamshidi and Thomas Kissinger and Wolfgang Lehner and Michael Mertig and Wolfgang E. Nagel and Giang T. Nguyen and Dirk Plettemeier and Michael Schr{\"o}ter and Thorsten Strufe},
 title = {Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy-Efficient Computing},
 journal = {Proceedings of the IEEE},
 year = {2019},
 volume = {107},
 number = {1},
 pages = {204--231},
 month = jan,
 doi = {10.1109/JPROC.2018.2874895},
 issn = {0018-9219},
 url = {https://ieeexplore.ieee.org/document/8565890}
 }Downloads1812_Fettweis_IEEEProc [PDF] Related PathsPermalink
- 2018
- 47. S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning", In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), pp. 230-233, Dec 2018. [doi]        [Bibtex & Downloads]
                QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning×ReferenceS. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning", In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), pp. 230-233, Dec 2018. [doi] Bibtex@INPROCEEDINGS{8742320,
 author={S. S. {Sahoo} and T. D. A. {Nguyen} and B. {Veeravalli} and A. {Kumar}},
 booktitle={2018 International Conference on Field-Programmable Technology (FPT)},
 title={QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning},
 year={2018},
 volume={},
 number={},
 pages={230-233},
 keywords={circuit optimisation;field programmable gate arrays;integrated circuit design;integrated circuit reliability;logic design;quality of service;Dynamic Partial Reconfiguration;QoS-aware cross-layer reliability-integrated design methodology;FPGA-based DPR systems;FPGA-based dynamic partially reconfigurable system;partially reconfigurable modules;quality of service;fault-mitigation;Conferences;Cross-layer Reliability;Dynamic Partial Reconfiguration;Field Programmable Gate Array;Embedded Systems},
 doi={10.1109/FPT.2018.00041},
 ISSN={},
 month={Dec},}Downloads08742320 [PDF] Permalink
- 46. Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?", Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi]        [Bibtex & Downloads]
                Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?×ReferenceShubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?", Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi] Bibtex@inproceedings{Rai:2018:ERN:3240765.3243472,
 author = {Rai, Shubham and Srinivasa, Srivatsa and Cadareanu, Patsy and Yin, Xunzhao and Hu, Xiaobo Sharon and Gaillardon, Pierre-Emmanuel and Narayanan, Vijaykrishnan and Kumar, Akash},
 title = {Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?},
 booktitle = {Proceedings of the International Conference on Computer-Aided Design},
 series = {ICCAD '18},
 year = {2018},
 month = {November},
 isbn = {978-1-4503-5950-4},
 location = {San Diego, California},
 pages = {13:1--13:8},
 articleno = {13},
 numpages = {8},
 url = {http://doi.acm.org/10.1145/3240765.3243472},
 doi = {10.1145/3240765.3243472},
 acmid = {3243472},
 publisher = {ACM},
 address = {New York, NY, USA},
 }DownloadsPID5531423 [PDF] Related PathsPermalink
- 45. S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems", In Integration, November 2018. [doi]        [Bibtex & Downloads]
                Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems×ReferenceS.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems", In Integration, November 2018. [doi] AbstractDynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification. Bibtex@article{SAHOO2018,
 title = "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems",
 journal = "Integration",
 year = "2018",
 month={November},
 issn = "0167-9260",
 doi = "https://doi.org/10.1016/j.vlsi.2018.10.006",
 url = "http://www.sciencedirect.com/science/article/pii/S0167926018302608",
 author = "S.S. Sahoo and T.D.A. Nguyen and B. Veeravalli and A. Kumar",
 keywords = "Dynamic partial reconfiguration, Field programmable gate arrays, Lifetime-aware scheduling, Task-graphs, Reliability, Heterogeneous systems, Real-time systems",
 abstract = "Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification."
 }DownloadsMulti-objective design_space_exploration [PDF] Permalink
- 44. Rohit Agrawal, Chin Hao Hoo, Kapil Ahuja, Akash Kumar, "Parallel FPGA Router using Sub-Gradient method and Steiner tree", In arXiv preprint arXiv:1803.03885, August 2018.        [Bibtex & Downloads]
                Parallel FPGA Router using Sub-Gradient method and Steiner tree×ReferenceRohit Agrawal, Chin Hao Hoo, Kapil Ahuja, Akash Kumar, "Parallel FPGA Router using Sub-Gradient method and Steiner tree", In arXiv preprint arXiv:1803.03885, August 2018. Bibtex@article{agrawal2018parallel,
 title={Parallel FPGA Router using Sub-Gradient method and Steiner tree},
 author={Agrawal, Rohit and Hoo, Chin Hao and Ahuja, Kapil and Kumar, Akash},
 journal={arXiv preprint arXiv:1803.03885},
 year={2018},
 month={August}
 }DownloadsParallel_FPGA_Router_Rohit [PDF] Permalink
- 43. Jeronimo Castrillon, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems", In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi]        [Bibtex & Downloads]
                A Hardware/Software Stack for Heterogeneous Systems×ReferenceJeronimo Castrillon, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems", In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi] AbstractPlenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore. Bibtex@Article{castrillon_tmscs17,
 author = {Jeronimo Castrillon and Matthias Lieber and Sascha Kl{\"u}ppelholz and Marcus V{\"o}lp and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fr{\"o}hlich and Andr\'{e}s Goens and Sebastian Haas and Dirk Habich and Hermann H{\"a}rtig and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Akash Kumar and Wolfgang Lehner and Linda Leuschner and Siqi Ling and Steffen M{\"a}rcker and Christian Menard and Johannes Mey and Wolfgang Nagel and Benedikt N{\"o}then and Rafael Pe{\~n}aloza and Michael Raitza and J{\"o}rg Stiller and Annett Ungeth{\"u}m and Axel Voigt and Sascha Wunderlich},
 title = {A Hardware/Software Stack for Heterogeneous Systems},
 journal = {IEEE Transactions on Multi-Scale Computing Systems},
 year = {2018},
 month = jul,
 volume={4},
 number={3},
 pages={243-259},
 abstract = {Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.},
 doi = {10.1109/TMSCS.2017.2771750},
 issn = {2332-7766},
 url = {http://ieeexplore.ieee.org/document/8103042/}
 }Downloads1711_Castrillon_TMSCS [PDF] Related PathsPermalink
- 42. Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Nguyen Duy Anh Tuan, Akash Kumar, Wolfgang Lehner, "Column Scan Optimization by Increasing Intra-Instruction Parallelism", Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA), July 2018. (Best Paper Award)        [Bibtex & Downloads]
                Column Scan Optimization by Increasing Intra-Instruction Parallelism×ReferenceNusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Nguyen Duy Anh Tuan, Akash Kumar, Wolfgang Lehner, "Column Scan Optimization by Increasing Intra-Instruction Parallelism", Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA), July 2018. (Best Paper Award) Bibtex@InProceedings{lisaDATA2018,
 author = {Nusrat Jahan Lisa and Annett Ungethüm and Dirk Habich and Nguyen Duy Anh Tuan and Akash Kumar and Wolfgang Lehner},
 title = {Column Scan Optimization by Increasing Intra-Instruction Parallelism},
 booktitle = {Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA) },
 month = {July},
 year = {2018},
 
 }DownloadsDATA_2018_47_CR (1) [PDF] Permalink
- 41. Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers", Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018.        [Bibtex & Downloads]
                SMApproxlib: library of FPGA-based approximate multipliers×ReferenceSalim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers", Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018. Bibtex@inproceedings{ullah2018smapproxlib,
 title={SMApproxlib: library of FPGA-based approximate multipliers},
 author={Ullah, Salim and Murthy, Sanjeev Sripadraj and Kumar, Akash},
 booktitle={Proceedings of the 55th Annual Design Automation Conference},
 pages={157},
 year={2018},
 month={June},
 organization={ACM}
 }DownloadsPID5307267 [PDF] Permalink
- 40. Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators", Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018.        [Bibtex & Downloads]
                Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators×ReferenceSalim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators", Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018. Bibtex@inproceedings{ullah2018area,
 title={Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators},
 author={Ullah, Salim and Rehman, Semeen and Prabakaran, Bharath Srinivas and Kriebel, Florian and Hanif, Muhammad Abdullah and Shafique, Muhammad and Kumar, Akash},
 booktitle={Proceedings of the 55th Annual Design Automation Conference},
 pages={159},
 year={2018},
 month={June},
 organization={ACM}
 }DownloadsPID5307263 [PDF] Permalink
- 39. Sadia Moriam, Elke Franz, Paul Walther, Akash Kumar, Thorsten Strufe, Gerhard Fettweis, "Protecting Communication in Many-Core Systems against Active Attackers", Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp. 45–50, May 2018.        [Bibtex & Downloads]
                Protecting Communication in Many-Core Systems against Active Attackers×ReferenceSadia Moriam, Elke Franz, Paul Walther, Akash Kumar, Thorsten Strufe, Gerhard Fettweis, "Protecting Communication in Many-Core Systems against Active Attackers", Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp. 45–50, May 2018. Bibtex@inproceedings{moriam2018protecting,
 title={Protecting Communication in Many-Core Systems against Active Attackers},
 author={Moriam, Sadia and Franz, Elke and Walther, Paul and Kumar, Akash and Strufe, Thorsten and Fettweis, Gerhard},
 booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI},
 pages={45--50},
 year={2018},
 Month={May},
 organization={ACM}
 }DownloadsNo Downloads available for this publication Related PathsPermalink
- 38. Anup Das, Akash Kumar, "Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware", Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp. 419–422, May 2018.        [Bibtex & Downloads]
                Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware×ReferenceAnup Das, Akash Kumar, "Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware", Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp. 419–422, May 2018. Bibtex@inproceedings{das2018dataflow,
 title={Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware},
 author={Das, Anup and Kumar, Akash},
 booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI},
 pages={419--422},
 year={2018},
 month={May},
 organization={ACM}
 }DownloadsNo Downloads available for this publication Related PathsPermalink
- 37. Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar, YC Tay, "A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems", In Proceeding: 2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC), pp. 116–123, May 2018.        [Bibtex & Downloads]
                A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems×ReferenceMohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar, YC Tay, "A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems", In Proceeding: 2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC), pp. 116–123, May 2018. Bibtex@inproceedings{haque2018self,
 title={A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems},
 author={Haque, Mohammad Shihabul and Vasudevan, Sriram and Nihar, Alamuri Sriram and Easwaran, Arvind and Kumar, Akash and Tay, YC},
 booktitle={2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)},
 pages={116--123},
 year={2018},
 month={May},
 organization={IEEE}
 }DownloadsNo Downloads available for this publication Permalink
- 36. Bjorn Gottschall, Thomas PreuBer, Akash Kumar, "Reloc—An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles", In Proceeding: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 211–211, April 2018.        [Bibtex & Downloads]
                Reloc—An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles×ReferenceBjorn Gottschall, Thomas PreuBer, Akash Kumar, "Reloc—An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles", In Proceeding: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 211–211, April 2018. Bibtex@inproceedings{gottschall2018reloc,
 title={Reloc—An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles},
 author={Gottschall, Bjorn and PreuBer, Thomas and Kumar, Akash},
 booktitle={2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
 pages={211--211},
 year={2018},
 month={April},
 organization={IEEE}
 }DownloadsNo Downloads available for this publication Permalink
- 35. B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi]        [Bibtex & Downloads]
                DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems×ReferenceB. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi] Bibtex@INPROCEEDINGS{8342140,
 author={B. S. Prabakaran and S. Rehman and M. A. Hanif and S. Ullah and G. Mazaheri and A. Kumar and M. Shafique},
 booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
 title={DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems},
 year={2018},
 volume={},
 number={},
 pages={917-920},
 keywords={adders;field programmable gate arrays;logic design;public domain software;DeMAS;FPGA community;RTL;approximate adders;area gain;behavioral model;generic design methodology;latency gain;multibit adder architectures;power-delay product gain;Adders;Approximate computing;Delays;Design methodology;Field programmable gate arrays;Hardware;Table lookup;Adders;Approximate Computing;Area;CAD;Design Flow;Efficiency;FPGA;LUTs;Optimization;Performance;Power},
 doi={10.23919/DATE.2018.8342140},
 ISSN={},
 month={March},}DownloadsDeMAS_DATE_2018 [PDF] Related PathsPermalink
- 34. Shubham Rai, Michael Raitza, Akash Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]        [Bibtex & Downloads]
                Technology mapping flow for emerging reconfigurable silicon nanowire transistors×ReferenceShubham Rai, Michael Raitza, Akash Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] Bibtex@inproceedings{Rai_2018,
 doi = {10.23919/date.2018.8342110},
 url = {https://doi.org/10.23919%2Fdate.2018.8342110},
 year = 2018,
 month = {mar},
 publisher = ,
 author = {Shubham Rai and Michael Raitza and Akash Kumar},
 title = {Technology mapping flow for emerging reconfigurable silicon nanowire transistors},
 booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
 }DownloadsTechnology_Mapping_DATE_2018 [PDF] Related PathsPermalink
- 33. Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]        [Bibtex & Downloads]
                A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs×ReferenceShubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] Bibtex@inproceedings{Rai_2018,
 doi = {10.23919/date.2018.8342080},
 url = {https://doi.org/10.23919%2Fdate.2018.8342080},
 year = 2018,
 month = {mar},
 publisher = ,
 author = {Shubham Rai and Ansh Rupani and Dennis Walter and Michael Raitza and Andre Heinzig and Tim Baldauf and Jens Trommer and Christian Mayr and Walter M. Weber and Akash Kumar},
 title = {A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable {FETs}},
 booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
 }DownloadsPhysical_Synthesis_DATE_2018 [PDF] Related PathsPermalink
- 32. Chin Hau Hoo, Akash Kumar, "ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling", Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 67–76, 2018.        [Bibtex & Downloads]
                ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling×ReferenceChin Hau Hoo, Akash Kumar, "ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling", Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 67–76, 2018. Bibtex@inproceedings{hoo2018paradro,
 title={ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling},
 author={Hoo, Chin Hau and Kumar, Akash},
 booktitle={Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
 pages={67--76},
 year={2018},
 organization={ACM}
 }DownloadsParaDRo_FPGA_18 [PDF] Related PathsPermalink
- 31. Hermann Härtig, Nils Asmussen, Jeronimo Castrillon, Adam Lackorzynski, Michael Roitzsch, Carsten Weinhold, Akash Kumar, "Extremely Heterogeneous Systems – Not Just For Niches", In Proceeding: Extreme Heterogeneity Workshop, Feb 2018.        [Bibtex & Downloads]
                Extremely Heterogeneous Systems – Not Just For Niches×ReferenceHermann Härtig, Nils Asmussen, Jeronimo Castrillon, Adam Lackorzynski, Michael Roitzsch, Carsten Weinhold, Akash Kumar, "Extremely Heterogeneous Systems – Not Just For Niches", In Proceeding: Extreme Heterogeneity Workshop, Feb 2018. Bibtex@InProceedings{haertig_ehw18,
 author = {Hermann H{\"a}rtig and Nils Asmussen and Jeronimo Castrillon and Adam Lackorzynski and Michael Roitzsch and Carsten Weinhold and Akash Kumar},
 title = {Extremely Heterogeneous Systems -- Not Just For Niches},
 booktitle = {Extreme Heterogeneity Workshop},
 year = {2018},
 month = feb,
 note = {(Workshop took place over remote conferencing)},
 location = {Gaithersburg, MD, USA}
 }Downloads1802_Haertig_EHW [PDF] Related PathsPermalink
- 30. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems", In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018.        [Bibtex & Downloads]
                CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems×ReferenceSiva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems", In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018. Bibtex@INPROCEEDINGS{VLSID2018-siva,
 author={Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
 booktitle={2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)},
 title={CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems },
 year={2018},
 volume={},
 number={},
 pages={1-6},
 keywords={Cross-layer Resilience, Real-time systems, FaultTolerance },
 doi={},
 ISSN={},
 month={Jan},}DownloadsVLSID-2018-siva [PDF] Related PathsPermalink
- 29. Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018.        [Bibtex & Downloads]
                Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems×ReferenceSiva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018. Bibtex@INPROCEEDINGS{dprLifeASPDAC,
 author={Siva Satyendra Sahoo and Tuan Duy Anh Nguyen and B. Veeravalli and Akash Kumar},
 booktitle={2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)},
 title={Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems },
 year={2018},
 volume={},
 number={},
 pages={1-6},
 keywords={Reconfigurable Computing, Dynamic Partial Reconfiguration, Integer Linear Programming, Network-on-Chip, FPGA Floorplanning},
 month={Jan},}DownloadsASPDAC-2018-siva [PDF] Related PathsPermalink
- 28. Anup Kumar Das, Akash Kumar, Bharadwaj Veeravalli, Francky Catthoor, "Reliable and Energy Efficient Streaming Multiprocessor Systems", Springer, 2018.        [Bibtex & Downloads]
                Reliable and Energy Efficient Streaming Multiprocessor Systems×ReferenceAnup Kumar Das, Akash Kumar, Bharadwaj Veeravalli, Francky Catthoor, "Reliable and Energy Efficient Streaming Multiprocessor Systems", Springer, 2018. Bibtex@book{das2018reliable,
 title={Reliable and Energy Efficient Streaming Multiprocessor Systems},
 author={Das, Anup Kumar and Kumar, Akash and Veeravalli, Bharadwaj and Catthoor, Francky},
 year={2018},
 publisher={Springer}
 }DownloadsNo Downloads available for this publication Permalink
- 2017
- 27. Ang Li, Shuaiwen Leon Song, Weifeng Liu, Xu Liu, Akash Kumar, Henk Corporaal, "Locality-Aware CTA Clustering For Modern GPUs", In Proceeding: Architectural Support for Programming Languages and Operating Systems (ASPLOS '17), April 2017.        [Bibtex & Downloads]
                Locality-Aware CTA Clustering For Modern GPUs×ReferenceAng Li, Shuaiwen Leon Song, Weifeng Liu, Xu Liu, Akash Kumar, Henk Corporaal, "Locality-Aware CTA Clustering For Modern GPUs", In Proceeding: Architectural Support for Programming Languages and Operating Systems (ASPLOS '17), April 2017. Bibtex@InProceedings{ang2017asplos,
 author = {Ang Li and Shuaiwen Leon Song and Weifeng Liu and Xu Liu and Akash Kumar and Henk Corporaal},
 title = ,
 booktitle = {Architectural Support for Programming Languages and Operating Systems (ASPLOS '17)},
 year = {2017},
 month = {April}
 }Downloadsasplos_2017_final [PDF] Permalink
- 26. Chin Hau Hoo, Akash Kumar, "ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding", In Proceeding: Field-Programmable Custom Computing Machines (FCCM), April 2017.        [Bibtex & Downloads]
                ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding×ReferenceChin Hau Hoo, Akash Kumar, "ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding", In Proceeding: Field-Programmable Custom Computing Machines (FCCM), April 2017. Bibtex@InProceedings{fccm2017chinhau,
 author = {Chin Hau Hoo and Akash Kumar},
 title = {ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding},
 booktitle = {Field-Programmable Custom Computing Machines (FCCM)},
 year = {2017},
 month = {April}
 }Downloadsfccm-2017 [PDF] Permalink
- 25. Martin Brüstel, Akash Kumar, "Accounting for Systematic Errors in Approximate Computing", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.        [Bibtex & Downloads]
                Accounting for Systematic Errors in Approximate Computing×ReferenceMartin Brüstel, Akash Kumar, "Accounting for Systematic Errors in Approximate Computing", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. Bibtex@InProceedings{martin2017date,
 author = {Br\"ustel, Martin and Kumar, Akash},
 title = ,
 booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
 year = {2017},
 month = {March},
 organization = {IEEE},
 }Downloadsdate-2017-martin [PDF] Related PathsPermalink
- 24. Walaa El-Harouni, Semeen Rehman, Bharath Srinivas Prabakaran, Akash Kumar, Rehan Hafiz, Muhammad Shafique, "Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. (Best paper nominee)        [Bibtex & Downloads]
                Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding×ReferenceWalaa El-Harouni, Semeen Rehman, Bharath Srinivas Prabakaran, Akash Kumar, Rehan Hafiz, Muhammad Shafique, "Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. (Best paper nominee) Bibtex@InProceedings{semeen2017date,
 author = {Walaa El-Harouni and Semeen Rehman and Bharath Srinivas Prabakaran and Akash Kumar and Rehan Hafiz and Muhammad Shafique},
 title = {Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding},
 booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
 month = {March},
 year = {2017},
 organization = {IEEE},
 
 }DownloadsDATE_2017_788_OutputPaper [PDF] Related PathsPermalink
- 23. Arun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Soft Error-Aware Architectural Exploration for Designing Reliability Adaptive Cache Hierarchies in Multi-Cores", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.        [Bibtex & Downloads]
                Soft Error-Aware Architectural Exploration for Designing Reliability Adaptive Cache Hierarchies in Multi-Cores×ReferenceArun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Soft Error-Aware Architectural Exploration for Designing Reliability Adaptive Cache Hierarchies in Multi-Cores", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. Bibtex@InProceedings{semeen2017date2,
 author = {Arun Subramaniyan and Semeen Rehman and Muhammad Shafique and Akash Kumar and J\"org Henkel},
 title = ,
 booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
 year = {2017},
 month = {March},
 organization = {IEEE}
 }DownloadsDATE_2017_597_OutputPaper [PDF] Related PathsPermalink
- 22. Michael Raitza, Jens Trommer, Akash Kumar, Marcus Völp, Dennis Walter, Walter Weber, Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.        [Bibtex & Downloads]
                Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits×ReferenceMichael Raitza, Jens Trommer, Akash Kumar, Marcus Völp, Dennis Walter, Walter Weber, Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. Bibtex@InProceedings{raitza2017date,
 author = {Michael Raitza and Jens Trommer and Akash Kumar and Marcus Völp and Dennis Walter and Walter Weber and Thomas Mikolajick},
 title = {Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits},
 booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
 year = {2017},
 month = {March},
 organization = {IEEE}
 }Downloadsdate-2017-michael [PDF] Related PathsPermalink
- 21. Rui Santos, Shyamsundar Venkataraman, Akash Kumar, "Scrubbing Mechanism for Heterogeneous  Applications in Reconfigurable Devices", In ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017.        [Bibtex & Downloads]
                Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices×ReferenceRui Santos, Shyamsundar Venkataraman, Akash Kumar, "Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices", In ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017. Bibtex@article{rui-todaes-2017,
 title = {Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices},
 journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
 year = {2017},
 author = {Rui Santos and Shyamsundar Venkataraman and Akash Kumar}
 }Downloadstodaes-2017-scrubbing [PDF] Related PathsPermalink
- 2016
- 20. Semeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Architectural-Space Exploration of Approximate Multipliers", Proceedings of the International Conference on Computer-Aided Design (ICCAD), Nov 2016.        [Bibtex & Downloads]
                Architectural-Space Exploration of Approximate Multipliers×ReferenceSemeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Architectural-Space Exploration of Approximate Multipliers", Proceedings of the International Conference on Computer-Aided Design (ICCAD), Nov 2016. Bibtex@InProceedings{semeen2016iccad,
 Title= ,
 Author= {Semeen Rehman and Walaa El-Harouni and Muhammad Shafique and Akash Kumar and J{\"{o}}rg Henkel},
 Booktitle= {Proceedings of the International Conference on Computer-Aided Design (ICCAD)},
 month={nov},
 dates={7-10},
 Year= {2016}
 }DownloadsICCAD_2017_ApproxMult [PDF] Related PathsPermalink
- 19. Nam Khanh Pham, Akash Kumar, Khin Mi Mi Aung, "Automatic framework to generate reconfigurable accelerators for option pricing applications", In Proceeding: International Conference on Reconfigurable Computing and FPGAs (ReConFig), Nov 2016.        [Bibtex & Downloads]
                Automatic framework to generate reconfigurable accelerators for option pricing applications×ReferenceNam Khanh Pham, Akash Kumar, Khin Mi Mi Aung, "Automatic framework to generate reconfigurable accelerators for option pricing applications", In Proceeding: International Conference on Reconfigurable Computing and FPGAs (ReConFig), Nov 2016. Bibtex@InProceedings{Khanh-Reconfig-2016,
 title = {Automatic framework to generate reconfigurable accelerators for option pricing applications},
 Booktitle = {International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
 year = {2016},
 month={Nov},
 author = {Nam Khanh Pham and Akash Kumar and Khin Mi Mi Aung}
 }DownloadsReConFig_2016 [PDF] Related PathsPermalink
- 18. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems", In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016.        [Bibtex & Downloads]
                Cross-layer fault-tolerant design of real-time systems×ReferenceSiva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems", In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016. Bibtex@INPROCEEDINGS{sssahooDFT16,
 author={Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
 booktitle={International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)},
 title={Cross-layer fault-tolerant design of real-time systems},
 year={2016},
 pages={1--6},
 month={Sept}}DownloadsDFT_cam_ready_Certified [PDF] Related PathsPermalink
- 17. Amit Kumar Singh, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, no. 99, pp. 1-14, Aug 2016. [doi]        [Bibtex & Downloads]
                Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors×ReferenceAmit Kumar Singh, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, no. 99, pp. 1-14, Aug 2016. [doi] Bibtex@ARTICLE{amit2016tvlsi,
 author={Amit Kumar Singh and Muhammad Shafique and Akash Kumar and J{\"{o}}rg Henkel},
 journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
 title={Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors},
 year={2016},
 volume={PP},
 number={99},
 pages={1-14},
 keywords={Acceleration;Correlation;Multicore processing;Prediction algorithms;Through-silicon vias;Throughput;3-D multicore;3-D video;design-time analysis;interconnect energy;synchronous dataflow;thermal-aware mapping;throughput.},
 doi={10.1109/TVLSI.2016.2517025},
 url={http://dx.doi.org/10.1109/TVLSI.2016.2517025},
 ISSN={1063-8210},
 month={aug},
 }Downloadstvlsi-2016-amit [PDF] Related PathsPermalink
- 16. Tuan D. A. Nguyen, Akash Kumar, "XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1-11, Aug 2016.        [Bibtex & Downloads]
                XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip×ReferenceTuan D. A. Nguyen, Akash Kumar, "XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1-11, Aug 2016. Bibtex@INPROCEEDINGS{xnocfpl2016,
 author={Tuan D. A. Nguyen and Akash Kumar},
 booktitle={International Conference on Field Programmable Logic and Applications (FPL)},
 title={XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip},
 year={2016},
 pages={1-11},
 month={Aug}}Downloadsfpl_2016_xnoc [PDF] Related PathsPermalink
- 15. Chin Hau Hoo, Yajun Ha, Akash Kumar, "ParaFRo: A Hybrid Parallel FPGA Router using Fine Grained Synchronization and Partitioning", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1–11, Aug 2016.        [Bibtex & Downloads]
                ParaFRo: A Hybrid Parallel FPGA Router using Fine Grained Synchronization and Partitioning×ReferenceChin Hau Hoo, Yajun Ha, Akash Kumar, "ParaFRo: A Hybrid Parallel FPGA Router using Fine Grained Synchronization and Partitioning", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1–11, Aug 2016. Bibtex@inproceedings{hoo2016parafro,
 title={ParaFRo: A Hybrid Parallel FPGA Router using Fine Grained Synchronization and Partitioning},
 author={Hoo, Chin Hau and Ha, Yajun and Kumar, Akash},
 booktitle={International Conference on Field Programmable Logic and Applications (FPL)},
 pages={1–11},
 month={Aug},
 year={2016},
 organization={IEEE}
 }Downloadsakumar_fpl2016_ChinHau [PDF] Permalink
- 14. Ang Li, Shuaiwen Leon Song, Mark Wijtvliet, Akash Kumar, Henk Corporaal, "SFU-Driven Transparent Approximation Acceleration on GPUs", Proceedings of the 2016 International Conference on Supercomputing, pp. 15, Jun 2016.        [Bibtex & Downloads]
                SFU-Driven Transparent Approximation Acceleration on GPUs×ReferenceAng Li, Shuaiwen Leon Song, Mark Wijtvliet, Akash Kumar, Henk Corporaal, "SFU-Driven Transparent Approximation Acceleration on GPUs", Proceedings of the 2016 International Conference on Supercomputing, pp. 15, Jun 2016. Bibtex@inproceedings{li2016sfu,
 title={SFU-Driven Transparent Approximation Acceleration on GPUs},
 author={Li, Ang and Song, Shuaiwen Leon and Wijtvliet, Mark and Kumar, Akash and Corporaal, Henk},
 booktitle={Proceedings of the 2016 International Conference on Supercomputing},
 pages={15},
 year={2016},
 month={jun},
 organization={ACM}
 }DownloadsICS-a15-li_camera-ready [PDF] Related PathsPermalink
- 13. Ang Li, Leon Shuaiwen Song, Eric Brugel, Akash Kumar, Daniel Chavarria, Henk Corporaal, "X: A Comprehensive Analytic Model for Parallel Machines", In Proceeding: 30th International Parallel and Distributed Processing Symposium (IPDPS), May 2016.        [Bibtex & Downloads]
                X: A Comprehensive Analytic Model for Parallel Machines×ReferenceAng Li, Leon Shuaiwen Song, Eric Brugel, Akash Kumar, Daniel Chavarria, Henk Corporaal, "X: A Comprehensive Analytic Model for Parallel Machines", In Proceeding: 30th International Parallel and Distributed Processing Symposium (IPDPS), May 2016. Bibtex@inproceedings{li2016x,
 title={X: A Comprehensive Analytic Model for Parallel Machines},
 author={Li, Ang and Song, Leon Shuaiwen and Brugel, Eric and Kumar, Akash and Chavarria, Daniel and Corporaal, Henk},
 booktitle={30th International Parallel and Distributed Processing Symposium (IPDPS)},
 year={2016},
 month={may},
 organization={IEEE}
 }DownloadsIPDPS x-model [PDF] Related PathsPermalink
- 12. Pham Nam Khanh, Akash Kumar, Khin Mi Mi Aung, "Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms", Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES, Sankt Goar, Germany, May 23-25, 2016, pp. 127–134, May 2016. (Awarded with Best presentation award of SCOPES 2016) [doi]        [Bibtex & Downloads]
                Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms×ReferencePham Nam Khanh, Akash Kumar, Khin Mi Mi Aung, "Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms", Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES, Sankt Goar, Germany, May 23-25, 2016, pp. 127–134, May 2016. (Awarded with Best presentation award of SCOPES 2016) [doi] Bibtex@inproceedings{DBLP:conf/scopes/KhanhKA16,
 author={Khanh, Pham Nam and Kumar, Akash and Aung, Khin Mi Mi},
 title={Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms},
 booktitle={Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, {SCOPES}, Sankt Goar, Germany, May 23-25, 2016},
 pages={127--134},
 year={2016},
 month={May},
 crossref={DBLP:conf/scopes/2016},
 url={http://doi.acm.org/10.1145/2906363.2906380},
 doi={10.1145/2906363.2906380},
 
 }Downloadsscopes_2016_camera_ready [PDF] Related PathsPermalink
- 11. Ang Li, Leon Shuaiwen Song, Akash Kumar, Eddy Z. Zhang, Daniel Chavarria Gerardo, Henk Corporaal, "Critical Points Based Register-Concurrency Autotuning for GPUs", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2016.        [Bibtex & Downloads]
                Critical Points Based Register-Concurrency Autotuning for GPUs×ReferenceAng Li, Leon Shuaiwen Song, Akash Kumar, Eddy Z. Zhang, Daniel Chavarria Gerardo, Henk Corporaal, "Critical Points Based Register-Concurrency Autotuning for GPUs", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2016. Bibtex@inproceedings{li2016date,
 title={Critical Points Based Register-Concurrency Autotuning for GPUs},
 author={Li, Ang and Song, Leon Shuaiwen and Kumar, Akash and Zhang, Eddy Z. and Chavarria Gerardo, Daniel and Corporaal, Henk},
 booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE)},
 year={2016},
 month={march},
 organization={IEEE}
 }DownloadsDATE-16-camera-ready [PDF] Related PathsPermalink
- 10. Shyamsundar Venkataraman, Rui Santos, Akash Kumar, "A Flexible Inexact TMR Technique for SRAM-based FPGAs", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2016.        [Bibtex & Downloads]
                A Flexible Inexact TMR Technique for SRAM-based FPGAs×ReferenceShyamsundar Venkataraman, Rui Santos, Akash Kumar, "A Flexible Inexact TMR Technique for SRAM-based FPGAs", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2016. Bibtex@inproceedings{rui2016date,
 title={A Flexible Inexact TMR Technique for SRAM-based FPGAs},
 author={Venkataraman, Shyamsundar and Santos, Rui and Kumar, Akash},
 booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE)},
 year={2016},
 month={march},
 organization={IEEE}
 }DownloadsDATE 2016 Camera ready [PDF] Related PathsPermalink
- 9. Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016.        [Bibtex & Downloads]
                Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults×ReferenceSiva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016. Bibtex@inproceedings{siva2016date,
 title={Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults},
 author={Siva Satyendra Sahoo and Akash Kumar and Bharadwaj Veeravalli},
 booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE)},
 year={2016},
 month={mar},
 organization={IEEE}
 }Downloadsdate-2016-385-camera ready [PDF] Related PathsPermalink
- 8. Tuan D. A. Nguyen, Akash Kumar, "PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems", In Proceeding: The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb 2016.        [Bibtex & Downloads]
                PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems×ReferenceTuan D. A. Nguyen, Akash Kumar, "PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems", In Proceeding: The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb 2016. Bibtex@inproceedings{tuan2016fpga,
 title={PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems},
 author={Tuan D. A. Nguyen and Akash Kumar},
 booktitle={The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)},
 year={2016},
 month={Feb},
 organization={IEEE}
 }Downloadsfp029-nguyenA [PDF] Related PathsPermalink
- 7. Amit Kumar Singh, Mohammad Shafique, Akash Kumar, Joerg Henkel, "Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 1, pp. 72-85, Jan 2016. [doi]        [Bibtex & Downloads]
                Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs×ReferenceAmit Kumar Singh, Mohammad Shafique, Akash Kumar, Joerg Henkel, "Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 1, pp. 72-85, Jan 2016. [doi] Bibtex@article{singh2016resource,
 author={Amit Kumar Singh and Mohammad Shafique and Akash Kumar and Joerg Henkel},
 journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
 title={Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs},
 year={2016},
 volume={35},
 number={1},
 pages={72-85},
 doi={10.1109/TCAD.2015.2446938},
 ISSN={0278-0070},
 month={Jan},}DownloadsTCAD-2016-RunTimeTraceMatch [PDF] Related PathsPermalink
- 6. Pham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung, "Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures", In Microprocessors and Microsystems, 2016.        [Bibtex & Downloads]
                Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures×ReferencePham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung, "Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures", In Microprocessors and Microsystems, 2016. Bibtex@article{Khanh-Micpro-2016,
 title = {Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures},
 journal = {Microprocessors and Microsystems },
 year = {2016},
 author = {Pham Nam Khanh and Amit Kumar Singh and Akash Kumar and Khin Mi Mi Aung}
 }DownloadsMICPRO-2016-Khanh [PDF] Related PathsPermalink
- 2015
- 5. Ang Li, Gert-Jan van den Braak, Akash Kumar, Henk Corporaal, "Adaptive and transparent cache bypassing for GPUs", Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 17, Nov 2015.        [Bibtex & Downloads]
                Adaptive and transparent cache bypassing for GPUs×ReferenceAng Li, Gert-Jan van den Braak, Akash Kumar, Henk Corporaal, "Adaptive and transparent cache bypassing for GPUs", Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 17, Nov 2015. Bibtex@inproceedings{li2015adaptive,
 title={Adaptive and transparent cache bypassing for GPUs},
 author={Li, Ang and van den Braak, Gert-Jan and Kumar, Akash and Corporaal, Henk},
 booktitle={Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis},
 pages={17},
 year={2015},
 month={nov},
 organization={ACM}
 }DownloadsSC-2015-camera-ready-a17-li [PDF] Related PathsPermalink
- 4. R. Santos, S. Venkataraman, Akash Kumar, "Generic Scrubbing-based Architecture for Custom Error Correction Algorithms", In Proceeding: Rapid System Prototyping (RSP), 2015 26th IEEE International Symposium on, Oct 2015.        [Bibtex & Downloads]
                Generic Scrubbing-based Architecture for Custom Error Correction Algorithms×ReferenceR. Santos, S. Venkataraman, Akash Kumar, "Generic Scrubbing-based Architecture for Custom Error Correction Algorithms", In Proceeding: Rapid System Prototyping (RSP), 2015 26th IEEE International Symposium on, Oct 2015. Bibtex@INPROCEEDINGS{Santos2015,
 author={Santos, R. and Venkataraman, S. and Kumar, Akash},
 title={Generic Scrubbing-based Architecture for Custom Error Correction Algorithms},
 booktitle={Rapid System Prototyping (RSP), 2015 26th IEEE International Symposium on},
 Organization={IEEE},
 month={oct},
 year={2015}
 }DownloadsRSP2015_final [PDF] Related PathsPermalink
- 3. Shakith Fernando, Mark Wijtvliet, Cedric Nugteren, Akash Kumar, Henk Corporaal, "(AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration", In Proceeding: 2015 Design, Automation   Test in Europe Conference   Exhibition (DATE), pp. 305-308, 2015.        [Bibtex & Downloads]
                (AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration×ReferenceShakith Fernando, Mark Wijtvliet, Cedric Nugteren, Akash Kumar, Henk Corporaal, "(AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration", In Proceeding: 2015 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 305-308, 2015. Bibtex@INPROCEEDINGS{7092403,
 author={Fernando, Shakith and Wijtvliet, Mark and Nugteren, Cedric and Kumar, Akash and Corporaal, Henk},
 booktitle={2015 Design, Automation Test in Europe Conference Exhibition (DATE)},
 title={(AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration},
 year={2015},
 volume={},
 number={},
 pages={305-308},}DownloadsNo Downloads available for this publication Permalink
- 2013
- 2. Shakith Fernando, Mark Wijtvliet, Firew Siyoum, Yifan He, Sander Stuijk, Akash Kumar, Henk Corporaal, "MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis", In Proceeding: 2013 23rd International Conference on Field programmable Logic and Applications, pp. 1-1, 2013.        [Bibtex & Downloads]
                MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis×ReferenceShakith Fernando, Mark Wijtvliet, Firew Siyoum, Yifan He, Sander Stuijk, Akash Kumar, Henk Corporaal, "MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis", In Proceeding: 2013 23rd International Conference on Field programmable Logic and Applications, pp. 1-1, 2013. Bibtex@INPROCEEDINGS{6645623,
 author={Fernando, Shakith and Wijtvliet, Mark and Siyoum, Firew and He, Yifan and Stuijk, Sander and Kumar, Akash and Corporaal, Henk},
 booktitle={2013 23rd International Conference on Field programmable Logic and Applications},
 title={MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis},
 year={2013},
 volume={},
 number={},
 pages={1-1},}DownloadsNo Downloads available for this publication Related Pathsother Permalink
- Previous Years
- 1.         [Bibtex & Downloads]
                ×ReferenceBibtex@article{FGCS_X-DINC,
 title = "X-DINC: Toward Cross-Layer Approximation for the Distributed and In-Network Acceleration of Multi-Kernel Applications",
 journal = "Future Generation Computer Systems",
 volume = "",
 pages = "1 - 2",
 year = "2025",
 month = "July",
 issn = "",
 doi = "",
 author = "Zahra Ebrahimi and Maryam Eslami and Xun Xiao and Akash Kumar",
 }DownloadsNo Downloads available for this publication Permalink
Former Publications Outside cfaed
Please note that the copyright of some articles may not be owned by me. Please comply with the respective owner's copyright in such cases.
The BibTeX entries can be found in this Akash Kumar.bib file (last updated in 2015). The list of publications is grouped in the following categories: Patents, Theses, Books and Book Chapters, Journal Papers, Conference Papers, and Reports.
- 
Pipelined Reed-Solomon DecoderInternational Application Number: PCT/IB2006/054745, filed on Dec 11, 2006. 
 Europe Patent Application Number: 05111971.7, filed on Dec 12, 2005.
- 
Method And Apparatus For Syndrome CalculationInternational Application Number: PCT/IB2006/052151, filed on June 28, 2006. 
 Europe Patent Application Number: 05105878.2, filed on June 30, 2005.
- 
Analysis, Design and Management of Multimedia Multiprocessor SystemsAkash Kumar 
 Ph.D. Thesis, submitted to Eindhoven University of Technology, The Netherlands and National University of Singapore, April 2009.
 ISBN: 978-90-386-1642-1.
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High-Throughput Reed Solomon Decoded for Ultra Wide Band (PDF)Akash Kumar 
 In: Masters Thesis Dec 2004.
 National University of Singapore and Technical University of Eindhoven.
- 
Wavelength Channel Scheduling Using Fragmentation Approach in Optical Burst Switching NetworksAkash Kumar 
 In: Bachelors Thesis 2002.
 National University of Singapore.
- 
Implementing Time-Constrained Applications on a Predictable MPSoCSander Stuijk, Akash Kumar, Roel Jordans and Henk Corporaal. 
 In M. Qadri and S Sangwine, editors, Multicore Technology: Architecture, Reconfiguration, and Modeling
 ISBN: 978-1-439880-63-0
 CRC Press, Boca Raton, Fl, USA, 2013.
 DOI: 10.1201/b15268-4
- 
Multimedia Multiprocessor Systems: Analysis, Design and ManagementAkash Kumar, Henk Corporaal, Bart Mesman and Yajun Ha 
 1st Edition., 2010, XVI, 163 pages, Hardcover.
 ISBN: 978-94-007-0083-3
 Springer, 2010.
 DOI: 10.1007/978-94-007-0083-3
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EE4214(E) Real Time Embedded SystemsAkash Kumar 
 Compiled for the course EE4214 offered in National University of Singapore from the following two books:
 1.Real Time Systems by Jane Liu, ISBN: 9780130996510.
 2.Operating Systems Principles by Lubomir Bic and Alan Shaw. ISBN: 9780131224551.
 ISBN: 978-981-06-8549-2
 Published by Pearson, 2010.
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High-Throughput and Low-Power Reed Solomon Decoded for Ultra Wide BandAkash Kumar and Sergei Sawitzki 
 In: Wim Verhaegh, Emile Aarts, and Jan Korst(Eds.): Intelligent Algorithms, Philips Research Book Series, Vol. 7, pp. 299-316, ISBN: 1-4020-4953-6.
 Springer, 2006.
 DOI: 10.1007/1-4020-4995-1_17
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Membrane systems and distributed computing (PDF)G. Ciobanu, R. Desai, A. Kumar 
 In: Gh.Paun, G.Rozenberg, A.Salomaa, C.Zandron (Eds.): Membrane Computing, Lecture Notes in Computer Science, Vol. 2597, pp. 187-202, ISSN: 0302-9743.
 Springer, 2003.
 DOI: 10.1007/3-540-36490-0_12
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Correlation ratio based volume image registration on GPUs (PDF)Ang Li, Akash Kumar, Yajun Ha, Henk Corporaal 
 In: Elsevier Microprocessors and Microsystems (Micpro). May 2015.
 Elsevier, 2015.
 DOI: 10.1016/j.micpro.2015.04.002
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Execution-Trace Driven Energy-Reliability Optimization for Multimedia MPSoCsAnup Das, Amit Kumar Singh and Akash Kumar 
 In: ACM Transactions on Reconfigurable Technology and Systems, TRETS. Vol 8, Issue 3, May 2015.
 ACM, 2015.
 DOI: 10.1145/2665071
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Nano-satellite swarm for SAR applications: design and robust schedulingChee Khiang Pang, Akash Kumar, Cher Hiang Goh, Cao Vinh Le 
 In: IEEE Transactions onAerospace and Electronic Systems, TAES. Vol 51, Issue 2, April 2015.
 IEEE, 2015.
 DOI: 10.1109/TAES.2014.140077
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Autonomous Soft-error Tolerance of FPGA Configuration Bits (PDF)Anup Das, Shyamsundar Venkataraman and Akash Kumar 
 In: ACM Transactions on Reconfigurable Technology and Systems, TRETS. Vol 8, Issue 2, April 2015.
 ACM, 2015.
 DOI: 10.1145/2629580
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Reliability and Energy-Aware Mapping and Scheduling of Multimedia Applications on Multiprocessor SystemsAnup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: IEEE Transactions on Parallel and Distributed Systems, TPDS. March 2015.
 IEEE, 2015.
 DOI: 10.1109/TPDS.2015.2412137
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A Low Active Leakage and High Reliability Phase Change Memory (PCM) based Non-Volatile FPGA Storage Element (PDF)Huang Kejie, Ha Yajun, Zhao Rong, Akash Kumar, Lian Yong 
 In: IEEE Transactions on Circuits and Systems I: Regular Papers
 IEEE, 2014.
 DOI: 10.1109/TCSI.2014.2312499
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Energy-Aware Task Mapping and Scheduling for Reliable Embedded Computing Systems (PDF)Anup Das, Akash Kumar, Bharadwaj Veeravalli 
 In: ACM Transactions on Embedded Computing Systems (TECS). Vol 13, 2014, pp. 72:1-72:27, ISSN: 1539-9087.
 ACM, 2014.
 DOI: 10.1145/2544375.2544392
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Communication and Migration Energy Aware Task Mapping for Reliable Multiprocessor Systems (PDF)Anup Das, Akash Kumar, Bharadwaj Veeravalli 
 In: Future Generations Computing Systems. Vol 30, 2014, pp. 216-228, ISSN: 0167-739X.
 Elsevier, 2014.
 DOI: 10.1016/j.future.2013.06.016
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CADSE: communication aware design space exploration for efficient run-time MPSoC management (PDF)Amit Kumar Singh, Akash Kumar, Jigang Wu, Thambipillai Srikanthan 
 In: Frontiers of Computer Science. 2013, ISSN: 2095-2228.
 Springer, 2013.
 DOI: 10.1007/s11704-013-2196-1
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Project-based Learning in Embedded Systems Education Using FPGA Platform (PDF)Akash Kumar, Shakith Fernando and Rajesh C Panicker 
 In: IEEE Transactions on Education. Vol 56, Issue 4, Nov 2013, pp. 407-415, ISSN: 0018-9359.
 IEEE, 2013.
 DOI: 10.1109/TE.2013.2246568
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Accelerating Throughput-aware Run-time Mapping for Heterogeneous MPSoCs (PDF)Amit Kumar Singh, Akash Kumar and Thambipillai Srikanthan 
 In: ACM Transactions on Design Automation of Electronic Systems. Vol 18, Issue 1, Dec 2012, pp. 1-29, ISSN:1084-4309.
 ACM, 2012.
 DOI: 10.1145/2390191.2390200
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CA-MPSoC: An Automated Design Flow for Predictable Multi-processor Architectures for Multiple Applications (PDF)Ahsan Shabbir, Akash Kumar, Sander Stuijk, Bart Mesman, Henk Corporaal. 
 In: Journal of Systems Architecture. Vol 56, Issue 7, July 2010, pp. 265-277, ISSN: 1383-7621.
 Elsevier, 2010.
 DOI: 10.1016/j.sysarc.2010.03.007
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Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms (PDF)Amit Kumar Singh, Thambipillai Srikanthan, Akash Kumar, Wu Jigang. 
 In: Journal of Systems Architecture. Vol 56, Issue 7, July 2010, pp. 242-255, ISSN: 1383-7621.
 Elsevier, 2010.
 DOI: 10.1016/j.sysarc.2010.04.007
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Iterative Probabilistic Performance Prediction for Multi-Application Multi-Processor Systems (PDF)Akash Kumar, Bart Mesman, Henk Corporaal and Yajun Ha 
 In: IEEE Transactions in Computer Aided Design. Vol 29, Issue 4, April 2010, pp. 538-551, ISSN:0278-0070.
 IEEE, 2010.
 DOI: 10.1109/TCAD.2010.2042887
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Multi-processor Systems Synthesis for Multiple Use-Cases of Multiple Applications on FPGA (PDF)Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman and Henk Corporaal 
 In: ACM Transactions on Design Automation of Electronic Systems. Vol 13, Issue 3, July 2008, pp. 1-27, ISSN:1084-4309.
 ACM, 2008.
 DOI: 10.1145/1367045.1367049
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Analyzing Composability of Applications on MPSoC Platforms (PDF)Akash Kumar, Bart Mesman, Bart Theelen, Henk Corporaal and Yajun Ha 
 In: Journal of Systems Architecture. Vol 54, Issue 3-4, March-April 2008, pp. 369-383. ISSN: 1383-7621.
 Elsevier B.V., 2008.
 DOI: 10.1016/j.sysarc.2007.10.002
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Efficient techniques for improved QoS performance in WDM optical burst switched networks (PDF)G. Mohan, K. Akash and M. Ashish 
 In: Computer Communications, Vol. 28, Issue 7, 2 May 2005, pp. 754-764. ISSN: 0140-3664.
 Elsevier B.V., 2005.
 DOI: 10.1016/j.comcom.2004.10.007
2015
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ParaLaR: A Parallel FPGA Router Based on Lagrangian RelaxationHoo Chin Hau, Akash Kumar and Yajun Ha 
 In: Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2-4 Sep 2015
 London, UK. IEEE.
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An Automated Technique to Generate Relocatable Partial Bitstreams for Xilinx FPGAsRoel Oomen, Tuan Nguyen, Akash Kumar and Henk Corporaal 
 In: Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2-4 Sep 2015
 London, UK. IEEE.
- 
Transit: A Visual Analytical Model for Multithreaded Machine (PDF)Ang Li, Akash Kumar, Y.C. Tay and Henk Corporaal 
 In: Proceedings of International Symposium on High Performance Distributed Computing (HPDC), 15-19 June 2015
 Portland, USA. IEEE.
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Fine-Grained Synchronizations and Dataflow Programming on GPUs (PDF)Ang Li, Gert-Jan Van Den Braak, Akash Kumar and Henk Corporaal 
 In: Proceedings of International Conference on Supercomputing (ICS), 8-11 June 2015
 Newport Beach, USA. IEEE.
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Dynamically Adaptive Scrubbing Mechanism for Improved Reliability in Reconfigurable Embedded Systems (PDF)Rui Santos, Shyamsundar Venkatraman, Akash Kumar 
 In: Proceedings of Design Automation Conference (DAC), 7-11 June 2015
 San Francisco, USA. IEEE.
- 
Workload Uncertainty Characterization and Adaptive Frequency Scaling for Energy Minimization of Embedded Systems (PDF)Anup Das, Akash Kumar, Bharadwaj Veeravalli, Rishad Shafik, Geoff Merrett and Bashir Al-Hashimi 
 In: Proceedings of Design Automation and Test in Europe (DATE), 9-13 Mar 2015
 Grenoble, France. IEEE.
 Best Paper Candidate
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Designing Inexact Systems Efficiently Using Elimination Heuristics (PDF)Shyamsundar Venkatraman, Akash Kumar, Jeremy Schlachter, Christian Enz 
 In: Proceedings of Design Automation and Test in Europe (DATE), 9-13 Mar 2015
 Grenoble, France. IEEE.
- 
Exploiting Loop-Array Dependencies to Accelerate the Design Space Exploration with High Level Synthesis (PDF)Nam Khanh Pham, Amit Kumar Singh, Akash Kumar and Mi Mi Aung Khin 
 In: Proceedings of Design Automation and Test in Europe (DATE), 9-13 Mar 2015
 Grenoble, France. IEEE.
- 
Dynamic Reconfigurable Puncturing for Secure Wireless Communication (PDF)Liang Tang, Jude Angelo Ambrose, Akash Kumar and Sri Parameswaran 
 In: Proceedings of Design Automation and Test in Europe (DATE), 9-13 Mar 2015
 Grenoble, France. IEEE.
- 
(AS)^2: Accelerator Synthesis using Algorithmic Skeletons for Rapid Design Space Exploration (PDF)Shakith Fernando, Mark Wijtvliet, Cedric Nugteren, Akash Kumar and Henk Corporaal 
 In: Proceedings of Design Automation and Test in Europe (DATE), 9-13 Mar 2015
 Grenoble, France. IEEE.
- 
Accelerating Non-volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems (PDF)Mohammad Shihabul Haque, Ang Li, Qingsong Wei and Akash Kuma 
 In: Proceedings of the 20th IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 19-22 Jan 2015
 Tokyo, Japan. IEEE.
2014
- 
A Heterogeneous Platform with GPU and FPGA for Power Efficient High Performance Computing (PDF)Wu Qiang, Yajun Ha, Akash Kumar, Luo Shaobo and Mohammad Shihabul Haque 
 In: Proceedings of the IEEE International Symposium on Integrated Circuits (ISIC), 10-12 Dec 2014
 Singapore. IEEE.
- 
Design and Robust Scheduling of Nano-Satellite Swarm for Synthetic Aperture Radar Applications (PDF)Chee Khiang Pang, Akash Kumar, Cher Hiang Goh, and C. Vincent Le 
 In: Proceedings of the 2014 IEEE ICARCV, December 10-12, 2014 (invited)
 Singapore. IEEE.
- 
Lightweight Bare-metal Stateful Firewall (PDF)Yihuan Xing, Ford Long Wong, Akash Kumar 
 In: Proceedings of the IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2014), 19-21 Nov 2014
 Singapore. IEEE.
- 
A Multi-stage Thermal Management Strategy for 3D Multicores (PDF)Dipika Suresh, Amit Singh and Akash Kumar 
 In: Proceedings of the IEEE International Symposium on Rapid System Prototyping (RSP), Embedded Systems Week, 12-17 Oct 2014
 New Delhi, India. IEEE.
- 
Artificial Intelligence Based Task Mapping and Pipelined Scheduling for Checkpointing on Real Time Systems with Imperfect Fault Detection (PDF)Anup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of the IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 1-3 Oct 2014
 Amsterdam, The Netherlands. IEEE.
- 
PR-HMPSoC: a Versatile Partially Reconfigurable Heterogeneous Multiprocessor System-on-Chip for Dynamic FPGA-based Embedded Systems (PDF)Tuan D. A. Nguyen and Akash Kumar 
 In: Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2-4 Sep 2014
 Munich, Germany. IEEE.
 Best Paper Candidate
- 
Criticality-aware Scrubbing Mechanism for SRAM-based FPGAs (PDF)Rui Santos, Shyamsundar Venkataraman, Anup Das and Akash Kumar 
 In: Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2-4 Sep 2014
 Munich, Germany. IEEE.
- 
Multi-Directional Error Correction Schemes for SRAM-Based FPGAs (PDF)Shyamsundar Venkataraman, Rui Santos, Sidharth Maheshwari and Akash Kumar 
 In: Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2-4 Sep 2014
 Munich, Germany. IEEE.
- 
A Bit-Interleaved Embedded Hamming Scheme to Correct Single-Bit and Multi-Bit Upsets for SRAM-Based FPGAs (PDF)Shyamsundar Venkataraman, Rui Santos, Anup Das and Akash Kumar 
 In: Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2-4 Sep 2014
 Munich, Germany. IEEE.
- 
Leakage and Performance Aware Resource Management for 2D Dynamically Reconfigurable FPGA Architectures (PDF)Siqi Wang, Nam Khanh Pham, Amit Kumar Singh and Akash Kumar 
 In: Proceedings of International Conference on Field Programmable Logic and Applications (FPL), 2-4 Sep 2014
 Munich, Germany. IEEE.
- 
Accelerating Volume Image Registration through Correlation Ratio based Methods on GPUs (PDF)Ang Li and Akash Kumar 
 In: Proceedings of International Conference on Digital Systems Design (DSD), 27-29 Aug 2014
 Verona, Italy. IEEE.
- 
Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems (PDF)Anup Das, Rishad A. Shafik, Geoff V. Merrett, Bashir M. Al-Hashimi, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of Design Automation Conference (DAC), 1-5 Jun 2014.
 San Francisco, USA. IEEE.
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A Multi-stage Leakage Aware Resource Management technique for Reconfigurable Architectures (PDF)Nam Khanh Pham, Amit Kumar Singh, and Akash Kumar 
 In: Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), 21-23 May 2014,
 Houston, USA. IEEE.
 Best Paper Candidate
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Temperature Aware Energy-Reliability Trade-offs for Mapping of Throughput-Constrained Applications on Multimedia Multiprocessor Systems (PDF)Anup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of Design Automation and Test in Europe (DATE), 24-28 Mar 2014
 Dresden, Germany. IEEE.
- 
Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs (PDF)Anup Das, Akash Kumar and Bharadwaj Veeravalli, Cristiana Bolchini and Antonio Miele 
 In: Proceedings of Design Automation and Test in Europe (DATE), 24-28 Mar 2014
 Dresden, Germany. IEEE.
2013
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Real-time and Low Power Embedded L1-Optimization Solver Design (PDF)Zhi Ping Ang and Akash Kumar 
 In: Proceedings of the International Conference on Field-Programmable Technology, (FPT), 9-11 Dec 2013.
 Kyoto, Japan. IEEE.
- 
Run-time mapping for reliable many-cores based on energy/performance trade-offs (PDF ~338 kB)Cristiana Bolchini, Matteo Carminati, Antonio Miele, Anup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2-4 Oct 2013
 New York City, USA. IEEE.
- 
Thermal-Aware Mapping of Streaming Applications on 3D Multi-Processor Systems (PDF)Marco Cox, Amit Kumar Singh, Akash Kumar and Henk Corporaal 
 In: Proceedings of the IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), Embedded Systems Week, 29 Sep-4 Oct 2013
 Montreal, Canada. IEEE.
- 
MAMPSx: A Design Framework for Rapid Synthesis of Predictable Heterogeneous MPSoCs (PDF)Shaktih Fernando, Firew Siyoum, Yifan He, Akash Kumar and Henk Corporaal 
 In: Proceedings of the 24rth IEEE International Symposium on Rapid System Prototyping (RSP), Embedded Systems Week, 29 Sep-4 Oct 2013
 Montreal, Canada. IEEE.
- 
Aging-aware Hardware-Software Task Partitioning for Reliable Reconfigurable Multiprocessor Systems (PDF)Anup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of the International Conference on Compilers Architectures and Synthesis of Embedded Systems (CASES), Embedded Systems Week, 29 Sep-4 Oct 2013.
 Montreal, Canada. ACM/IEEE.
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RAPIDITAS: RAPId Design-space-exploration Incorporating Trace-based Analysis and Simulation (PDF)Amit Kumar Singh, Anup Das and Akash Kumar 
 In: Proceedings of international conference on digital systems design (DSD), 4-6 Sep 2013
 Santander, Spain. IEEE.
- 
Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-time Mapping for Heterogeneous MPSoCs (PDF)Nam Khanh Pham, Amit Kumar Singh, Akash Kumar and Mi Mi Aung Khin 
 In: Proceedings of international conference on digital systems design (DSD), 4-6 Sep 2013
 Santander, Spain. IEEE.
- 
Improving Autonomous Soft-error Tolerance of FPGA through LUT Configuration Bit Manipulation (PDF)Anup Das, Shyamsundar Venkataraman and Akash Kumar 
 In: Proceedings of international conference on field programmable logic and applications (FPL), 2-4 Sep 2013
 Porto, Portugal. IEEE.
- 
A Directional Coarse-Grained Power Gated FPGA Switch Box and Power Gating Aware Routing Algorithm (PDF)Chin Hau Hoo, Yajun Ha and Akash Kumar 
 In: Proceedings of international conference on field programmable logic and applications (FPL), 2-4 Sep 2013
 Porto, Portugal. IEEE.
- 
MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis (PDF kB)Shakith Fernando, Mark Wijtvliet, Firew Siyoum, Yifan He, Sander Stuijk, Akash Kumar, Henk Corporaal 
 In: Proceedings of international conference on field programmable logic and applications (FPL), 2-4 Sep 2013
 Porto, Portugal. IEEE.
- 
Enhancing VHDL Learning through a Light-weight Integrated Environment for Development and Automated Checking (PDF)Akash Kumar, Rajesh C Panicker and Ashraf Kassim 
 In: Proceedings of IEEE International Conference on Teaching, Assessment and Learning for Engineering (TALE), 26-29 Aug 2013
 Bali, Indonesia. IEEE.
- 
Energy-Aware Dynamic Reconfiguration of Communication-Centric Applications for Reliable MPSoCs (PDF)Anup Das, Amit Kumar Singh and Akash Kumar 
 In: Proceedings of 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 10-12 Jul 2013
 Darmstadt, Germany. IEEE.
- 
Mapping on Multi/Many-Core Systems: Survey of Current and Emerging Trends (PDF)Amit Singh, Muhammad Shafique, Akash Kumar, Jörg Henkel 
 In: Proceedings of Design Automation Conference (DAC), 2-6 Jun 2013
 Austin, USA. IEEE.
- 
Energy Optimization by Exploiting Execution Slacks in Streaming Applications on Multiprocessor Systems (PDF)Amit Singh, Anup Kumar Das, Akash Kumar 
 In: Proceedings of Design Automation Conference (DAC), 2-6 Jun 2013
 Austin, USA. IEEE.
- 
High Speed Video Processing Using Fine-Grained Processing on FPGA Platform (PDF)Ang Zhi Ping, Akash Kumar and Yajun Ha 
 In: 21st IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 28-30 Apr 2013
 Seattle, Washington, USA. IEEE. The extended version is also available.
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Reliability-Driven Task Mapping for Lifetime Extension of NoC-based Multiprocessor Systems (PDF)Anup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of Design Automation and Test in Europe (DATE), 18-22 Mar 2013
 Grenoble, France. IEEE.
- 
Communication and Migration Energy Aware Design Space Exploration for Multicore Systems with Intermittent Faults (PDF)Anup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of Design Automation and Test in Europe (DATE), 18-22 Mar 2013
 Grenoble, France. IEEE.
- 
TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs (PDF)Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Wu Qiang and Luo Shaobo 
 In: Proceedings of the 18th IEEE Asia and South Pacific Design Automation Conference (ASPDAC), 22-25 Jan 2013
 Yokohama, Japan. IEEE.
2012
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Energy-Aware Communication and Remapping of Tasks for Reliable Multimedia Multiprocessor Systems (PDF)Anup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems (ICPADS), 17-19 Dec 2012
 Singapore. IEEE.
- 
Fault-Aware Task Re-Mapping for Throughput Constrained Multimedia Applications on NoC-based MPSoC (PDF 621kB)Anup Das and Akash Kumar 
 In: Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping (RSP), 11-12 Oct 2012
 Tampere, Finland. IEEE.
- 
A Design Flow for Partially Reconfigurable Heterogeneous Multi-Processor Platforms (PDF 422kB)Li Jiashu, Anup Das and Akash Kumar 
 In: Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping (RSP), 11-12 Oct 2012
 Tampere, Finland. IEEE.
- 
Minimizing Power Consumption of Spatial Division based Networks-on-Chip Using Multi-Path and Frequency Reduction (PDF 685kB)Sheng Hao Wang, Anup Das, Akash Kumar and Henk Corporaal 
 In: Proceedings of the 15th Euromicro Conference on Digital Systems Design (DSD), 5-8 Sep 2012
 Izmir, Turkey. IEEE.
- 
An Area-efficient Partially Reconfigurable Crossbar Switch with Low Reconfiguration Delay (PDF 954kB)Hoo Chin Hau and Akash Kumar 
 In: Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 29-31 Aug 2012.
 Oslo, Norway. IEEE.
- 
Acceleration of Distance-to-Default with Software-Hardware Co-design (PDF 188kB)Izaan Allugundu, Pranay Puranik, Yat Piu Lo and Akash Kumar 
 In: Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 29-31 Aug 2012.
 Oslo, Norway. IEEE.
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Development of a Real-Time FPGA-Based P300 Brain Computer Interface Speller Application (PDF 98kB)Kanav Khurana, Pooja Gupta, Rajesh Panicker and Akash Kumar 
 In: Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 29-31 Aug 2012.
 Oslo, Norway. IEEE.
- 
Fault-Tolerant Network Interface for Spatial Division Multiplexing Based Network-on-Chip (PDF 870kB)Anup Das, Akash Kumar and Bharadwaj Veeravalli 
 In: Proceedings of the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 9-11 Jul 2012.
 York, United Kingdom. IEEE.
2011
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Communication-Aware Design Space Exploration for Efficient Run-Time MPSoC Management (PDF 238kB)Amit Kumar Singh, Akash Kumar, Wu Jigang and Thambipillai Srikanthan. 
 In: Proceedings of the Fourth International Symposium on Parallel Architectures, Algorithms and Programming (PAAP), 9-11 Dec 2011.
 Tianjin, China. IEEE.
 DOI: 10.1109/PAAP.2011.18
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Bringing Soccer to the Field of Real-Time Embedded Systems Education (PDF)Akash Kumar, Shakith Fernando and Manmohan Manoharan 
 In: Workshop in Embedded Systems Education (WESE), Embedded Systems Week, 9-14 Oct 2011.
 Taipei, 2011. ACM/IEEE.
 DOI: 10.1145/2077370.2077377
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A Hybrid Strategy for Mapping Multiple Throughput-constrained Applications on MPSoCs (PDF)Amit Kumar Singh, Akash Kumar and Thambipillai Srikanthan. 
 In: Proceedings of the International Conference on Compilers Architectures and Synthesis of Embedded Systems (CASES), Embedded Systems Week, 9-14 Oct 2011.
 Taipei, 2011. ACM/IEEE.
 DOI: 10.1145/2038698.2038726
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Distributed Resource Management for Concurrent Execution of Multimedia Applications on MPSoC Platforms (PDF)Ahsan Shabbir, Akash Kumar, Bart Mesman and Henk Corporaal. 
 In: Proceedings of the International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS), 18-21 Jul 2011.
 Samos, Greece, 2011. IEEE.
 DOI: 10.1109/SAMOS.2011.6045454
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A Design Space Exploration Methodology for Application Specific MPSoC Design (PDF)Amit Kumar Singh, Akash Kumar and Thambipillai Srikanthan. 
 In: Proceedings of the Annual Symposium on VLSI (ISVLSI), 4-6 Jul 2011.
 Chennai, 2011. IEEE.
 DOI: 10.1109/ISVLSI.2011.44
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An MPSoC Design Approach for Multiple Use-cases of Throughput Constrained Applications (PDF)Ahsan Shabbir, Sander Stuijk, Akash Kumar, Bart Mesman and Henk Corporaal. 
 In: Proceedings of the ACM Computing Frontiers, 3-6 May 2011.
 Ischia, Italy, 2011. ACM. -->
 DOI: 10.1145/2016604.2016628
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An Automated Flow to Map Throughput Constrained Applications to a MPSoC (PDF)An Automated Flow to Map Throughput Constrained Applications to a MPSoC (PDF) 
 Roel Jordans, Firew Siyoum, Sander Stuijk, Akash Kumar and Henk Corporaal.
 In: Workshop on Predictability and Performance in Embedded Systems, 18 March 2011.
 Grenoble, France, 2011. Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik.
 Published in: Bringing Theory to Practice: Predictability and Performance in Embedded Systems in OpenAccess Series in Informatics (OASIcs)
 Vol. 18, pp. 47-58, ISBN: 978-3-939897-28-6.
 DOI: 10.4230/OASIcs.PPES.2011.47
2010 and Earlier
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An Area-efficient Dynamically Reconfigurable Spatial Division Multiplexing Network-on-Chip with Static Throughput Guarantee (PDF)Zhiyao Joseph Yang, Akash Kumar and Yajun Ha. 
 In: Proceedings of the International Conference on Field-Programmable Technology, 8-10 Dec 2010.
 Beijing, 2010. IEEE.
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Mapping Real-life Applications on Run-time Reconfigurable NoC-based MPSoC on FPGA (PDF)Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan, and Yajun Ha. 
 In: Proceedings of the International Conference on Field-Programmable Technology, 8-10 Dec 2010.
 Beijing, 2010. IEEE.
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Run-time Mapping of Multiple Communicating Tasks on MPSoC Platforms (PDF)Amit Kumar Singh, Wu Jigang, Akash Kumar, Thambipillai Srikanthan. 
 In: Proceedings of the International Conference on Computational Science, May-June 2010.
 Amsterdam, 2010. Elsevier.
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A Predictable Communication Assist (PDF ~293 kB)Ahsan Shabbir, Sander Stuijk, Akash Kumar, Bart Theelen, Bart Mesman, Henk Corporaal. 
 In: Proceedings of the ACM Computing Frontiers, May 2010, pp. 97-98. ISBN: 978-1-4503-0044-5.
 Italy, 2010. ACM.
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Performance Evaluation of Concurrently Executing Parallel Applications on Multi-Processor Systems (PDF)Ahsan Shabbir, Akash Kumar, Bart Mesman, and Henk Corporaal. 
 In: Proceedings of the International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS 09), July 2009, pp. 100-107. ISBN: 978-1-4244-4502-8.
 Samos, Greece, 2009. IEEE.
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Enabling MPSoC Design Space Exploration on FPGAsAhsan Shabbir, Akash Kumar, Bart Mesman and Henk Corporaal 
 In: International Multi-topic Conference (IMTIC), 11-12 Apr 2008, Jamshoro, Pakistan.
 Published in: D.M.A. Hussain, A.Q.K. Rajput, B.S. Chowdhry and Q. Gee (Eds): Wireless Networks, Information Processing and Systems, Communications in Computer and Information Science Series.
 Vol. 20, pp. 412-421, ISBN: 978-3-540-89852-8.
 Springer, 2009.
 DOI: 10.1007/978-3-540-89853-5_44
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Vectorization of Reed Solomon Decoding and Mapping on the EVP (PDF)Akash Kumar and Kees van Berkel 
 Proceedings of Design Automation and Test in Europe, Mar 2008, pp. 450-455. ISBN: 978-3-9810801-3-1.
 Munich, Germany, 2008. IEEE Computer Society.
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Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA (PDF ~157 kB)Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, and Henk Corporaal 
 Proceedings of Field Programmable Logic (FPL) Conference, Aug 2007, pp. 92-97. ISBN: 1-4244-1060-6
 Amsterdam, The Netherlands, 2007. IEEE Circuit and Systems Society.
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A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices (PDF)Akash Kumar, Bart Mesman, Bart Theelen, Henk Corporaal and Yajun Ha 
 Proceedings of Design Automation Conference, Jun 2007, pp. 726-731. ISBN: 978-1-59593-627-1.
 San Diego, USA, 2007. IEEE Computer Society.
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An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems-on-Chip (PDF)Akash Kumar, Andreas Hansson, Jos Huisken and Henk Corporaal 
 Proceedings of Design Automation and Test in Europe, Apr 2007, pp. 117-122. ISBN: 978-3-9810801-2-4.
 Nice, France, 2007. IEEE Computer Society.
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Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip (PDF)Akash Kumar, Bart Mesman, Bart Theelen, Henk Corporaal and Yajun Ha 
 In: Proceedings of the 4th Workshop on Embedded Systems for Real-Time Multimedia, Oct 2006, pp. 33-38. ISBN: 0-7803-9783-5.
 Seoul, Korea, 2006. IEEE Computer Society.
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Global Analysis of Resource Arbitration for MPSoC (PDF)Akash Kumar, Bart Mesman, Henk Corporaal, Jef van Meerbergen and Yajun Ha 
 In: Proceedings of the 9th Euromicro Conference on Digital Systems Design, Aug 2006, pp. 71-78. ISBN: 0-7695-2609-8.
 Dubrovnik, Croatia, 2006. IEEE Computer Society.
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On Composability of MPSoC Applications (PDF)Akash Kumar, Bart Theelen, Bart Mesman and Henk Corporaal 
 In: Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), Jul 2006, pp. 149-152, ISBN: 90-382-0981-9
 L'Aquila, Italy, 2006.
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Reconfigurable Multi-Processor Network-on-Chip on FPGA(PDF)Akash Kumar, Ido Ovadia, Jos Huisken, Henk Corporaal, Jef van Meerbergen and Yajun Ha 
 In: Proceedings of 12th Annual Conference of the Advanced School for Computing and Imaging, Jun 2006, pp. 313-317, ISBN: 90-810-8491-7.
 Lommel, Belgium, 2006.
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High-Throughput and Low-Power Architectures for Reed Solomon Decoder (PDF)Akash Kumar and Sergei Sawitzki 
 Proceedings of the 39th Asilomar Conference on Signals, Systems, and Computers, Oct 2005, pp. 990-994. ISBN: 1-4244-0132-1.
 Pacific Grove, U.S.A., 2005. IEEE Circuit and Systems Society.
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High-Throughput and Low-Power Reed Solomon Decoded for Ultra Wide Band (PDF)Akash Kumar and Sergei Sawitzki 
 In: Proceedings of Philips Symposium on Intelligent Algorithms Dec 2004.
 Philips High Tech Campus, Eindhoven, 2004.
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Burst Scheduling Based on Time-slotting and Fragmentation in WDM Optical Burst Switched Networks (PDF)G. Mohan, M. Ashish, and K. Akash 
 In: Proceedings of IASTED International Conference on Wireless and Optical Communications WOC, July 2002, pp. 351-355.
 Banff, Canada.
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Membrane Systems and Distributed ComputingGabriel Ciobanu, Rahul Desai and Akash Kumar 
 In: Workshop on Membrane Computing, 2002
 Romania.
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Accurate Run-time Performance Prediction for Multi-Application Multi-Processor Systems. (PDF)Akash Kumar, Bart Mesman, Henk Corporaal, and Yajun Ha. 
 In: ES Report ESR-2008-07. June 16, 2008.
 Eindhoven University of Technology.
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A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. (PDF)Akash Kumar, Bart Mesman, Henk Corporaal, Bart Theelen and Yajun Ha. 
 In: ES Report ESR-2007-02. Mar 25, 2007.
 Eindhoven University of Technology.
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On Composability of MPSoC Applications (PDF)Akash Kumar, Bart Theelen, Bart Mesman and Henk Corporaal 
 In: Architecture and Compilers for Embedded Systems Oct 2006, pp. 110-113, ISBN: 90-382-1016-7.
 Edegem, Belgium, 2006.
 
		

