cfaed Publications

Technology mapping flow for emerging reconfigurable silicon nanowire transistors

Reference

S. Rai, M. Raitza, A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), vol. , no. , pp. 767-772, March 2018. [doi]

Bibtex

@INPROCEEDINGS{8342110,
author={S. Rai and M. Raitza and A. Kumar},
booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={Technology mapping flow for emerging reconfigurable silicon nanowire transistors},
year={2018},
volume={},
number={},
pages={767-772},
keywords={CMOS logic circuits;elemental semiconductors;logic design;logic gates;nanoelectronics;nanowires;reconfigurable architectures;silicon;transistor circuits;CMOS based mapping;CMOS flow;HOF;Si;SiNW based genlib;SiNW based logic design;SiNW based logic gates;SiNW transistors;XOR logic family;ambipolar transistors;area-optimized technology mapping;conventional circuit design-flow;efficient circuit designs;electrical properties;extended functionality;functional flexibility;higher order functions;modified ABC tool;open source license;reconfigurable silicon nanowire transistors;single logical output;static layout;technology mapping flow;CMOS technology;Logic circuits;Logic gates;Optimization;Silicon;Tools;Transistors},
doi={10.23919/DATE.2018.8342110},
ISSN={},
month={March},}

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Technology_Mapping_DATE_2018 [PDF]

Related Paths

Silicon Nanowire Path

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