Computer Architecture 1 (RA I)

Lecturer: Prof. Akash Kumar

Instructor: Martin Brüstel (Contact)

Description: The objective of this course is to introduce the basic principles of computing technology. The course material is very helpful in understanding the architectures of modern computer systems. It starts with an introduction of binary coding (number systems) and methods of data processing. The designs of different basic computer components will be discussed. Using the principles of Von Neumann computer, CISC and RISC architectures will be introduced. The course will also cover the memory hierarchy, communication protocols and interaction of individual components.

Configuration: 2 V / 2 Ü / 0 P

Module: INF-B-330, INF-B-330, INF-B-330, INF-B-330, INF-LE-EUI, INF-LE-MA, IST-05-PF-GS, MATH-BA-INFG  

Language of Instruction: German 

Schedule (Vorlesung): Tuesday 14:50 hrs (Room: HSZ / 0002)

Tutorials (Übung): Information is available here.

Examination Type: TBA

Lecture Material and Exercises (Vorlesung und Übung): Available here

Achtung: Für die Übung Rechnerarchitektur I gibt es zwei zusätzliche Termine, in denen bisher nich besprochene Aufgaben nachgeholt werden können:
- 06.02.2019, 09:00 (Treff Foyer APB)
- 07.02.2019, 09:20 APB 009


Additional Resources: anandtech, RISC


Embedded Hardware Systems Design

Lecturer: Prof. Akash Kumar

Instructor: Dr. Tuan Duy Anh Nguyen (Contact)

Module Number: DSE-14-E14, INF-B-510, INF-B-520, INF-BAS3, INF-BAS4, INF-BI-4, INF-BI-5, INF-E-3,

Language of Instruction: English

Motivations: Nowadays, the means of computation in datacenters are no longer homogeneous. Traditionally, only the General Purpose Processors were used to process the data. The current datacenters are moving towards heterogeneous computation where other components are integrated alongside GPPs. They are either GPGPUs (General Purpose Graphic Processing Units), dedicated hardware accelerators (like Google TPU, Tensor-Processing Unit) or a more generic reconfigurable platform for accelerators, FPGA (Field Programmable Gate Array). GPGPU proves to be very efficient in parallel processing in the big-data era with tremendous data bandwidth and processing power. However, they require hundreds of watts of power (each) to operate which significantly contribute to the plethora of problems in cooling and power management in datacenters. On the other end of the spectrum, dedicated hardware accelerators are extremely fast and power efficient for its very desired functionality. FPGAs sit in the middle of the spectrum to offer the best of both worlds: fast computation with inherently infinite parallelism, generic enough for (almost) any accelerator on the same platform with reconfigurability, and finally, energy-efficient with reasonable power consumption (40W on Microsoft datacenters). As a result, many companies have been investing in FPGA in their datacenter solutions such as Microsoft, Amazon, Baidu, Huawei, Ericsson, etc.
The aim of this module is to equip the students with the knowledge of hardware systems design. It starts with different ideas, flows, and steps involved in moving from a high-level system architecture specification models to a fully functional, optimized system on the FPGA. In order to fulfill this goal, the students need to have a different mindset in working with hardware. It’s no longer sequential, everything is parallelized. The insights into different algorithms and techniques in every step of building the hardware (turning hardware description language model to logic elements, mapping and placing them to FPGA resources, connecting those resources to realize a working system) are discussed. These are the foundations for the students to critically analyze and successfully design a hardware system on the FPGA. 

Configuration: 2 V / 0 Ü / 0 P

Pre-requisites: Basic knowledge of computer architecture and embedded systems is required. Furthermore, knowledge in hardware design, including VHDL and FPGA is an advantage.

Examination: The exam form for the award of credits corresponds to the regular exam at the first retake exam (WH1). In the case of an approved second re-examination (WH2), the examination is an oral individual examination of 30 minutes.

Credits and grades: 6 credit points. The module grade corresponds to the grade of the examination.

Schedule: Thursdays, 11.10-12.40 (Computer Science Faculty, room APB E009)

Dates: 4.4. / 11.4. / 18.4. / 25.4. / 2.5. / 9.5. / 16.5. / 23.5. / 6.6. / 27.6. / 4.7. / 11.7.

Lecture Material

Lecture 1 - Introduction (PDF)

Lecture 2 - FPGA (PDF)

Seminar Embedded Hardware Systems Design

Configuration: 0 V / 2 Ü / 0 P

Description: In this seminar, the student acquires the basic skills for doing developmental research: performing a related work search on the desired topics, deriving the solutions and plan for implementing the topic, composing a 4-page paper-like write-down and presenting it. These are fundamental skills that are required as early as doing a Bachelors Thesis or Master Thesis.

The students, in groups of 1 to 2, are free to choose a topic from a set of pre-defined ones ranging from system architecture modeling, high-level synthesis for some particular domains such as Machine Learning, Image Processing, data processing like compression, filtering, etc. They can also propose their own. Afterwards, the students have one month to review and gather related works and techniques on the topic. The next one month would be for implementation. Finally, the students work on the 4-page technical report and presentation.

Schedule: The instructors and students will agree upon the timeline for meeting during first lecture (Vorlesung). It’s preferably every two weeks to make sure that the students are going the right direction and to clarify the doubts.

Language: English.

Forschungslinie – Einführung in die Forschung

Configuration: 1DS

Lecturer: Prof. Akash Kumar

Description: Overview of modern embedded processor designs and principles with a quick introduction to today's research problems in the domain, including approximate computing and fault-tolerant computing.



Course Material:

Seminar Current Topics in Embedded Systems (Hauptseminar)




















Configuration: 0/2/0

Description: In this seminar, the student acquires the basic skills for doing research: performing a related work search, composing a 6-page paper-like write-down and presenting it. These are fundamental skills that are required as early as doing a Bachelors Thesis, Großer Beleg or Masters Thesis.

The student is free to choose a topic/paper from a set of pre-selected conference papers. The papers will be in the domain of low-power and predictable multi-processor architectures including design techniques like approximate computing and reconfigurable architectures. Afterwards, the student has one month to review and gather related work on the subject matter addressed in this paper. The write-down must present a more detailed comparison on the paper topic than is already given in the related work section. It may also refer to commonalities in other areas and should suggest new research directions that the approach in the selected paper does not cover.

Schedule: There will be a maximum capacity of 10 students to participate in the seminar. Register with an e-mail to Martin Brüstel until the 30th of April. We will follow up with a date for the presentation and the distribution of topics afterwards.

Language: English.