Teaching

Lecturer: Prof. Akash Kumar

Instructor: Steffen Märcker (steffen.maercker@tu-dresden.de)

Description: The objective of this course is to introduce the basic principles of computing technology. The course material is very helpful in understanding the architectures of modern computer systems. It starts with an introduction of binary coding (number systems) and methods of data processing. The designs of different basic computer components will be discussed. Using the principles of Von Neumann computer, CISC and RISC architectures will be introduced. The course will also cover the memory hierarchy, communication protocols and interaction of individual components.

Configuration: 2 V / 2 Ü / 0 P

Module: INF-B-330, INF-LE-EUI, INF-LE-MA, IST-05-PF-GS, MATH-BA-INFG

Registeration: OPAL

Language of Instruction: German 

Schedule (Vorlesung): Tuesday 14:50 hrs (QA Session: online, slides and video available before each date))

Tutorials (Übung): Information is available here.

Examination Type: TBA

Lecture Material and Exercises (Vorlesung und Übung): Available here

Additional Resources: anandtech, RISC, RISC-V use news

Configuration: 3 weeks each with 4 DS

Lecturer: Prof. Akash Kumar
Instructor: Salim Ullah (for practical sessions only)

Description: This course gives an introduction to different topics in computer engineering. It is taught by several professors of the institute for "Technische Informatik", including "Parallel Processing" by Prof. Nagel , "HW/SW Co-design" by Prof. Göhringer, Compiler Design by Prof. Castrillon. The part covered by Prof. Kumar includes trends and challenges in modern computing systems, with emphasis on neural network design and optimization.

Registration: OPAL
Schedule: In the winter semester 2020/2021, the lecture will be held on Tuesdays, 16:40-18:10 in room APB/E007, and Fridays, 14:50-16:20 in room APB/E006 (2nd part starting on 20.11.2020). More details available here.

Lectures: 20.11 (2:50pm), 24.11 (4:40pm), 27.11 (2:50pm), 01.12 (4:40pm), 04.12 (2:50pm), 08.12 (4:40pm)

Lecturer: Prof. Akash Kumar

Instructor: Dr.-Ing. Salim Ullah (Contact)

Module Number: DSE-14-E14, INF-B-510, INF-B-520, INF-BAS3, INF-BAS4, INF-BI-4, INF-BI-5, INF-E-3,
INF-PM-ANW, INF-PM-FOR, INF-VERT3, INF-VERT4, INF-VERT5

Language of Instruction: English

Motivations: Nowadays, the means of computation in datacenters are no longer homogeneous. Traditionally, only the General Purpose Processors were used to process the data. The current datacenters are moving towards heterogeneous computation where other components are integrated alongside GPPs. They are either GPGPUs (General Purpose Graphic Processing Units), dedicated hardware accelerators (like Google TPU, Tensor-Processing Unit) or a more generic reconfigurable platform for accelerators, FPGA (Field Programmable Gate Array). GPGPU proves to be very efficient in parallel processing in the big-data era with tremendous data bandwidth and processing power. However, they require hundreds of watts of power (each) to operate which significantly contribute to the plethora of problems in cooling and power management in datacenters. On the other end of the spectrum, dedicated hardware accelerators are extremely fast and power efficient for its very desired functionality. FPGAs sit in the middle of the spectrum to offer the best of both worlds: fast computation with inherently infinite parallelism, generic enough for (almost) any accelerator on the same platform with reconfigurability, and finally, energy-efficient with reasonable power consumption (40W on Microsoft datacenters). As a result, many companies have been investing in FPGA in their datacenter solutions such as Microsoft, Amazon, Baidu, Huawei, Ericsson, etc.
The aim of this module is to equip the students with the knowledge of hardware systems design. It starts with different ideas, flows, and steps involved in moving from a high-level system architecture specification models to a fully functional, optimized system on the FPGA. In order to fulfill this goal, the students need to have a different mindset in working with hardware. It’s no longer sequential, everything is parallelized. The insights into different algorithms and techniques in every step of building the hardware (turning hardware description language model to logic elements, mapping and placing them to FPGA resources, connecting those resources to realize a working system) are discussed. These are the foundations for the students to critically analyze and successfully design a hardware system on the FPGA. 

Configuration: 2 V / 2 Ü / 0 P

Pre-requisites: Basic knowledge of computer architecture and embedded systems is required. Furthermore, knowledge in hardware design, including VHDL and FPGA is an advantage.

Examination: There will be a written exam at the end of the semester.

Schedule: In Summer Semester

Lecture: Thursdays, 13.00-14.30, POT/13/U (Updated)

Seminar/Tutorials: Tuesdays, 14:50-16:10, ZEU 147 (Updated)

Course Registeration: Using OPAL

Please register to get regular updates

Lecture Material will be uploaded in OPAL.

Lecturer: Prof. Dr. Akash Kumar

Instructor: Dr.-Ing. Salim Ullah (Contact)

Configuration: 0 V / 0 Ü / 4 P

Module: INF-DSE-20-E-EHS-L

Description: This module is designed as a follow-up for the Embedded System Design (lecture and seminar) offered in the last semester. However, it is also suitable for other participants who did not attend the lecture. Previously, the participants learnt about the knowledge of hardware systems design. It started with different ideas, flows, and steps in moving from a high-level system architecture specification models to a fully functional, optimized system on the FPGA. The insights into different algorithms and techniques in every step of building the hardware (turning hardware description language model to logic elements, mapping, and placing them to FPGA resources, connecting those resources to realize a working system) were discussed. These are the foundations for the participants to critically analyze and successfully design a hardware system on the FPGA.

In this module, the participants will be designing the actual embedded systems on the FPGA. It is different than the Embedded System Design Seminar, where the participants are free to choose the topics of interest without having to implement on the FPGA board. The goal of this module is to have hands-on practice of developing complex embedded systems on a Xilinx Zynq FPGA. In these systems, the software running on the ARM core (in the Processing Subsystem) will interact with the hardware accelerators implemented in the Programmable Logic via the AMBA AXI bus. The participants will be instructed through a set of tutorials every week to learn what these embedded systems are comprised of, how they can be implemented starting from the most basic accelerator to the more complex ones with AMBA AXI-4 and AXI-Stream interfaces. The participants will also write their own hardware accelerators with any hardware description language that they are comfortable with. The main language for the software running on ARM is C/C++.

Schedule (Winter Semester): Please check OPAL

Registration: OPAL

Language: English

Pre-requisites: Basic knowledge of computer architecture and embedded systems is required. Furthermore, knowledge in hardware design, including VHDL and FPGA, is an advantage.

Lecturer: Prof. Dr. Akash Kumar
Module Number: INF-PM-FPA, INF-VERT1, INF-VERT4, INF-VERT5  

Schedule: Once every two weeks, will be agreed upon by all participants. The location will be BAR-III (the exact room will be informed later)
Language: English
Motivations: This module is similar to the Praktikum Embedded Hardware Systems Design. However, it is more research oriented. The participants will work on the state-of-the-art problems in order to propose novel solutions to tackle them. The participants will also need to write a research article that is compliant with the international conferences/journals.
Configuration: 0 V / 0 Ü / 4 P
Pre-requisites: Basic knowledge of computer architecture and embedded systems is required. Furthermore, knowledge in hardware design, including VHDL and FPGA is an advantage.

Regitration: OPAL

Configuration: 8P/PB

Description: In this module, the student acquires the essential skills for doing research: performing a related work search, proposing new solutions, implementing the ideas and composing a 6-page paper-like write-down and presenting it. These are fundamental skills that are required as early as doing a Bachelor Thesis, Großer Beleg or Master Thesis.
The student is free to choose a topic/paper from a set of pre-selected conference papers. The papers will be in the domain of low-power and multi-processor architectures including design techniques like approximate computing and reconfigurable architectures for machine learning, image/signal processing, etc. The student has two to three weeks to review and gather related work on the subject matter addressed in this paper. Then, the student needs to analyze the advantages as well as the disadvantages of the state-of-the-art, propose a solution to address one of those drawbacks. Afterwards, the student has to implement and evaluate the solution, either using hardware (preferably), software or simulation of the hardware. Finally, the paper report is expected to be compliant with the international conferences/journals. If the results are sufficiently good, the student will submit the paper to a suitable conference/journal.

Pre-requisites: Basic knowledge of computer architecture and embedded systems is required. Furthermore, knowledge in hardware design, including VHDL and FPGA is an advantage.

Schedule: Individually

Language: Deutsch/English

Configuration: 1DS

Lecturer: Prof. Akash Kumar

Description: Overview of modern embedded processor designs and principles with a quick introduction to today's research problems in the domain, including approximate computing and fault-tolerant computing.

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