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ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems

Reference

Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems" , In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi]

Bibtex

@article{Baranwal_2020,
doi = {10.1109/tcad.2020.3028350},
url = {https://doi.org/10.1109%2Ftcad.2020.3028350},
year = 2020,
month={28 October},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Akhil Raj Baranwal and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{ReLAccS}: A Multi-level Approach to Accelerator Design for Reinforcement Learning on {FPGA}-based Systems},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
}

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