cfaed Publications
BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators
Reference
Yuhao Liu, Salim Ullah, Akash Kumar, "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators" (to appear), In Proceeding: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 1-2, 2024.
Bibtex
@INPROCEEDINGS{BitSys_FCCM_Poster,
author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
title={BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators},
year={2024},
volume={},
number={},
pages={1-2},
doi={}}
author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
title={BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators},
year={2024},
volume={},
number={},
pages={1-2},
doi={}}
Downloads
FCCM_Poster_Final_3 [PDF]
Permalink
https://cfaed.tu-dresden.de/publications?pubId=3737