cfaed Publications
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
Reference
Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi]
Bibtex
@article{Ullah_2021,
doi = {10.1109/les.2020.2995053},
url = {https://doi.org/10.1109%2Fles.2020.2995053},
year = 2021,
month = {jun},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {13},
number = {2},
pages = {41--44},
author = {Salim Ullah and Tuan Duy Anh Nguyen and Akash Kumar},
title = {Energy-Efficient Low-Latency Signed Multiplier for {FPGA}-Based Hardware Accelerators},
journal = {{IEEE} Embedded Systems Letters}
}
doi = {10.1109/les.2020.2995053},
url = {https://doi.org/10.1109%2Fles.2020.2995053},
year = 2021,
month = {jun},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {13},
number = {2},
pages = {41--44},
author = {Salim Ullah and Tuan Duy Anh Nguyen and Akash Kumar},
title = {Energy-Efficient Low-Latency Signed Multiplier for {FPGA}-Based Hardware Accelerators},
journal = {{IEEE} Embedded Systems Letters}
}
Downloads
ESL_acc_multiplier [PDF]
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https://cfaed.tu-dresden.de/publications?pubId=2652