cfaed Publications

Energy-Efficient Low-Latency Signed Multiplier for FPGA-based Hardware Accelerators

Reference

S. Ullah, T. D. A. Nguyen, A. Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-based Hardware Accelerators", In IEEE Embedded Systems Letters, May 2020.

Bibtex

@ARTICLE{9094238,
author={S. {Ullah} and T. D. A. {Nguyen} and A. {Kumar}},
journal={IEEE Embedded Systems Letters},
title={Energy-Efficient Low-Latency Signed Multiplier for FPGA-based Hardware Accelerators},
year={2020},
month={May},}

Downloads

ESL_acc_multiplier [PDF]

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https://cfaed.tu-dresden.de/publications?pubId=2652


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