cfaed Publications
Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
Reference
Yuhao Liu, Salim Ullah, Akash Kumar, "Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators" (to appear), In Proceeding: 2025 26th International Symposium on Quality Electronic Design (ISQED), pp. 1-8, 2025.
Bibtex
@INPROCEEDINGS{BitSys2,
author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
booktitle={2025 26th International Symposium on Quality Electronic Design (ISQED)},
title={Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators},
year={2025},
volume={},
number={},
pages={1-8},
keywords={Mixed-precision;Quantized Neural Network;Multiplier;Runtime-Reconfigurable;Accelerator;FPGA},
doi={}}
author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
booktitle={2025 26th International Symposium on Quality Electronic Design (ISQED)},
title={Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators},
year={2025},
volume={},
number={},
pages={1-8},
keywords={Mixed-precision;Quantized Neural Network;Multiplier;Runtime-Reconfigurable;Accelerator;FPGA},
doi={}}
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