cfaed Publications
Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators
Reference
Yuhao Liu, Salim Ullah, Akash Kumar, "Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators", In Proceeding: 2025 26th International Symposium on Quality Electronic Design (ISQED), pp. 1-9, 2025. [doi]
Bibtex
@INPROCEEDINGS{11014376,
author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
booktitle={2025 26th International Symposium on Quality Electronic Design (ISQED)},
title={Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators},
year={2025},
volume={},
number={},
pages={1-9},
keywords={Runtime;Quantization (signal);Accuracy;Neural networks;Memory architecture;Systolic arrays;Delays;Racetrack memory;Object tracking;Clocks},
doi={10.1109/ISQED65160.2025.11014376}}
author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
booktitle={2025 26th International Symposium on Quality Electronic Design (ISQED)},
title={Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators},
year={2025},
volume={},
number={},
pages={1-9},
keywords={Runtime;Quantization (signal);Accuracy;Neural networks;Memory architecture;Systolic arrays;Delays;Racetrack memory;Object tracking;Clocks},
doi={10.1109/ISQED65160.2025.11014376}}
Downloads
BitSys_ISQED [PDF]
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https://cfaed.tu-dresden.de/publications?pubId=3808