cfaed Publications

A CORDIC Based Configurable Activation Function for ANN Applications

Reference

G. Raut, S. Rai, S. K. Vishvakarma, A. Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications", In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 78-83, July 2020. (Best paper nominee) [doi]

Abstract

An efficient ASIC-based hardware design of activation function (AF) in neural networks faces the challenge of offering functional configurability and limited chip area. Therefore an area-efficient configurable architecture for an AF is imperative to fully harness the parallel processing capacity of an ASIC in contrast to a general-purpose processor. To address this, we propose a configurable AF based on the shift-and-add algorithm, collectively known as Co-ordinate Rotation Digital Computer(CORDIC) algorithm. The proposed versatile configurable activation function is designed using CORDIC architecture and implements both tan hyperbolic and sigmoid function. The derived model is synthesized and verified at 45nm technology. Further, in order to address leakage issues at lower technology nodes, we exploit the power-gating technique for the proposed AF based on CORDIC architecture. Our circuit design is extracted in cadence virtuoso and simulated for all physical parameters. With respect to the state-of-the-art, our design architecture shows improvement by 29% in area, 42% in power dissipation and 20% in latency. The used power gating technique saves 30% static power with minimal area overhead. The Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that mean and σ deviation are 180.73µW and 51.7µW respectively which is 60% of the state-of-the-art.

Bibtex

@INPROCEEDINGS{9155065,
author={G. {Raut} and S. {Rai} and S. K. {Vishvakarma} and A. {Kumar}},
booktitle={2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
title={A CORDIC Based Configurable Activation Function for ANN Applications},
year={2020},
pages={78-83},
abstract={An efficient ASIC-based hardware design of activation function (AF) in neural networks faces the challenge of offering functional configurability and limited chip area. Therefore an area-efficient configurable architecture for an AF is imperative to fully harness the parallel processing capacity of an ASIC in contrast to a general-purpose processor. To address this, we propose a configurable AF based on the shift-and-add algorithm, collectively known as Co-ordinate Rotation Digital Computer(CORDIC) algorithm. The proposed versatile configurable activation function is designed using CORDIC architecture and implements both tan hyperbolic and sigmoid function. The derived model is synthesized and verified at 45nm technology. Further, in order to address leakage issues at lower technology nodes, we exploit the power-gating technique for the proposed AF based on CORDIC architecture. Our circuit design is extracted in cadence virtuoso and simulated for all physical parameters. With respect to the state-of-the-art, our design architecture shows improvement by 29% in area, 42% in power dissipation and 20% in latency. The used power gating technique saves 30% static power with minimal area overhead. The Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that mean and σ deviation are 180.73µW and 51.7µW respectively which is 60% of the state-of-the-art.},
keywords={Computer architecture;Hardware;Mathematical model;Biological neural networks;Neurons;Delays;Computational modeling;Artificial neural network;ASIC;CORDIC;compute efficiency;configurable architecture;multi activation function},
doi={10.1109/ISVLSI49217.2020.00024},
ISSN={2159-3477},
month={July},
comment={Best paper nominee}}

Downloads

ISVLSI 2020 Paper [PDF]

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https://cfaed.tu-dresden.de/publications?pubId=2860


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