cfaed Publications

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

Reference

S. Rai, A. Rupani, D. Walter, M. Raitza, A. Heinzig, T. Baldauf, J. Trommer, C. Mayr, W. M. Weber, A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), vol. , no. , pp. 605-608, March 2018. [doi]

Bibtex

@INPROCEEDINGS{8342080,
author={S. Rai and A. Rupani and D. Walter and M. Raitza and A. Heinzig and T. Baldauf and J. Trommer and C. Mayr and W. M. Weber and A. Kumar},
booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs},
year={2018},
volume={},
number={},
pages={605-608},
keywords={field effect transistors;lithography;logic design;logic gates;nanowires;Library Exchange Format;SiNW based RFETs;SiNW based circuits;circuit designers;complete design flow;computational unit;early technology evaluation;fully symmetrical reconfigurable transistors;functionally enhanced transistors;gate terminal;independent gates;lithography steps;logic gates;logic synthesis;n-type functionality;p-type functionality;physical synthesis flow;program gate;silicon nanowire based reconfigurable FETs;silicon nanowire based reconfigurable field-effect transistors;Layout;Logic gates;Mathematical model;Nanoscale devices;Silicon;Tools;Transistors},
doi={10.23919/DATE.2018.8342080},
ISSN={},
month={March},}

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Physical_Synthesis_DATE_2018 [PDF]

Related Paths

Silicon Nanowire Path

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