cfaed Publications
LAKSA: An MLIR-based Higher-Level Synthesis Compiler for Edge Inference
Reference
Jiahong Bi, Lars Schütze, Jeronimo Castrillon, "LAKSA: An MLIR-based Higher-Level Synthesis Compiler for Edge Inference" (to appear), In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Special issue on Compilers, Architecture, and Synthesis of Embedded Systems (CASES'26), IEEE Press, Oct 2026.
Abstract
Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted due to their energy efficiency advantages compared to CPUs and GPUs. To generate high-performance and low-power FPGA designs, several frameworks built upon High Level Synthesis (HLS) vendor tools have been proposed, among which template-based (e.g., FINN) and compiler-based frameworks are gaining traction due to their ease of use. However, existing template-based frameworks often face challenges in extensibility, while frameworks leveraging Multi-Level Intermediate Representation (MLIR) frequently target devices with no stringent resource constraints. To address these limitations, we propose LAKSA, an MLIR-based framework that abstracts and automates the HLS design process for edge devices without relying on template-driven compilation. LAKSA adopts a streaming architecture with carefully managed buffers, specifically designed to accommodate resource constraints while ensuring low latency. Compared to recent MLIR-based frameworks, LAKSA is capable of generating designs that successfully undergo Place and Route (PnR). Even under highly constrained resources and large input sizes, LAKSA achieves a geometric mean of 3.32x speedup compared to the best recent framework. Compared to FINN, LAKSA achieves an average of 1.74x speedup for end-to-end network inference.
Bibtex
author = {Jiahong Bi and Lars Schütze and Jeronimo Castrillon},
title = {{LAKSA}: An MLIR-based Higher-Level Synthesis Compiler for Edge Inference},
abstract = {Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted due to their energy efficiency advantages compared to CPUs and GPUs. To generate high-performance and low-power FPGA designs, several frameworks built upon High Level Synthesis (HLS) vendor tools have been proposed, among which template-based (e.g., FINN) and compiler-based frameworks are gaining traction due to their ease of use. However, existing template-based frameworks often face challenges in extensibility, while frameworks leveraging Multi-Level Intermediate Representation (MLIR) frequently target devices with no stringent resource constraints. To address these limitations, we propose LAKSA, an MLIR-based framework that abstracts and automates the HLS design process for edge devices without relying on template-driven compilation. LAKSA adopts a streaming architecture with carefully managed buffers, specifically designed to accommodate resource constraints while ensuring low latency. Compared to recent MLIR-based frameworks, LAKSA is capable of generating designs that successfully undergo Place and Route (PnR). Even under highly constrained resources and large input sizes, LAKSA achieves a geometric mean of 3.32x speedup compared to the best recent framework. Compared to FINN, LAKSA achieves an average of 1.74x speedup for end-to-end network inference.},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Special issue on Compilers, Architecture, and Synthesis of Embedded Systems (CASES'26)},
location = {Barcelona, Spain},
month = oct,
publisher = {IEEE Press},
year = {2026},
}
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