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Printable Parallel Arrays of Si Nanowire Schottky-Barrier-FETs With Tunable Polarity for Complementary Logic
Reference
Sebastian Pregl, André Heinzig, Larysa Baraban, Gianaurelio Cuniberti, Thomas Mikolajick, Walter M Weber, "Printable Parallel Arrays of Si Nanowire Schottky-Barrier-FETs With Tunable Polarity for Complementary Logic", In IEEE Transactions on Nanotechnology, IEEE, vol. 15, no. 3, pp. 549–556, 2016.
Bibtex
@article{pregl2016printable,
title={Printable Parallel Arrays of Si Nanowire Schottky-Barrier-FETs With Tunable Polarity for Complementary Logic},
author={Pregl, Sebastian and Heinzig, Andr{\'e} and Baraban, Larysa and Cuniberti, Gianaurelio and Mikolajick, Thomas and Weber, Walter M},
journal={IEEE Transactions on Nanotechnology},
volume={15},
number={3},
pages={549--556},
year={2016},
publisher={IEEE}
}
title={Printable Parallel Arrays of Si Nanowire Schottky-Barrier-FETs With Tunable Polarity for Complementary Logic},
author={Pregl, Sebastian and Heinzig, Andr{\'e} and Baraban, Larysa and Cuniberti, Gianaurelio and Mikolajick, Thomas and Weber, Walter M},
journal={IEEE Transactions on Nanotechnology},
volume={15},
number={3},
pages={549--556},
year={2016},
publisher={IEEE}
}
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Related Paths
Silicon Nanowire Path, Silicon Nanowire Path, Silicon Nanowire Path
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