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An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

Reference

S. Hoppner, Dennis Walter, Thomas Hocker, Stephan Henker, S. Hanzsche, Daniel Sausner, Georg Ellguth, J-U Schlussler, Holger Eisenreich, R. Schuffny, "An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS" , IEEE, 2015. [doi]

Bibtex

@article{hoppner2015energy,
title={An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS},
author={Hoppner, S and Walter, Dennis and Hocker, Thomas and Henker, Stephan and Hanzsche, S and Sausner, Daniel and Ellguth, Georg and Schlussler, J-U and Eisenreich, Holger and Schuffny, R},
year={2015},
publisher={IEEE},
doi={10.1109/JSSC.2014.2381637}
}

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