cfaed Publications

@InProceedings{korol_isvlsi23,
author = {Guilherme Korol and Michael Guilherme Jordan and Mateus Beck Rutzig and Jeronimo Castrillon and Antonio Carlos Schneider Beck},
booktitle = {2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
title = {Design Space Exploration for {CNN} Offloading to {FPGAs} at the Edge},
doi = {10.1109/ISVLSI59464.2023.10238644},
location = {Foz do Igua{\c{c}}u, Brazil},
organization = {IEEE},
publisher = {IEEE Computer Society},
url = {https://ieeexplore.ieee.org/abstract/document/10238644},
address = {Los Alamitos, CA, USA},
month = jun,
year = {2023},
location = {Foz do Igua{\c{c}}u, Brazil},
abstract = {AI-based IoT applications relying on heavy-load deep learning algorithms like CNNs challenge IoT devices that are restricted in energy or processing capabilities. Edge computing offers an alternative by allowing the data to get offloaded to so-called edge servers with hardware more powerful than IoT devices and physically closer than the cloud. However, the increasing complexity of data and algorithms and diverse conditions make even powerful devices, such as those equipped with FPGAs, insufficient to cope with the current demands. In this case, optimizations in the algorithms, like pruning and early-exit, are mandatory to reduce the CNNs computational burden and speed up inference processing. With that in mind, we propose ExpOL, which combines the pruning and early-exit CNN optimizations in a system-level FPGA-based IoT-Edge design space exploration. Based on a user-defined multi-target optimization, ExpOL delivers designs tailored to specific application environments and user needs. When evaluated against state-of-the-art FPGA-based accelerators (either local or offloaded), designs produced by ExpOL are more power-efficient (by up to 2x) and process inferences at higher user quality of experience (by up to 12.5%).},
}