cfaed Publications
Design Space Explorations of Novel Hardware Solutions: from Atoms to Applications
Reference
Jeronimo Castrillon, Michael Niemier, "Design Space Explorations of Novel Hardware Solutions: from Atoms to Applications", In Workshop on EcoCompute: Building Sustainable Scientific Computing Practices Through Academia-Industry Collaboration (CECAM) (invited talk), May 2026.
Abstract
This talk will showcase efforts to evaluate technology-driven computer architectures in application-level contexts. A particular emphasis will be made on (a) quantifying the potential efficacy of emerging (random access as well as intelligent) memory solutions for at scale workloads and (b) memory technologies that (at present) are of most interest to major semiconductor companies and are thereby more likely to become commercially available for end users (e.g., Intel, Samsung, TSMC per targeted research efforts in the Semiconductor Research Corporation’s JUMP 2.0 SUPREME research center). We will describe both bottom-up and top-down evaluation methodologies that may be employed to quantify figures of merit such as read and write latency, write energy, endurance, etc. – all of which will either directly or indirectly inform computational sustainability. We will also highlight recent work from our collaborators in the compilers community that employs multilevel intermediate representations (MLIR) to preserve program structure to generate ideal HLL to accelerator mappings (e.g., mapping Euclidean distance calculations to technology-enabled associative memory hardware that can perform said computations in-situ, thereby eliminating data transfer overhead). While recent work does aim to minimize write events owing to energy and endurance concerns of non-volatile memories, our goal is to specifically quantify array-level figures of merit for all emerging memories, thereby allowing the compiler to identify/down select to viable hardware solutions for a given workload. We will highlight recent efforts in this regard, as well as how it may create a feedback loop to materials science and device research to develop technology with maximal application-level impact.
Bibtex
author = {Jeronimo Castrillon and Michael Niemier},
date = {2026-05},
title = {Design Space Explorations of Novel Hardware Solutions: from Atoms to Applications},
howpublished = {Workshop on EcoCompute: Building Sustainable Scientific Computing Practices Through Academia-Industry Collaboration (CECAM) (invited talk)},
location = {Lugano, Switzerland},
abstract = {This talk will showcase efforts to evaluate technology-driven computer architectures in application-level contexts. A particular emphasis will be made on (a) quantifying the potential efficacy of emerging (random access as well as intelligent) memory solutions for at scale workloads and (b) memory technologies that (at present) are of most interest to major semiconductor companies and are thereby more likely to become commercially available for end users (e.g., Intel, Samsung, TSMC per targeted research efforts in the Semiconductor Research Corporation’s JUMP 2.0 SUPREME research center). We will describe both bottom-up and top-down evaluation methodologies that may be employed to quantify figures of merit such as read and write latency, write energy, endurance, etc. – all of which will either directly or indirectly inform computational sustainability. We will also highlight recent work from our collaborators in the compilers community that employs multilevel intermediate representations (MLIR) to preserve program structure to generate ideal HLL to accelerator mappings (e.g., mapping Euclidean distance calculations to technology-enabled associative memory hardware that can perform said computations in-situ, thereby eliminating data transfer overhead). While recent work does aim to minimize write events owing to energy and endurance concerns of non-volatile memories, our goal is to specifically quantify array-level figures of merit for all emerging memories, thereby allowing the compiler to identify/down select to viable hardware solutions for a given workload. We will highlight recent efforts in this regard, as well as how it may create a feedback loop to materials science and device research to develop technology with maximal application-level impact.},
month = may,
year = {2026},
}
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https://cfaed.tu-dresden.de/publications?pubId=3887


