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Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture
Reference
Shashikanth Bobba, Giovanni De Micheli, "Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture", IEEE, 2013.
Bibtex
@article{bobba2013layout,
title={Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture},
author={Bobba, Shashikanth and De Micheli, Giovanni},
year={2013},
publisher={IEEE}
}
title={Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture},
author={Bobba, Shashikanth and De Micheli, Giovanni},
year={2013},
publisher={IEEE}
}
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