SecuReFET: Secure Circuits through inherent Reconfigurable FET
Today’s societies critically depend on electronic systems. Over the last years, the security of these systems has been at risk by a number of hardware-level attacks that circumvent software-level security mechanisms. Solutions based on classical CMOS electronics have been shown to be either cost-intensive due to a high area overhead or energy inefficient. One promising option to fight against these hardware-level attacks in the future electronic system is emerging nanotechnologies, such as reconfigurable field-effect transistors (RFETs) with programmable p- and n-function. The runtime-reconfigurable nature of those nano-electronic devices yields to an inherent polymorphic functionality at the logic gate level. As a result, circuits made of regular RFET blocks are able to provide a large number of possible functional combinations based on the apparently same circuit representation. The manufacturers, therefore, are able to program the desired functionality after chip production. The big difference to standard CMOS electronics is, that the actual circuit or function remains hidden since they cannot be differentiated from other possible combinations by physical reverse engineering or electrical monitoring of the circuit (i.e., by side-channel attacks).
In SecuReFET, such circuits will be developed exploiting the inherent polymorphic property of RFETs. RFET-based secure circuit cells, which aim to protect proprietary IP designs and provide physically unclonable functions, will be designed, modeled, manufactured, and measured. The benefit of those cells regarding their resilience against side-channel attacks and reverse engineering will be demonstrated. In addition, potential security threats stemming from the reconfigurable nature of the technology, such as hardware Trojans, will be investigated. Measures to mitigate those vulnerabilities by the circuit as well as device design will be established. Furthermore, an RFET-compatible automated design-synthesis environment (EDA) for logic and physical design of security circuits will be established based on modified modern design rules. Finally, the developed concepts will be verified and benchmarked by means of modern security tests.
Project title: Secure Circuits through inherent Reconfigurable FET
Funding period: July 2020 - June 2023
Funding program: DFG SPP Nano-Security
- Mark Wijtvliet, postdoc
- Jan Gärtner; process support
- Thorsten Neuhaus, tool support
Attribution within the Priority Program:
- Area 1 “Nano-electronics for Security“
- Interdisciplinary Group IG1 “Secret Generation”
- Interdisciplinary Group IG3 “Physical Attack Resilience”