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Prof. Dr. Akash Kumar |
||
Phone Fax Visitor's Address |
+49 351 463-39274 +49 351 463-39995 Helmholtzstrasse 18, BAR-III73-74 |
Akash Kumar is a chaired Professor of Processor Design (with tenure) in the department of Computer Science at Technische Universität Dresden (TUD), Germany. From 2009 to 2015, he was with the Department of Electrical and Computer Engineering, NUS. He received the joint Ph.D. degree in electrical engineering in embedded systems from Eindhoven University of Technology (TU/e) and National University of Singapore (NUS), in 2009; joint Master’s degree from TU/e and NUS in 2005 in embedded systems and Bachelor of Computer Engineering degree from NUS in 2002.
His research interests span various aspects of design automation in the context of embedded real-time systems, particularly emphasizing reliable, resource-efficient and predictable architectures for embedded systems, including FPGA-based architectures. His research spans across various layers in the system design from hardware design to application analysis. He has published close to 170 articles in premier international conferences and journals in the area of design automation. He has released many open-source tool flows with his research group for system design and analysis to allow the community to reproduce their results and further research in the related areas.
He serves (or has recently served) on the program committee of renowned conferences in the area like DAC, DATE, FPL and CASES. He was the program chair of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’18 and ’19), Embedded Systems for Real-Time Multimedia (ESTIMedia ’17), subcommittee chair for several editions of Design Automation and Test in Europe (DATE) conference and Brief Presentations Chair for Real-time Systems Symposium (RTSS’19) and Associate Editor for Elsevier Microprocessors and Microsystems journal for 2013-2017 and ACM Transactions on Embedded Computing Systems (TECS) special issue. He is an associate editor for IEEE Transactions on Circuits and Systems II, IEEE Embedded Systems Letters (ESL), IEEE Design and Test and MDPI Electronics. He was the program chair for IEEE International Conference on Field Programmable Logic and Applications 2021.
He has received Best Paper Award at DATA 2018, and best paper award nominations at DATE 2015, 2017 and 2020, FPL 2014, GLSVLSI 2014, ISVLSI 2020 and Supercomputing Conference 2015. His group also received HiPEAC Technology transfer award 2019. His current publication and citation profile can be found at Google scholar. According to CS-rankings, he is one of the most published professors in top conferences at TU Dresden in Computer Science. The DBLP profile can be found at this link.
His CV can be found here.
Publications
2024
- 187. Behnaz Ranjbar, Paul Justen, Akash Kumar, "GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems" (to appear), In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), October 2024. [doi] [Bibtex & Downloads]
GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems
Reference
Behnaz Ranjbar, Paul Justen, Akash Kumar, "GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems" (to appear), In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), October 2024. [doi]
Bibtex
@article{Ranjbar_2024,
doi = {10.1109/LES.2024.3466268)},
year = 2024,
month = {October},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
author = {Behnaz Ranjbar and Paul Justen and Akash Kumar},
title = {GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems},
journal = {IEEE Embedded Systems Letters}
}Downloads
2024-LES [PDF]
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- 186. H. Mehrabian, A. Kumar, "FedPoll: A Novel Robustness and Communication-Efficient Aggregation Method", In Proceeding: 2nd IEEE International Conference on Federated Learning Technologies and Applications (FLTA24), pp. 1-9, Sep 2024. [Bibtex & Downloads]
FedPoll: A Novel Robustness and Communication-Efficient Aggregation Method
Reference
H. Mehrabian, A. Kumar, "FedPoll: A Novel Robustness and Communication-Efficient Aggregation Method", In Proceeding: 2nd IEEE International Conference on Federated Learning Technologies and Applications (FLTA24), pp. 1-9, Sep 2024.
Bibtex
@INPROCEEDINGS{mehrabian_flta24, author={Hamidreza Mehrabian and Akash Kumar}, booktitle={2nd IEEE International Conference on Federated Learning Technologies and Applications (FLTA24)}, title={FedPoll: A Novel Robustness and Communication-Efficient Aggregation Method}, year={2024}, month={sep}, volume={}, number={}, pages={1-9} }Downloads
45_6717 [PDF]
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- 185. Siva Satyendra Sahoo, Salim Ullah, Soumyo Bhattacharjee, Akash Kumar, "AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling", In IEEE Transactions on Circuits and Systems I: Regular Papers, Institute of Electrical and Electronics Engineers (IEEE), vol. 71, no. 6, pp. 2646–2659, Jun 2024. [doi] [Bibtex & Downloads]
AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling
Reference
Siva Satyendra Sahoo, Salim Ullah, Soumyo Bhattacharjee, Akash Kumar, "AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling", In IEEE Transactions on Circuits and Systems I: Regular Papers, Institute of Electrical and Electronics Engineers (IEEE), vol. 71, no. 6, pp. 2646–2659, Jun 2024. [doi]
Bibtex
@article{Sahoo_2024, title={AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling}, volume={71}, ISSN={1558-0806}, url={http://dx.doi.org/10.1109/TCSI.2024.3385333}, DOI={10.1109/tcsi.2024.3385333}, number={6}, journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sahoo, Siva Satyendra and Ullah, Salim and Bhattacharjee, Soumyo and Kumar, Akash}, year={2024}, month=jun, pages={2646–2659} }Downloads
No Downloads available for this publication
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- 184. Yuhao Liu, Salim Ullah, Akash Kumar, "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators", In Proceeding: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp. 220–220, May 2024. [doi] [Bibtex & Downloads]
BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators
Reference
Yuhao Liu, Salim Ullah, Akash Kumar, "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators", In Proceeding: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp. 220–220, May 2024. [doi]
Bibtex
@inproceedings{Liu_2024, title={BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators}, url={http://dx.doi.org/10.1109/fccm60383.2024.00042}, DOI={10.1109/fccm60383.2024.00042}, booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Liu, Yuhao and Ullah, Salim and Kumar, Akash}, year={2024}, month=may, pages={220–220} }Downloads
FCCM_Poster_Final_3 [PDF]
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- 183. Max Sponner, Bernd Waschneck, Akash Kumar, "Adapting Neural Networks at Runtime: Current Trends in At-Runtime Optimizations for Deep Learning", In ACM Computing Surveys, Association for Computing Machinery (ACM), Apr 2024. [doi] [Bibtex & Downloads]
Adapting Neural Networks at Runtime: Current Trends in At-Runtime Optimizations for Deep Learning
Reference
Max Sponner, Bernd Waschneck, Akash Kumar, "Adapting Neural Networks at Runtime: Current Trends in At-Runtime Optimizations for Deep Learning", In ACM Computing Surveys, Association for Computing Machinery (ACM), Apr 2024. [doi]
Bibtex
@article{Sponner_2024, title={Adapting Neural Networks at Runtime: Current Trends in At-Runtime Optimizations for Deep Learning}, ISSN={1557-7341}, url={http://dx.doi.org/10.1145/3657283}, DOI={10.1145/3657283}, journal={ACM Computing Surveys}, publisher={Association for Computing Machinery (ACM)}, author={Sponner, Max and Waschneck, Bernd and Kumar, Akash}, year={2024}, month=apr }Downloads
No Downloads available for this publication
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- 182. Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming", In ACM Transactions on Reconfigurable Technology and Systems (TRETS), pp. 1–28, April 2024. [Bibtex & Downloads]
AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming
Reference
Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming", In ACM Transactions on Reconfigurable Technology and Systems (TRETS), pp. 1–28, April 2024.
Bibtex
@article{siva_trets_2024,
title={AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming},
author={Sahoo, Siva Satyendra and Ullah, Salim and Kumar, Akash},
journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
volume={},
number={},
pages={1--28},
year={2024},
month={April}
}Downloads
No Downloads available for this publication
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- 181. Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "Utilizing Machine Learning Techniques for Worst-Case Execution Time Estimation on GPU Architectures", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–15, March 2024. [doi] [Bibtex & Downloads]
Utilizing Machine Learning Techniques for Worst-Case Execution Time Estimation on GPU Architectures
Reference
Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "Utilizing Machine Learning Techniques for Worst-Case Execution Time Estimation on GPU Architectures", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–15, March 2024. [doi]
Bibtex
@article{VKumar_2024,
doi = {10.1109/ACCESS.2024.3379018},
year = 2024,
month = {March},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--15},
author = {Vikash Kumar and Behnaz Ranjbar and Akash Kumar},
title = {Utilizing Machine Learning Techniques for Worst-Case Execution Time Estimation on GPU Architectures},
journal = {{IEEE} Access}
}Downloads
No Downloads available for this publication
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- 180. Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2024. [doi] [Bibtex & Downloads]
Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems
Reference
Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2024. [doi]
Bibtex
@INPROCEEDINGS{behnaz2024date,
author={Kumar, Vikash and Ranjbar, Behnaz and Kumar, Akash},
booktitle={2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
title={Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems},
year={2024},
month={Mar.},
doi = {10.23919/DATE58400.2024.10546654},
organization={IEEE}}Downloads
2024-DATE [PDF]
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- 179. Paul Jungmann, Julia Poray, Akash Kumar, "Analytical Uncertainty Propagation in Neural Networks", In IEEE Transactions on Neural Networks and Learning Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–14, 2024. [doi] [Bibtex & Downloads]
Analytical Uncertainty Propagation in Neural Networks
Reference
Paul Jungmann, Julia Poray, Akash Kumar, "Analytical Uncertainty Propagation in Neural Networks", In IEEE Transactions on Neural Networks and Learning Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–14, 2024. [doi]
Bibtex
@article{Jungmann_2024, title={Analytical Uncertainty Propagation in Neural Networks}, ISSN={2162-2388}, url={http://dx.doi.org/10.1109/tnnls.2023.3347156}, DOI={10.1109/tnnls.2023.3347156}, journal={IEEE Transactions on Neural Networks and Learning Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Jungmann, Paul and Poray, Julia and Kumar, Akash}, year={2024}, pages={1–14} }Downloads
No Downloads available for this publication
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- 178. G. Noble, S. Nalesh, S. Kala, Akash Kumar, "Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects", In Alexandria Engineering Journal, vol. 91, pp. 84-94, 2024. [doi] [Bibtex & Downloads]
Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects
Reference
G. Noble, S. Nalesh, S. Kala, Akash Kumar, "Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects", In Alexandria Engineering Journal, vol. 91, pp. 84-94, 2024. [doi]
Bibtex
@article{NOBLE202484,
title = {Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects},
journal = {Alexandria Engineering Journal},
volume = {91},
pages = {84-94},
year = {2024},
issn = {1110-0168},
doi = {https://doi.org/10.1016/j.aej.2024.01.075},
url = {https://www.sciencedirect.com/science/article/pii/S1110016824001145},
author = {G. Noble and S. Nalesh and S. Kala and Akash Kumar},
keywords = {Accelerator, FPGA, Outer product, Sparse matrix multiplication, SpGEMM, Quantization},
}Downloads
No Downloads available for this publication
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- 177. Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar, "QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] [Bibtex & Downloads]
QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit
Reference
Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar, "QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]
Bibtex
@article{Ashar_2024, title={QuantMAC: Enhancing Hardware Performance in DNNs with Quantize Enabled Multiply-Accumulate Unit}, ISSN={2169-3536}, url={http://dx.doi.org/10.1109/ACCESS.2024.3379906}, DOI={10.1109/access.2024.3379906}, journal={IEEE Access}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Ashar, Neha and Raut, Gopal and Trivedi, Vasundhara and Vishvakarma, Santosh Kumar and Kumar, Akash}, year={2024}, pages={1–1} }Downloads
No Downloads available for this publication
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- 176. Nima Kavand, Armin Darjani, Giulio Galderisi, Jens Trommer, Thomas Mikolajick, Akash Kumar, "REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024. [Bibtex & Downloads]
REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks
Reference
Nima Kavand, Armin Darjani, Giulio Galderisi, Jens Trommer, Thomas Mikolajick, Akash Kumar, "REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024.
Bibtex
@inproceedings{kavand2024redcap, title={REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks}, author={Kavand, Nima and Darjani, Armin and Galderisi, Giulio and Trommer, Jens and Mikolajick, Thomas, and Kumar, Akash}, booktitle={2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, year={2024}, organization={IEEE} }Downloads
No Downloads available for this publication
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- 175. Niladri Bhattacharjee, Viktor Havel, Suruchi Kumari, Nima Kavand, Jorge Navarro Quijada, Akash Kumar, Thomas Mikolajick, Jens Trommer, "Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024. [Bibtex & Downloads]
Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology
Reference
Niladri Bhattacharjee, Viktor Havel, Suruchi Kumari, Nima Kavand, Jorge Navarro Quijada, Akash Kumar, Thomas Mikolajick, Jens Trommer, "Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology" (to appear), In Proceeding: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024.
Bibtex
@inproceedings{bhattacharjee2024dynamic, title={Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology}, author={Bhattacharjee, Niladri and Havel, Viktor and Kumari, Suruchi and Kavand, Nima and Navarro Quijada, Jorge and Kumar, Akash and Mikolajick, Thomas and Trommer, Jens}, booktitle={2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, year={2024}, organization={IEEE} }Downloads
No Downloads available for this publication
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- 174. Zahra Ebrahimi, Akash Kumar, "GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient ProcessiNg at the Edge", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] [Bibtex & Downloads]
GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient ProcessiNg at the Edge
Reference
Zahra Ebrahimi, Akash Kumar, "GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient ProcessiNg at the Edge", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]
Bibtex
@article{Ebrahimi_2024, title={GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient ProcessiNg at the Edge}, ISSN={1937-4151}, url={http://dx.doi.org/10.1109/TCAD.2024.3383349}, DOI={10.1109/tcad.2024.3383349}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Ebrahimi, Zahra and Kumar, Akash}, year={2024}, pages={1–1} }Downloads
GREEN_TCAD3383349_camera-ready [PDF]
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- 173. Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "ESOMICS: ML-Based Timing Behaviour Analysis For Efficient Mixed-Criticality System Design", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] [Bibtex & Downloads]
ESOMICS: ML-Based Timing Behaviour Analysis For Efficient Mixed-Criticality System Design
Reference
Vikash Kumar, Behnaz Ranjbar, Akash Kumar, "ESOMICS: ML-Based Timing Behaviour Analysis For Efficient Mixed-Criticality System Design", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]
Bibtex
@article{Kumar_2024, title={ESOMICS: ML-Based Timing Behaviour Analysis For Efficient Mixed-Criticality System Design}, ISSN={2169-3536}, url={http://dx.doi.org/10.1109/ACCESS.2024.3396225}, DOI={10.1109/access.2024.3396225}, journal={IEEE Access}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Kumar, Vikash and Ranjbar, Behnaz and Kumar, Akash}, year={2024}, pages={1–1} }Downloads
No Downloads available for this publication
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- 172. Elias Trommer, Bernd Waschneck, Akash Kumar, "Smaller together: Groupwise Encoding of Sparse Neural Networks", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [Bibtex & Downloads]
Smaller together: Groupwise Encoding of Sparse Neural Networks
Reference
Elias Trommer, Bernd Waschneck, Akash Kumar, "Smaller together: Groupwise Encoding of Sparse Neural Networks", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024.
Bibtex
@article{Elias_TCAD_2024, title={Smaller together: Groupwise Encoding of Sparse Neural Networks}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Trommer, Elias and Waschneck, Bernd and Kumar, Akash}, year={2024}, pages={1–1} }Downloads
ieee_tcad_smaller_together [PDF]
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- 171. Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Thwarting GNN-based attacks against logic locking", In IEEE Transactions on Information Forensics and Security, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] [Bibtex & Downloads]
Thwarting GNN-based attacks against logic locking
Reference
Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Thwarting GNN-based attacks against logic locking", In IEEE Transactions on Information Forensics and Security, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]
Bibtex
@article{Darjani_2024, title={Thwarting GNN-based attacks against logic locking}, ISSN={1556-6021}, url={http://dx.doi.org/10.1109/TIFS.2024.3431991}, DOI={10.1109/tifs.2024.3431991}, journal={IEEE Transactions on Information Forensics and Security}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Darjani, Armin and Kavand, Nima and Rai, Shubham and Kumar, Akash}, year={2024}, pages={1–1} }Downloads
No Downloads available for this publication
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- 170. Maryam Eslami, Yuhao Liu, Salim Ullah, Mostafa Ersali Salehi Nasab, Reshad Hosseini, Seyed Ahmad Mirsalari, Akash Kumar, "MONO: Enhancing Bit-Flip Resilience with Bit Homogeneity for Neural Networks" (to appear), In IEEE Embedded Systems Letters, pp. 1-1, 2024. [Bibtex & Downloads]
MONO: Enhancing Bit-Flip Resilience with Bit Homogeneity for Neural Networks
Reference
Maryam Eslami, Yuhao Liu, Salim Ullah, Mostafa Ersali Salehi Nasab, Reshad Hosseini, Seyed Ahmad Mirsalari, Akash Kumar, "MONO: Enhancing Bit-Flip Resilience with Bit Homogeneity for Neural Networks" (to appear), In IEEE Embedded Systems Letters, pp. 1-1, 2024.
Bibtex
@ARTICLE{10261986,
author={Eslami, Maryam, and Liu, Yuhao and Ullah, Salim and Salehi Nasab, Mostafa Ersali and Hosseini, Reshad and Mirsalari, Seyed Ahmad and Kumar, Akash},
journal={IEEE Embedded Systems Letters},
title={MONO: Enhancing Bit-Flip Resilience with Bit Homogeneity for Neural Networks},
year={2024},
volume={},
number={},
pages={1-1},
doi={}}Downloads
No Downloads available for this publication
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2023
- 169. Rohit Agrawal, Kapil Ahuja, Dhaarna Maheshwari, Mohd Ubaid Shaikh, Mohamed Bouaziz, Akash Kumar, "Parallel FPGA Routers with Lagrange Relaxation", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, November 2023. [doi] [Bibtex & Downloads]
Parallel FPGA Routers with Lagrange Relaxation
Reference
Rohit Agrawal, Kapil Ahuja, Dhaarna Maheshwari, Mohd Ubaid Shaikh, Mohamed Bouaziz, Akash Kumar, "Parallel FPGA Routers with Lagrange Relaxation", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, November 2023. [doi]
Bibtex
@article{Agrawal_2023,
doi = {10.1109/access.2023.3328769},
url = {https://doi.org/10.1109%2Faccess.2023.3328769},
year = 2023,
month={November},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Rohit Agrawal and Kapil Ahuja and Dhaarna Maheshwari and Mohd Ubaid Shaikh and Mohamed Bouaziz and Akash Kumar},
title = {Parallel {FPGA} Routers with Lagrange Relaxation},
journal = {{IEEE} Access}
}Downloads
Manuscript[2] [PDF]
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- 168. Mark Wijtvliet, Henk Corporaal, Akash Kumar, "Blocks: Auf dem Weg zu Energieeffizienten, Grobkörnigen, Rekonfigurierbaren Architekturen (CGRA)", Springer International Publishing, November 2023. [doi] [Bibtex & Downloads]
Blocks: Auf dem Weg zu Energieeffizienten, Grobkörnigen, Rekonfigurierbaren Architekturen (CGRA)
Reference
Mark Wijtvliet, Henk Corporaal, Akash Kumar, "Blocks: Auf dem Weg zu Energieeffizienten, Grobkörnigen, Rekonfigurierbaren Architekturen (CGRA)", Springer International Publishing, November 2023. [doi]
Bibtex
@book{Wijtvliet_2023,
doi = {10.1007/978-3-031-36650-5},
url = {https://doi.org/10.1007%2F978-3-031-36650-5},
year = 2023,
month={November},
publisher = {Springer International Publishing},
author = {Mark Wijtvliet and Henk Corporaal and Akash Kumar},
title = {Blocks: Auf dem Weg zu Energieeffizienten, Grobkörnigen, Rekonfigurierbaren Architekturen ({CGRA})}
}Downloads
No Downloads available for this publication
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- 167. Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations", Chapter in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer International Publishing, pp. 89–119, Oct 2023. [doi] [Bibtex & Downloads]
Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations
Reference
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations", Chapter in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer International Publishing, pp. 89–119, Oct 2023. [doi]
Bibtex
@incollection{Ullah_2023,
doi = {10.1007/978-3-031-19568-6_4},
url = {https://doi.org/10.1007%2F978-3-031-19568-6_4},
year = 2023,
month = {oct},
publisher = {Springer International Publishing},
pages = {89--119},
author = {Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {Designing Resource-Efficient Hardware Arithmetic for {FPGA}-Based Accelerators Leveraging Approximations and Mixed Quantizations},
booktitle = {Embedded Machine Learning for Cyber-Physical, {IoT}, and Edge Computing}
}Downloads
No Downloads available for this publication
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- 166. Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators", In ACM Trans. Embed. Comput. Syst., Association for Computing Machinery, vol. 22, no. 5s, New York, NY, USA, Sep 2023. [doi] [Bibtex & Downloads]
AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators
Reference
Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators", In ACM Trans. Embed. Comput. Syst., Association for Computing Machinery, vol. 22, no. 5s, New York, NY, USA, Sep 2023. [doi]
Bibtex
@article{10.1145/3609096,
author = {Sahoo, Siva Satyendra and Ullah, Salim and Kumar, Akash},
title = {AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators},
year = {2023},
issue_date = {October 2023},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {22},
number = {5s},
issn = {1539-9087},
url = {https://doi.org/10.1145/3609096},
doi = {10.1145/3609096},
journal = {ACM Trans. Embed. Comput. Syst.},
month = sep,
articleno = {101},
numpages = {26},
keywords = {Monte Carlo Tree Search, AI-based exploration, Approximate computing, circuit synthesis, automated hardware design, arithmetic operator design, computer arithmetic}
}Downloads
AxOTreeS-cases-esweek-tecs-2023 [PDF]
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- 165. Max Sponner, Julius Ott, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "Temporal Patience: Efficient Adaptive Deep Learning for Embedded Radar Data Processing", In ACM Workshop on Compilers, Deployment, and Tooling for Edge AI (CODAI), September 2023. [Bibtex & Downloads]
Temporal Patience: Efficient Adaptive Deep Learning for Embedded Radar Data Processing
Reference
Max Sponner, Julius Ott, Lorenzo Servadei, Bernd Waschneck, Robert Wille, Akash Kumar, "Temporal Patience: Efficient Adaptive Deep Learning for Embedded Radar Data Processing", In ACM Workshop on Compilers, Deployment, and Tooling for Edge AI (CODAI), September 2023.
Bibtex
@article{sponner2023temporal,
title={Temporal Patience: Efficient Adaptive Deep Learning for Embedded Radar Data Processing},
author={Max Sponner and Julius Ott and Lorenzo Servadei and Bernd Waschneck and Robert Wille and Akash Kumar},
journal={ACM Workshop on Compilers, Deployment, and Tooling for Edge AI (CODAI)},
year={2023},
month={September}
}Downloads
temporal [PDF]
Permalink
- 164. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers", In IEEE Embedded Systems Letters, pp. 1-1, 2023. [doi] [Bibtex & Downloads]
High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers", In IEEE Embedded Systems Letters, pp. 1-1, 2023. [doi]
Bibtex
@ARTICLE{10261986,
author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
journal={IEEE Embedded Systems Letters},
title={High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers},
year={2023},
volume={},
number={},
pages={1-1},
doi={10.1109/LES.2023.3298736}}Downloads
ESL_LB_CASES_2023 Camera ready [PDF]
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- 163. Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi] [Bibtex & Downloads]
NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories
Reference
Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi]
Bibtex
@article{Zhao_2023,
doi = {10.1109/les.2023.3299202},
url = {https://doi.org/10.1109%2Fles.2023.3299202},
year = 2023,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Yuankang Zhao and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{NvMISC}: Towards an {FPGA}-Based Emulation Platform for {RISC}-V and Non-Volatile Memories},
journal = {{IEEE} Embedded Systems Letters}
}Downloads
NvMISC_Towards_an_FPGA-Based_Emulation_Platform_for_RISC-V_and_Non-Volatile_Memories_ESL [PDF]
Permalink
- 162. Behnaz Ranjbar, Alireza Ejlali, Akash Kumar, "Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems", Springer, September 2023. [Bibtex & Downloads]
Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems
Reference
Behnaz Ranjbar, Alireza Ejlali, Akash Kumar, "Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems", Springer, September 2023.
Bibtex
@book{Ranjbar2023Book,
title={Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems},
author={Ranjbar, Behnaz and Ejlali, Alireza and Kumar, Akash},
year={2023},
month = {September},
url={https://doi.org/10.1007/978-3-031-38960-3},
publisher={Springer}
}Downloads
No Downloads available for this publication
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- 161. Behnaz Ranjbar, Ali Hosseinghorban, Akash Kumar, "ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi] [Bibtex & Downloads]
ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems
Reference
Behnaz Ranjbar, Ali Hosseinghorban, Akash Kumar, "ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi]
Bibtex
@inproceedings{Ranjbar_DAC_2023,
year = 2023,
month = {July},
author = {Behnaz Ranjbar and Ali Hosseinghorban and Akash Kumar},
title = {ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems},
booktitle = {Design Automation Conference (DAC)},
pages={1-6},
doi={10.1109/DAC56929.2023.10248007}
}Downloads
1215_Camera_Ready_Paper [PDF]
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- 160. Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Discerning the Limitations of GNN-Based Attacks on Logic Locking", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi] [Bibtex & Downloads]
Discerning the Limitations of GNN-Based Attacks on Logic Locking
Reference
Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Discerning the Limitations of GNN-Based Attacks on Logic Locking", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi]
Bibtex
@inproceedings{Darjani_DAC_2023,
year = 2023,
month = {July},
author = {Armin Darjani and Nima Kavand and Shubham Rai and Akash Kumar},
title = {Discerning the Limitations of GNN-Based Attacks on Logic Locking},
booktitle = {Design Automation Conference (DAC)},
pages={1-6},
doi={10.1109/DAC56929.2023.10247847}
}Downloads
DAC2023_Cirrostrato [PDF]
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- 159. Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators", Proceedings of the Great Lakes Symposium on VLSI 2023, ACM, Jun 2023. [doi] [Bibtex & Downloads]
CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators
Reference
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators", Proceedings of the Great Lakes Symposium on VLSI 2023, ACM, Jun 2023. [doi]
Bibtex
@inproceedings{Ullah_2023,
doi = {10.1145/3583781.3590222},
url = {https://doi.org/10.1145%2F3583781.3590222},
year = 2023,
month = {jun},
publisher = ,
author = {Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{CoOAx}: Correlation-aware Synthesis of {FPGA}-based Approximate Operators},
booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023}
}Downloads
Application_specific_AI_inference_on_FPGAs-5 [PDF]
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- 158. Raghul Saravanan, Sathwika Bavikadi, Shubham Rai, Akash Kumar, Sai Manoj Pudukotai Dinakarrao, "Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications", In Proceeding: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2023. [Bibtex & Downloads]
Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications
Reference
Raghul Saravanan, Sathwika Bavikadi, Shubham Rai, Akash Kumar, Sai Manoj Pudukotai Dinakarrao, "Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications", In Proceeding: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2023.
Bibtex
@inproceedings{Rai_2023,
year = 2023,
month = {may},
publisher = ,
author = {Raghul Saravanan and Sathwika Bavikadi and Shubham Rai and Akash Kumar and Sai Manoj Pudukotai Dinakarrao},
title = {Reconfigurable {FET} Approximate Computing-Based Accelerator for Deep Learning Applications},
booktitle = {IEEE International Symposium on Circuits and Systems ({ISCAS})}
}Downloads
No Downloads available for this publication
Permalink
- 157. Elias Trommer, Bernd Waschneck, Akash Kumar, "Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks", In Proceeding: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, May 2023. [Bibtex & Downloads]
Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks
Reference
Elias Trommer, Bernd Waschneck, Akash Kumar, "Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks", In Proceeding: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, May 2023.
Bibtex
@inproceedings{Trommer_DDECS,
year = 2023,
month = {may},
publisher = ,
author = {Elias Trommer and Bernd Waschneck and Akash Kumar},
title = {Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks},
booktitle = {International Symposium on Design and Diagnostics of Electronic Circuits and Systems ({DDECS})}
}Downloads
No Downloads available for this publication
Permalink
- 156. Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers", In IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, May 2023. [doi] [Bibtex & Downloads]
Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers
Reference
Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers", In IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, May 2023. [doi]
Bibtex
@ARTICLE{Kavand2023,
author={Kavand, Nima and Darjani, Armin and Rai, Shubham and Kumar, Akash},
journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
title={Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers},
year={2023},
month = {May},
volume={},
number={},
pages={1-1},
doi={10.1109/TCSII.2023.3275983}}Downloads
RFET_Compressor_TCASII_brief (5) [PDF]
Permalink
- 155. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi] [Bibtex & Downloads]
NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi]
Bibtex
@INPROCEEDINGS{10196610,
author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
booktitle={2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
title={NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs},
year={2023},
volume={},
number={},
pages={85-92},
doi={10.1109/IPDPSW59300.2023.00026}}Downloads
RAW2023-NetPU-M [PDF]
Permalink
- 154. Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed Elkacem Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski, Maciej Wiatr, "Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors", In Proceeding: Design, Automation and Test in Europe Conference (DATE), IEEE/ACM, April 2023. [Bibtex & Downloads]
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors
Reference
Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed Elkacem Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski, Maciej Wiatr, "Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors", In Proceeding: Design, Automation and Test in Europe Conference (DATE), IEEE/ACM, April 2023.
Bibtex
@inproceedings{Rai_DATE_2023,
year = 2023,
month = {April},
publisher = ,
author = {Jens Trommer and Niladri Bhattacharjee and Thomas Mikolajick and Sebastian Huhn and Marcel Merten and Mohammed Elkacem Djeridane and Muhammad Hassan and Rolf Drechsler and Shubham Rai and Nima Kavand and Armin Darjani and Akash Kumar and Violetta Sessi and Maximilian Drescher and Sabine Kolodinski and Maciej Wiatr},
title = {Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors},
booktitle = {Design, Automation and Test in Europe Conference ({DATE})}
}Downloads
DATE_2023_Cirrostrato [PDF]
Permalink
- 153. Behnaz Ranjbar, Amit Kumar Singh, Siva Satyendra Sahoo, Piotr Dziurzanski, Akash Kumar, "Power Management of Multicore Systems", Chapter in Handbook of Computer Architecture, Springer Nature Singapore, pp. 1–33, 2023. [doi] [Bibtex & Downloads]
Power Management of Multicore Systems
Reference
Behnaz Ranjbar, Amit Kumar Singh, Siva Satyendra Sahoo, Piotr Dziurzanski, Akash Kumar, "Power Management of Multicore Systems", Chapter in Handbook of Computer Architecture, Springer Nature Singapore, pp. 1–33, 2023. [doi]
Bibtex
@incollection{Ranjbar_2023,
doi = {10.1007/978-981-15-6401-7_55-1},
url = {https://doi.org/10.1007%2F978-981-15-6401-7_55-1},
year = 2023,
publisher = {Springer Nature Singapore},
pages = {1--33},
author = {Behnaz Ranjbar and Amit Kumar Singh and Siva Satyendra Sahoo and Piotr Dziurzanski and Akash Kumar},
title = {Power Management of Multicore Systems},
booktitle = {Handbook of Computer Architecture}
}Downloads
No Downloads available for this publication
Permalink
- 152. Behnaz Ranjbar, Ali Hosseinghorban, Akash Kumar, "Motivating Agent-Based Learning For Bounding Time in Mixed-Criticality Systems", In Proceeding: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-2, April 2023. [doi] [Bibtex & Downloads]
Motivating Agent-Based Learning For Bounding Time in Mixed-Criticality Systems
Reference
Behnaz Ranjbar, Ali Hosseinghorban, Akash Kumar, "Motivating Agent-Based Learning For Bounding Time in Mixed-Criticality Systems", In Proceeding: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-2, April 2023. [doi]
Bibtex
@inproceedings{Ranjbar_DATE_2023,
year = 2023,
month = {April},
pages={1-2},
author = {Behnaz Ranjbar and Ali Hosseinghorban and Akash Kumar},
title = {Motivating Agent-Based Learning For Bounding Time in Mixed-Criticality Systems},
booktitle = {Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
doi={10.23919/DATE56975.2023.10137189}
}Downloads
No Downloads available for this publication
Permalink
- 151. Behnaz Ranjbar, Florian Klemme, Paul R. Genssler, Hussam Amrouch, Jinhyo Jung, Shail Dave, Hwisoo So, Kyongwoo Lee, Aviral Shrivastava, Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Francky Catthoor, Dwaipayan Biswas, Akash Kumar, "Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level", In Proceeding: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-10, April 2023. [doi] [Bibtex & Downloads]
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level
Reference
Behnaz Ranjbar, Florian Klemme, Paul R. Genssler, Hussam Amrouch, Jinhyo Jung, Shail Dave, Hwisoo So, Kyongwoo Lee, Aviral Shrivastava, Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Francky Catthoor, Dwaipayan Biswas, Akash Kumar, "Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level", In Proceeding: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-10, April 2023. [doi]
Bibtex
@inproceedings{Ranjbar_SS_DATE_2023,
year = 2023,
month = {April},
pages={1-10},
author = {Behnaz Ranjbar and Florian Klemme and Paul R. Genssler and Hussam Amrouch and Jinhyo Jung and Shail Dave and Hwisoo So and Kyongwoo Lee and Aviral Shrivastava and Ji-Yung Lin and Pieter Weckx and Subrat Mishra and Francky Catthoor and Dwaipayan Biswas and Akash Kumar},
title = {Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level},
booktitle = {Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
doi={10.23919/DATE56975.2023.10137182}
}Downloads
No Downloads available for this publication
Permalink
- 150. Zahra Ebrahimi, Muhammad Zaid, Mark Wijtvliet, Akash Kumar, "RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 712–725, Mar 2023. [doi] [Bibtex & Downloads]
RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency
Reference
Zahra Ebrahimi, Muhammad Zaid, Mark Wijtvliet, Akash Kumar, "RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 712–725, Mar 2023. [doi]
Bibtex
@article{Ebrahimi_2023,
doi = {10.1109/tcad.2022.3184928},
url = {https://doi.org/10.1109%2Ftcad.2022.3184928},
year = 2023,
month = {mar},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {42},
number = {3},
pages = {712--725},
author = {Zahra Ebrahimi and Muhammad Zaid and Mark Wijtvliet and Akash Kumar},
title = {{RAPID}: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
}Downloads
TCAD_RAPID_long_version [PDF]
Permalink
- 149. Shubham Rai, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 914–927, Mar 2023. [doi] [Bibtex & Downloads]
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits
Reference
Shubham Rai, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 914–927, Mar 2023. [doi]
Bibtex
@article{Rai_2023,
doi = {10.1109/tcad.2022.3184633},
url = {https://doi.org/10.1109%2Ftcad.2022.3184633},
year = 2023,
month = {mar},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {42},
number = {3},
pages = {914--927},
author = {Shubham Rai and Alessandro Tempia Calvino and Heinz Riener and Giovanni De Micheli and Akash Kumar},
title = {Utilizing {XMG}-Based Synthesis to Preserve Self-Duality for {RFET}-Based Circuits},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
}Downloads
TCAD_2022 [PDF]
Permalink
- 148. Mehdi Moghaddamfar, Norman May, Christian Färber, Wolfgang Lehner, Akash Kumar, "A Study of Early Aggregation in Database Query Processing on FPGAs", Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ACM, Feb 2023. [doi] [Bibtex & Downloads]
A Study of Early Aggregation in Database Query Processing on FPGAs
Reference
Mehdi Moghaddamfar, Norman May, Christian Färber, Wolfgang Lehner, Akash Kumar, "A Study of Early Aggregation in Database Query Processing on FPGAs", Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ACM, Feb 2023. [doi]
Bibtex
@inproceedings{Moghaddamfar_2023,
doi = {10.1145/3543622.3573194},
url = {https://doi.org/10.1145%2F3543622.3573194},
year = 2023,
month = {feb},
publisher = ,
author = {Mehdi Moghaddamfar and Norman May and Christian Färber and Wolfgang Lehner and Akash Kumar},
title = {A Study of Early Aggregation in Database Query Processing on {FPGAs}},
booktitle = {Proceedings of the 2023 {ACM}/{SIGDA} International Symposium on Field Programmable Gate Arrays}
}Downloads
No Downloads available for this publication
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- 147. Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks", Proceedings of the 28th Asia and South Pacific Design Automation Conference, ACM, Jan 2023. [doi] [Bibtex & Downloads]
SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks
Reference
Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks", Proceedings of the 28th Asia and South Pacific Design Automation Conference, ACM, Jan 2023. [doi]
Bibtex
@inproceedings{Ranjan_2023,
doi = {10.1145/3566097.3567891},
url = {https://doi.org/10.1145%2F3566097.3567891},
year = 2023,
month = {jan},
publisher = ,
author = {Rohit Ranjan and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{SyFAxO}-{GeN}: Synthesizing FPGA-based Approximate Operators with Generative Networks},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference}
}Downloads
No Downloads available for this publication
Permalink
- 146. Paul Jungmann, Jeffrey B. Johnson, Eduardo C. Silva, William Taylor, Abdul Hanan Khan, Akash Kumar, "TCAD-enabled Machine Learning - An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication", In IEEE Transactions on Semiconductor Manufacturing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi] [Bibtex & Downloads]
TCAD-enabled Machine Learning - An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication
Reference
Paul Jungmann, Jeffrey B. Johnson, Eduardo C. Silva, William Taylor, Abdul Hanan Khan, Akash Kumar, "TCAD-enabled Machine Learning - An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication", In IEEE Transactions on Semiconductor Manufacturing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi]
Bibtex
@article{Jungmann_2023,
doi = {10.1109/tsm.2023.3240033},
url = {https://doi.org/10.1109%2Ftsm.2023.3240033},
year = 2023,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Paul Jungmann and Jeffrey B. Johnson and Eduardo C. Silva and William Taylor and Abdul Hanan Khan and Akash Kumar},
title = {{TCAD}-enabled Machine Learning - An Efficient Framework to Build Highly Accurate and Reliable Models for Semiconductor Technology Development and Fabrication},
journal = {{IEEE} Transactions on Semiconductor Manufacturing}
}Downloads
No Downloads available for this publication
Permalink
- 145. Steffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, Akash Kumar, "Formal Analysis of Camouflaged Reconfigurable Circuits" (to appear), Proceedings 21st International NEWCAS Conference, pp. 1–4, 2023. [Bibtex & Downloads]
Formal Analysis of Camouflaged Reconfigurable Circuits
Reference
Steffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, Akash Kumar, "Formal Analysis of Camouflaged Reconfigurable Circuits" (to appear), Proceedings 21st International NEWCAS Conference, pp. 1–4, 2023.
Bibtex
@inproceedings{mrt+23,
author = {M\"arcker, Steffen and Raitza, Michael and Rai, Shubham and Galderisi, Giulio and Mikolajick, Thomas and Trommer, Jens and Kumar, Akash},
title = {Formal Analysis of Camouflaged Reconfigurable Circuits},
year = {2023},
volume = {},
number = {},
pages = {1--4},
booktitle = {Proceedings 21st International NEWCAS Conference}
}Downloads
newcas23-camouflaging [PDF]
Related Paths
Permalink
- 144. Siva Satyendra Sahoo, Anup Das, Akash Kumar, "Fault Tolerant Architectures", Chapter in Handbook of Computer Architecture, Springer Nature Singapore, pp. 1–44, 2023. [doi] [Bibtex & Downloads]
Fault Tolerant Architectures
Reference
Siva Satyendra Sahoo, Anup Das, Akash Kumar, "Fault Tolerant Architectures", Chapter in Handbook of Computer Architecture, Springer Nature Singapore, pp. 1–44, 2023. [doi]
Bibtex
@incollection{Sahoo_2023,
doi = {10.1007/978-981-15-6401-7_11-1},
url = {https://doi.org/10.1007%2F978-981-15-6401-7_11-1},
year = 2023,
publisher = {Springer Nature Singapore},
pages = {1--44},
author = {Siva Satyendra Sahoo and Anup Das and Akash Kumar},
title = {Fault Tolerant Architectures},
booktitle = {Handbook of Computer Architecture}
}Downloads
No Downloads available for this publication
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- 143. Salim Ullah, Akash Kumar, "Approximate Arithmetic Circuit Architectures for FPGA-based Systems", Springer International Publishing, 2023. [doi] [Bibtex & Downloads]
Approximate Arithmetic Circuit Architectures for FPGA-based Systems
Reference
Salim Ullah, Akash Kumar, "Approximate Arithmetic Circuit Architectures for FPGA-based Systems", Springer International Publishing, 2023. [doi]
Bibtex
@book{Ullah_2023,
doi = {10.1007/978-3-031-21294-9},
url = {https://doi.org/10.1007%2F978-3-031-21294-9},
year = 2023,
publisher = {Springer International Publishing},
author = {Salim Ullah and Akash Kumar},
title = {Approximate Arithmetic Circuit Architectures for {FPGA}-based Systems}
}Downloads
No Downloads available for this publication
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- 142. Nima Kavand, Armin Darjani, Jens Trommer, Giulio Galderisi, Thomas Mikolajick, Nicolai Mueller, Amir Moradi, Chongzhou Fang, Ning Miao, Han Wang, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Benjamin Hettwer, Luca Parrini, Akash Kumar, "Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches", Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis, pp. 8–17, 2023. [Bibtex & Downloads]
Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches
Reference
Nima Kavand, Armin Darjani, Jens Trommer, Giulio Galderisi, Thomas Mikolajick, Nicolai Mueller, Amir Moradi, Chongzhou Fang, Ning Miao, Han Wang, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Benjamin Hettwer, Luca Parrini, Akash Kumar, "Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches", Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis, pp. 8–17, 2023.
Bibtex
@inproceedings{kavand2023special,
title={Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches},
author={Kavand, Nima and Darjani, Armin and Trommer, Jens and Galderisi, Giulio and Mikolajick, Thomas and Mueller, Nicolai and Moradi, Amir and Fang, Chongzhou and Miao, Ning and Wang, Han and Pudukotai Dinakarrao, Sai Manoj and Homayoun, Houman and Hettwer, Benjamin and Parrini, Luca and Kumar, Akash},
booktitle={Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis},
pages={8--17},
year={2023}
}Downloads
No Downloads available for this publication
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2022
- 141. Seetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu, "SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 16 August 2022. [doi] [Bibtex & Downloads]
SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation
Reference
Seetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu, "SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 16 August 2022. [doi]
Bibtex
@article{Potluri_2022,
doi = {10.1109/tcad.2022.3199153},
url = {https://doi.org/10.1109%2Ftcad.2022.3199153},
year = 2022,
month={16 August},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Seetal Potluri and Shamik Kundu and Akash Kumar and Kanad Basu and Aydin Aysu},
title = {{SeqL}+: Secure Scan-Obfuscation with Theoretical and Empirical Validation},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
}Downloads
SeqL_Secure_Scan-Obfuscation_with_Theoretical_and_Empirical_Validation [PDF]
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- 140. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi] [Bibtex & Downloads]
NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi]
Bibtex
@INPROCEEDINGS{9974206,
author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
booktitle={2022 International Conference on Field-Programmable Technology (ICFPT)},
title={NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture},
year={2022},
month = {dec},
pages={1-1},
doi={10.1109/ICFPT56656.2022.9974206}}Downloads
NetPU_Prototyping_a_Generic_Reconfigurable_Neural_Network_Accelerator_Architecture [PDF]
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- 139. Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Securing Hardware through Reconfigurable Nano-structures", In Proceeding: International Conference on Computer-Aided Design (ICCAD), ACM/IEEE, Nov 2022. [Bibtex & Downloads]
Securing Hardware through Reconfigurable Nano-structures
Reference
Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Securing Hardware through Reconfigurable Nano-structures", In Proceeding: International Conference on Computer-Aided Design (ICCAD), ACM/IEEE, Nov 2022.
Bibtex
@inproceedings{Kavand_ICCAD,
year = 2022,
month = {nov},
publisher = ,
author = {Nima Kavand and Armin Darjani and Shubham Rai and Akash Kumar},
title = {Securing Hardware through Reconfigurable Nano-structures},
booktitle = {International Conference on Computer-Aided Design ({ICCAD})}
}Downloads
ICCAD_2022_Special_Session [PDF]
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- 138. Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 10, pp. 3239-3251, October 2022. [doi] [Bibtex & Downloads]
BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems
Reference
Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 10, pp. 3239-3251, October 2022. [doi]
Bibtex
@article{Ranjbar_2022_tcad,
year = 2022,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
month ={October},
author = {Behnaz Ranjbar and Ali Hosseinghorban and Siva Satyendra Sahoo and Alireza Ejlali and Akash Kumar},
title = {BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
year={2022},
volume={41},
number={10},
pages={3239-3251},
doi={10.1109/TCAD.2021.3127867}
}Downloads
Behnaz_TCAD_DATE2021_Extension_Camera_ready [PDF]
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- 137. Mozhgan Navardi, Behnaz Ranjbar, Nezam Rohbani, Alireza Ejlali, Akash Kumar, "Peak-Power Aware Life-time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems", In IEEE Open Journal of Circuits and Systems, vol. 3, pp. 199-215, September 2022. [doi] [Bibtex & Downloads]
Peak-Power Aware Life-time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems
Reference
Mozhgan Navardi, Behnaz Ranjbar, Nezam Rohbani, Alireza Ejlali, Akash Kumar, "Peak-Power Aware Life-time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems", In IEEE Open Journal of Circuits and Systems, vol. 3, pp. 199-215, September 2022. [doi]
Bibtex
@ARTICLE{9896164,
author={Navardi, Mozhgan and Ranjbar, Behnaz and Rohbani, Nezam and Ejlali, Alireza and Kumar, Akash},
journal={IEEE Open Journal of Circuits and Systems},
title={Peak-Power Aware Life-time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems},
year={2022},
month={September},
volume={3},
number={},
pages={199-215},
doi={10.1109/OJCAS.2022.3207598}}Downloads
OJCAS2022-ACCEPTED [PDF]
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- 136. Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, "ERMES: Efficient Racetrack Memory Emulation System based on FPGA", In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022. [Bibtex & Downloads]
ERMES: Efficient Racetrack Memory Emulation System based on FPGA
Reference
Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, "ERMES: Efficient Racetrack Memory Emulation System based on FPGA", In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022.
Bibtex
@INPROCEEDINGS{ERMES,
author={Fanny Spagnolo and Salim Ullah and Pasquale Corsonello and Akash Kumar},
booktitle={2022 International Conference on Field-Programmable Logic and Applications (FPL)},
title={ERMES: Efficient Racetrack Memory Emulation System based on FPGA},
year={2022},
month={aug},
volume={},
number={},
pages={1-6}
}Downloads
RTM_Emulator_FPL [PDF]
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- 135. Mohammed Bawatna, Behnaz Ranjbar, Akash Kumar, "A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 181-188, Aug 2022. [doi] [Bibtex & Downloads]
A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems
Reference
Mohammed Bawatna, Behnaz Ranjbar, Akash Kumar, "A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 181-188, Aug 2022. [doi]
Bibtex
@InProceedings{medo_dsd22,
author = {Mohammed Bawatna and Behnaz Ranjbar and Akash Kumar},
title = {A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems},
booktitle = { Euromicro Conference on Digital System Design (DSD)},
year = {2022},
month = {Aug},
pages={181-188},
doi={10.1109/DSD57027.2022.00033}
}Downloads
No Downloads available for this publication
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- 134. Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022. [Bibtex & Downloads]
PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML
Reference
Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022.
Bibtex
@InProceedings{posax,
author = {Amritha Immaneni and Salim Ullah and Suresh Nambi and Siva Satyendra Sahoo and Akash Kumar},
title = {PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML},
booktitle = {Euromicro Conference on Digital System Design (DSD)},
year = {2022},
month = {Aug},
pages={1-6},
}Downloads
PosAx_O [PDF]
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- 133. Nishant Gupta, Mohil Desai, Mark Wijtvliet, Shubham Rai, Akash Kumar, "DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,", In Proceeding: 2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear), pp. 1-6, 7/2022. [Bibtex & Downloads]
DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,
Reference
Nishant Gupta, Mohil Desai, Mark Wijtvliet, Shubham Rai, Akash Kumar, "DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,", In Proceeding: 2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear), pp. 1-6, 7/2022.
Bibtex
@INPROCEEDINGS{dac-2022-delta,
author={Gupta, Nishant and Desai, Mohil and Wijtvliet, Mark and Rai, Shubham and Kumar, Akash},
booktitle={2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear)},
title={DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,},
year={2022},
month=7,
pages={1-6}
}Downloads
Nishant_Trojan-1 [PDF]
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- 132. Max Sponner, Bernd Waschneck, Akash Kumar, "AI-Driven Performance Modeling for AI Inference Workloads", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 15, pp. 7, Jul 2022. [doi] [Bibtex & Downloads]
AI-Driven Performance Modeling for AI Inference Workloads
Reference
Max Sponner, Bernd Waschneck, Akash Kumar, "AI-Driven Performance Modeling for AI Inference Workloads", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 15, pp. 7, Jul 2022. [doi]
Bibtex
@article{Sponner_2022,
doi = {10.3390/electronics11152316},
url = {https://doi.org/10.3390/electronics11152316},
year = 2022,
month = {jul},
publisher = {{MDPI} {AG}},
volume = {11},
number = {15},
pages = {7},
author = {Max Sponner and Bernd Waschneck and Akash Kumar},
title = {AI-Driven Performance Modeling for AI Inference Workloads},
journal = {Journal of Low Power Electronics and Applications}
}Downloads
electronics-11-02316 [PDF]
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- 131. Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu, "SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture", In Proceeding: 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2022. [doi] [Bibtex & Downloads]
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture
Reference
Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu, "SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture", In Proceeding: 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2022. [doi]
Bibtex
@inproceedings{Rangarajan_2022,
doi = {10.1109/isvlsi54635.2022.00067},
url = {https://doi.org/10.1109%2Fisvlsi54635.2022.00067},
year = 2022,
month = {jul},
publisher = ,
author = {Nikhil Rangarajan and Satwik Patnaik and Mohammed Nabeel and Mohammed Ashraf and Shubham Rai and Gopal Raut and Heba Abunahla and Baker Mohammad and Santosh Kumar Vishvakarma and Akash Kumar and Johann Knechtel and Ozgur Sinanoglu},
title = {{SCRAMBLE}: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture},
booktitle = {2022 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
}Downloads
No Downloads available for this publication
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- 130. Armin Darjani, Nima Kavand, Shubham Rai, Mark Wijtvliet, Akash Kumar, "ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks", In Proceeding: ACM Great Lakes Symposium on VLSI (GLSVLSI), 6/2022. [doi] [Bibtex & Downloads]
ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks
Reference
Armin Darjani, Nima Kavand, Shubham Rai, Mark Wijtvliet, Akash Kumar, "ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks", In Proceeding: ACM Great Lakes Symposium on VLSI (GLSVLSI), 6/2022. [doi]
Bibtex
@INPROCEEDINGS{DARJANI2022,
author = {Armin Darjani and Nima Kavand and Shubham Rai and Mark Wijtvliet and Akash Kumar},
title = {ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks},
booktitle={ACM Great Lakes Symposium on VLSI (GLSVLSI)},
doi = {10.1145/3526241.3530371},
year = 2022,
month = 6
}Downloads
author-prepared-GLSVLSI_2022_ArminDarjani [PDF]
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- 129. Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), vol. 39, no. 3, pp. 73–81, Jun 2022. [doi] [Bibtex & Downloads]
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy
Reference
Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), vol. 39, no. 3, pp. 73–81, Jun 2022. [doi]
Bibtex
@article{Lohana_2022,
doi = {10.1109/mdat.2021.3063373},
url = {https://doi.org/10.1109%2Fmdat.2021.3063373},
year = 2022,
month = {jun},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {39},
number = {3},
pages = {73--81},
author = {Aditya Lohana and Ansh Rupani and Shubham Rai and Akash Kumar},
title = {Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy},
journal = {{IEEE} Design {\&} Test}
}Downloads
DandT [PDF]
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- 128. Behnaz Ranjbar, Hamidreza Alikhani, Bardia Safaei, Alireza Ejlali, Akash Kumar, "Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems", In Computers, vol. 11, no. 7, June 2022. [doi] [Bibtex & Downloads]
Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems
Reference
Behnaz Ranjbar, Hamidreza Alikhani, Bardia Safaei, Alireza Ejlali, Akash Kumar, "Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems", In Computers, vol. 11, no. 7, June 2022. [doi]
Bibtex
@Article{computers11070101,
AUTHOR = {Ranjbar, Behnaz and Alikhani, Hamidreza and Safaei, Bardia and Ejlali, Alireza and Kumar, Akash},
TITLE = {Learning-Oriented QoS- and Drop-Aware Task Scheduling for Mixed-Criticality Systems},
JOURNAL = {Computers},
VOLUME = {11},
YEAR = {2022},
NUMBER = {7},
MONTH = {June},
ARTICLE-NUMBER = {101},
URL = {https://www.mdpi.com/2073-431X/11/7/101},
ISSN = {2073-431X},
DOI = {10.3390/computers11070101}
}Downloads
No Downloads available for this publication
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- 127. Behnaz Ranjbar, Ali Hosseinghorban, Mohammad Salehi, Alireza Ejlali, Akash Kumar, "Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 5, pp. 1509-1522, May 2022. [doi] [Bibtex & Downloads]
Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems
Reference
Behnaz Ranjbar, Ali Hosseinghorban, Mohammad Salehi, Alireza Ejlali, Akash Kumar, "Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 5, pp. 1509-1522, May 2022. [doi]
Bibtex
@article{Ranjbar_2021,
doi = {10.1109/tcad.2021.3082495},
url = {https://doi.org/10.1109%2Ftcad.2021.3082495},
year = 2022,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
month = May,
volume={41},
number={5},
pages={1509-1522},
author = {Behnaz Ranjbar and Ali Hosseinghorban and Mohammad Salehi and Alireza Ejlali and Akash Kumar},
title = {Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}
}Downloads
Tree-PPMFTMCS- Arxiv [PDF]
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- 126. T. Mikolajick, G. Galderisi, S. Rai, M. Simon, R. Böckle, M. Sistani, C. Cakirlar, N. Bhattacharjee, T. Mauersberger, A. Heinzig, A. Kumar, W.M. Weber, J. Trommer, "Reconfigurable Field Effect Transistors: A Technology Enablers Perspective", In Solid-State Electronics, Elsevier BV, pp. 108381, May 2022. [doi] [Bibtex & Downloads]
Reconfigurable Field Effect Transistors: A Technology Enablers Perspective
Reference
T. Mikolajick, G. Galderisi, S. Rai, M. Simon, R. Böckle, M. Sistani, C. Cakirlar, N. Bhattacharjee, T. Mauersberger, A. Heinzig, A. Kumar, W.M. Weber, J. Trommer, "Reconfigurable Field Effect Transistors: A Technology Enablers Perspective", In Solid-State Electronics, Elsevier BV, pp. 108381, May 2022. [doi]
Bibtex
@article{Mikolajick_2022,
doi = {10.1016/j.sse.2022.108381},
url = {https://doi.org/10.1016%2Fj.sse.2022.108381},
year = 2022,
month = {may},
publisher = {Elsevier {BV}},
pages = {108381},
author = {T. Mikolajick and G. Galderisi and S. Rai and M. Simon and R. Böckle and M. Sistani and C. Cakirlar and N. Bhattacharjee and T. Mauersberger and A. Heinzig and A. Kumar and W.M. Weber and J. Trommer},
title = {Reconfigurable Field Effect Transistors: A Technology Enablers Perspective},
journal = {Solid-State Electronics}
}Downloads
SSE_Review_Full_Version [PDF]
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- 125. Mehdi Moghaddamfar, Christian Farber, Norman May, Wolfgang Lehner, Akash Kumar, "FPGA-Based Database Query Processing on Arbitrarily Wide Tables", In Proceeding: 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, May 2022. [doi] [Bibtex & Downloads]
FPGA-Based Database Query Processing on Arbitrarily Wide Tables
Reference
Mehdi Moghaddamfar, Christian Farber, Norman May, Wolfgang Lehner, Akash Kumar, "FPGA-Based Database Query Processing on Arbitrarily Wide Tables", In Proceeding: 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, May 2022. [doi]
Bibtex
@inproceedings{Moghaddamfar_2022, title={FPGA-Based Database Query Processing on Arbitrarily Wide Tables}, url={http://dx.doi.org/10.1109/fccm53951.2022.9786091}, DOI={10.1109/fccm53951.2022.9786091}, booktitle={2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Moghaddamfar, Mehdi and Farber, Christian and May, Norman and Lehner, Wolfgang and Kumar, Akash}, year={2022}, month=may }Downloads
No Downloads available for this publication
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- 124. Zahra Ebrahimi, Dennis Klar, Mohammad Aasim Ekhtiyar, Akash Kumar, "Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider" (to appear), In ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), vol. 27, no. 2, pp. 1–33, Mar 2022. [doi] [Bibtex & Downloads]
Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider
Reference
Zahra Ebrahimi, Dennis Klar, Mohammad Aasim Ekhtiyar, Akash Kumar, "Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider" (to appear), In ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), vol. 27, no. 2, pp. 1–33, Mar 2022. [doi]
Bibtex
@article{Ebrahimi_2022,
doi = {10.1145/3486616},
url = {https://doi.org/10.1145%2F3486616},
year = 2022,
month = {mar},
publisher = {Association for Computing Machinery ({ACM})},
volume = {27},
number = {2},
pages = {1--33},
author = {Zahra Ebrahimi and Dennis Klar and Mohammad Aasim Ekhtiyar and Akash Kumar},
title = {Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient {SIMD} Soft Multiplier-divider},
journal = {{ACM} Transactions on Design Automation of Electronic Systems}
}Downloads
zahra_plasticine_todaes [PDF]
Related Paths
other
Permalink
- 123. M. Thümmler, S. Rai, A. Kumar, "Improving Technology Mapping for And-Inverter-Cones", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), March 2022. [Bibtex & Downloads]
Improving Technology Mapping for And-Inverter-Cones
Reference
M. Thümmler, S. Rai, A. Kumar, "Improving Technology Mapping for And-Inverter-Cones", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), March 2022.
Bibtex
@InProceedings{Thuemmler2022,
Title = {Improving Technology Mapping for And-Inverter-Cones},
Author = {M. Th{\"{u}}mmler and S. Rai and A. Kumar},
Booktitle = {2022 Design, Automation Test in Europe Conference Exhibition (DATE)},
Year = {2022},
Month = {March},
Owner = {shubham},
Timestamp = {2018.04.26}
}Downloads
Martin_thuemmler_AIC(1) [PDF]
Permalink
- 122. Michael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar, "Exploring Standard-Cell Designs for Reconfigurable
Nanotechnologies: A Formal Approach", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2022. [Bibtex & Downloads]
Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach
Reference
Michael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar, "Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2022.
Bibtex
@INPROCEEDINGS{9474132,
author={Raitza, Michael and M{\"a}rcker, Steffen and Rai, Shubham and Kumar, Akash},
booktitle={2022 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={Exploring Standard-Cell Designs for Reconfigurable
Nanotechnologies: A Formal Approach},
year={2022},
month = mar,
volume={},
number={}
}Downloads
DATE_SS_2022 [PDF]
Permalink
- 121. Ali Hosseinghorban, Akash Kumar, "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications", In Electronics, vol. 11, Mar 2022. [doi] [Bibtex & Downloads]
A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications
Reference
Ali Hosseinghorban, Akash Kumar, "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications", In Electronics, vol. 11, Mar 2022. [doi]
Bibtex
@Article{ali-mdpi-electronics-2022,
AUTHOR = {Hosseinghorban, Ali and Kumar, Akash},
TITLE = {A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications},
JOURNAL = {Electronics},
VOLUME = {11},
YEAR = {2022},
month={mar},
ARTICLE-NUMBER = {978},
URL = {https://www.mdpi.com/2079-9292/11/7/978},
ISSN = {2079-9292},
DOI = {10.3390/electronics11070978}
}Downloads
LTE_on_Chip_MDPI-author-prepared [PDF]
Permalink
- 120. Stefano Corda, Bram Veenboer, Ahsan Javed Awan, John W. Romein, Roel Jordans, Akash Kumar, Albert-Jan Boonstra, Henk Corporaal, "Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 10, pp. 22819–22843, 2022. [doi] [Bibtex & Downloads]
Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware
Reference
Stefano Corda, Bram Veenboer, Ahsan Javed Awan, John W. Romein, Roel Jordans, Akash Kumar, Albert-Jan Boonstra, Henk Corporaal, "Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 10, pp. 22819–22843, 2022. [doi]
Bibtex
@article{Corda_2022,
doi = {10.1109/access.2022.3150861},
url = {https://doi.org/10.1109%2Faccess.2022.3150861},
year = 2022,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {10},
pages = {22819--22843},
author = {Stefano Corda and Bram Veenboer and Ahsan Javed Awan and John W. Romein and Roel Jordans and Akash Kumar and Albert-Jan Boonstra and Henk Corporaal},
title = {Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware},
journal = {{IEEE} Access}
}Downloads
IEEE-Access-final-version-Stefano [PDF]
Permalink
- 119. Negar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar, "Multi-Precision Deep Neural Network Acceleration on FPGAs" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022. [Bibtex & Downloads]
Multi-Precision Deep Neural Network Acceleration on FPGAs
Reference
Negar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar, "Multi-Precision Deep Neural Network Acceleration on FPGAs" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022.
Bibtex
@InProceedings{mehdi_2022_aspdac,
author = {Negar Neda and Salim Ullah and Azam Ghanbari and Hoda Mahdiani and Mehdi Modarressi and Akash Kumar},
booktitle = {Asia and South Pacific Design Automation Conference (ASPDAC)},
title = {Multi-Precision Deep Neural Network Acceleration on {FPGAs}},
year = {2022},
month=1,
organization = {IEEE},
}Downloads
No Downloads available for this publication
Permalink
- 118. Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli, "A Versatile Mapping Approach for Technology Mapping and Graph Optimization" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022. [Bibtex & Downloads]
A Versatile Mapping Approach for Technology Mapping and Graph Optimization
Reference
Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli, "A Versatile Mapping Approach for Technology Mapping and Graph Optimization" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022.
Bibtex
@InProceedings{alessandro_2022_aspdac,
author = {Alessandro Tempia Calvino and Heinz Riener and Shubham Rai and Akash Kumar and Giovanni De Micheli},
booktitle = {Asia and South Pacific Design Automation Conference (ASPDAC)},
title = {A Versatile Mapping Approach for Technology Mapping and Graph Optimization},
year = {2022},
month = {1},
organization = {IEEE},
}Downloads
ASP_DAC22 [PDF]
Permalink
- 117. Mark Wijtvliet, Akash Kumar, Henk Corporaal, "Blocks: challenging SIMDs and VLIWs with a reconfigurable architecture", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–14, 1/2022. [doi] [Bibtex & Downloads]
Blocks: challenging SIMDs and VLIWs with a reconfigurable architecture
Reference
Mark Wijtvliet, Akash Kumar, Henk Corporaal, "Blocks: challenging SIMDs and VLIWs with a reconfigurable architecture", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–14, 1/2022. [doi]
Bibtex
@article{mark-tcad-2021,
doi = {10.1109/tcad.2021.3120541},
url = {https://doi.org/10.1109%2Ftcad.2021.3120541},
year = 2022,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--14},
month = 1,
author = {Mark Wijtvliet and Akash Kumar and Henk Corporaal},
title = {Blocks: challenging {SIMDs} and {VLIWs} with a reconfigurable architecture},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
}Downloads
TCAD3120541 [PDF]
Permalink
- 116. Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022. [Bibtex & Downloads]
AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems
Reference
Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022.
Bibtex
@article{ullah2022appaxo,
title={AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems},
author={Ullah, Salim and Sahoo, Siva Satyendra and Ahmed, Nemath and Chaudhury, Debabrata and Kumar, Akash},
journal={ACM Transactions on Embedded Computing Systems (TECS)},
volume={},
number={},
pages={1--31},
year={2022},
month={January}
}Downloads
AppAxO [PDF]
Permalink
- 115. Mark Wijtvliet, Henk Corporaal, Akash Kumar, "Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures", Springer International Publishing, 2022. [doi] [Bibtex & Downloads]
Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures
Reference
Mark Wijtvliet, Henk Corporaal, Akash Kumar, "Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures", Springer International Publishing, 2022. [doi]
Bibtex
@book{Wijtvliet_2022,
doi = {10.1007/978-3-030-79774-4},
url = {https://doi.org/10.1007%2F978-3-030-79774-4},
year = 2022,
publisher = {Springer International Publishing},
author = {Mark Wijtvliet and Henk Corporaal and Akash Kumar},
title = {Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures}
}Downloads
No Downloads available for this publication
Permalink
- 114. Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi] [Bibtex & Downloads]
END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator
Reference
Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi]
Bibtex
@incollection{Rai_2022,
doi = {10.1007/978-3-031-16818-5_9},
url = {https://doi.org/10.1007%2F978-3-031-16818-5_9},
year = 2022,
publisher = {Springer Nature Switzerland},
pages = {175--203},
author = {Shubham Rai and Nishant Gupta and Abhiroop Bhattacharjee and Ansh Rupani and Michael Raitza and Jens Trommer and Thomas Mikolajick and Akash Kumar},
title = {{END}-{TRUE}: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator},
booktitle = {{VLSI}-{SoC}: Technology Advancement on {SoC} Design}
}Downloads
No Downloads available for this publication
Permalink
- 113. Cecilia De la Parra, Taha Soliman, Andre Guntoro, Akash Kumar, Norbert Wehn, "Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation" (to appear), In IEEE Micro, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2022. [doi] [Bibtex & Downloads]
Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation
Reference
Cecilia De la Parra, Taha Soliman, Andre Guntoro, Akash Kumar, Norbert Wehn, "Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation" (to appear), In IEEE Micro, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2022. [doi]
Bibtex
@article{Cecilia_micro22,
doi = {MicroSI-2022-03-0032},
url = {https://cfaed.tu-dresden.de/cpd-publications},
year = 2022,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Cecilia De la Parra and Taha Soliman and Andre Guntoro and Akash Kumar and Norbert Wehn},
title = {Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation},
journal = {{IEEE} Micro}
}Downloads
IEEE_MICRO_camera_ready [PDF]
Permalink
- 112. Jorge Navarro Quijada, Tim Baldauf, Shubham Rai, Andre Heinzig, Akash Kumar, Walter M. Weber, Thomas Mikolajick, Jens Trommer, "A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation", In IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–8, 2022. [doi] [Bibtex & Downloads]
A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation
Reference
Jorge Navarro Quijada, Tim Baldauf, Shubham Rai, Andre Heinzig, Akash Kumar, Walter M. Weber, Thomas Mikolajick, Jens Trommer, "A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation", In IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–8, 2022. [doi]
Bibtex
@article{Quijada_2022,
doi = {10.1109/tnano.2022.3221836},
url = {https://doi.org/10.1109%2Ftnano.2022.3221836},
year = 2022,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--8},
author = {Jorge Navarro Quijada and Tim Baldauf and Shubham Rai and Andre Heinzig and Akash Kumar and Walter M. Weber and Thomas Mikolajick and Jens Trommer},
title = {A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation},
journal = {{IEEE} Transactions on Nanotechnology}
}Downloads
GeNW_RFET_VerilogA-TNANO [PDF]
Permalink
2021
- 111. Najdet Charaf, Christoph Tietz, Michael Raitza, Akash Kumar, Diana Gohringer, "AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs", In Proceeding: 2021 International Conference on Field-Programmable Technology (ICFPT), IEEE, Dec 2021. [doi] [Bibtex & Downloads]
AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs
Reference
Najdet Charaf, Christoph Tietz, Michael Raitza, Akash Kumar, Diana Gohringer, "AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs", In Proceeding: 2021 International Conference on Field-Programmable Technology (ICFPT), IEEE, Dec 2021. [doi]
Bibtex
@inproceedings{Charaf_2021,
doi = {10.1109/icfpt52863.2021.9609948},
url = {https://doi.org/10.1109%2Ficfpt52863.2021.9609948},
year = 2021,
month = {dec},
publisher = ,
author = {Najdet Charaf and Christoph Tietz and Michael Raitza and Akash Kumar and Diana Gohringer},
title = {{AMAH}-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on {FPGAs}},
booktitle = {2021 International Conference on Field-Programmable Technology ({ICFPT})}
}Downloads
FPT-2021-AMAH-Flex_A_Modular_and_Highly_Flexible_Tool_for_Generating_Relocatable_Systems_on_FPGAs [PDF]
Permalink
- 110. T. Mikolajick, G. Galderisi, M. Simon, S. Rai, A. Kumar, A. Heinzig, W.M. Weber, J. Trommer, "20 Years of reconfigurable field-effect transistors: From concepts to future applications", In Solid-State Electronics, Elsevier BV, vol. 186, pp. 108036, Dec 2021. [doi] [Bibtex & Downloads]
20 Years of reconfigurable field-effect transistors: From concepts to future applications
Reference
T. Mikolajick, G. Galderisi, M. Simon, S. Rai, A. Kumar, A. Heinzig, W.M. Weber, J. Trommer, "20 Years of reconfigurable field-effect transistors: From concepts to future applications", In Solid-State Electronics, Elsevier BV, vol. 186, pp. 108036, Dec 2021. [doi]
Bibtex
@article{Mikolajick_2021,
doi = {10.1016/j.sse.2021.108036},
url = {https://doi.org/10.1016%2Fj.sse.2021.108036},
year = 2021,
month = {dec},
publisher = {Elsevier {BV}},
volume = {186},
pages = {108036},
author = {T. Mikolajick and G. Galderisi and M. Simon and S. Rai and A. Kumar and A. Heinzig and W.M. Weber and J. Trommer},
title = {20 Years of reconfigurable field-effect transistors: From concepts to future applications},
journal = {Solid-State Electronics}
}Downloads
Solid_state_electronics_2021 [PDF]
Permalink
- 109. Elias Trommer, Bernd Waschneck, Akash Kumar, "dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021. [Bibtex & Downloads]
dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference
Reference
Elias Trommer, Bernd Waschneck, Akash Kumar, "dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021.
Bibtex
@INPROCEEDINGS{Trommer2021,
author={Trommer, Elias and Waschneck, Bernd and Kumar, Akash},
booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
title={dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference},
month={Nov},
year={2021},
volume={},
number={}}Downloads
No Downloads available for this publication
Permalink
- 108. Andreas Krinke, Shubham Rai, Akash Kumar, Jens Lienig, "Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021. [Bibtex & Downloads]
Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies
Reference
Andreas Krinke, Shubham Rai, Akash Kumar, Jens Lienig, "Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021.
Bibtex
@INPROCEEDINGS{krinke2021,
author={Krinke, Andreas and Rai, Shubham and Kumar, Akash and Lienig, Jens},
booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
title={Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies},
month={Nov},
year={2021},
volume={},
number={}}Downloads
iccad_2021_2 [PDF]
Permalink
- 107. Yasasvi V. Peruvemba, Shubham Rai, Kapil Ahuja, Akash Kumar, "RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021. [Bibtex & Downloads]
RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis
Reference
Yasasvi V. Peruvemba, Shubham Rai, Kapil Ahuja, Akash Kumar, "RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021.
Bibtex
@INPROCEEDINGS{peruvemba2021,
author={Peruvemba, Yasasvi V. and Rai, Shubham and Ahuja, Kapil and Kumar, Akash},
booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
title={RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis},
month={Nov},
year={2021},
volume={},
number={}}Downloads
101_Final_ICCAD_Paper (1) [PDF]
Permalink
- 106. Siva Satyendra Sahoo, Akash Kumar, "Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. [Bibtex & Downloads]
Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems
Reference
Siva Satyendra Sahoo, Akash Kumar, "Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021.
Bibtex
@INPROCEEDINGS{siva-vlsisoc2021-mctsclr,
author={Siva Satyendra Sahoo and Akash Kumar},
booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC)},
title={Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems},
year={2021},
month={Oct},
volume={},
number={}}Downloads
MCTS_CLRIntegTMap [PDF]
Permalink
- 105. Siva Satyendra Sahoo, Akash Kumar, "CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. [Bibtex & Downloads]
CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems
Reference
Siva Satyendra Sahoo, Akash Kumar, "CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021.
Bibtex
@INPROCEEDINGS{siva-vlsisoc2021-cleocode,
author={Siva Satyendra Sahoo and Akash Kumar},
booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC)},
title={CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems},
year={2021},
month={Oct},
volume={},
number={}}Downloads
CLEOCoDe [PDF]
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- 104. Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi] [Bibtex & Downloads]
Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput
Reference
Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi]
Bibtex
@inproceedings{Bhattacharjee_2021,
doi = {10.1109/vlsi-soc53125.2021.9607015},
url = {https://doi.org/10.1109%2Fvlsi-soc53125.2021.9607015},
year = 2021,
month = {oct},
publisher = ,
author = {Abhiroop Bhattacharjee and Shubham Rai and Ansh Rupani and Michael Raitza and Akash Kumar},
title = {Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput},
booktitle = {2021 {IFIP}/{IEEE} 29th International Conference on Very Large Scale Integration ({VLSI}-{SoC})}
}Downloads
VLSI-SOC_2021 [PDF]
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- 103. Behnaz Ranjbar, Tuan D. A. Nguyen, Alireza Ejlali, Akash Kumar, "Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 40, no. 10, pp. 2009-2023, October 2021. [doi] [Bibtex & Downloads]
Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform
Reference
Behnaz Ranjbar, Tuan D. A. Nguyen, Alireza Ejlali, Akash Kumar, "Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 40, no. 10, pp. 2009-2023, October 2021. [doi]
Bibtex
@article{Ranjbar_2020,
doi = {10.1109/tcad.2020.3033374},
url = {https://doi.org/10.1109%2Ftcad.2020.3033374},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {2009-2023},
volume={40},
number={10},
month ={October},
author = {Behnaz Ranjbar and Tuan D. A. Nguyen and Alireza Ejlali and Akash Kumar},
title = {Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}
}Downloads
TCAD3033374-power-aware-accepted [PDF]
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- 102. Stefano Corda, Madhurya Kumaraswamy, Ahsan Javed Awan, Roel Jordans, Akash Kumar, Henk Corporaal, "NMPO: Near-Memory Computing Profiling and Offloading", In Proceeding: 2021 24th Euromicro Conference on Digital System Design (DSD), IEEE, Sep 2021. [doi] [Bibtex & Downloads]
NMPO: Near-Memory Computing Profiling and Offloading
Reference
Stefano Corda, Madhurya Kumaraswamy, Ahsan Javed Awan, Roel Jordans, Akash Kumar, Henk Corporaal, "NMPO: Near-Memory Computing Profiling and Offloading", In Proceeding: 2021 24th Euromicro Conference on Digital System Design (DSD), IEEE, Sep 2021. [doi]
Bibtex
@inproceedings{Corda_2021,
doi = {10.1109/dsd53832.2021.00048},
url = {https://doi.org/10.1109%2Fdsd53832.2021.00048},
year = 2021,
month = {sep},
publisher = ,
author = {Stefano Corda and Madhurya Kumaraswamy and Ahsan Javed Awan and Roel Jordans and Akash Kumar and Henk Corporaal},
title = {{NMPO}: Near-Memory Computing Profiling and Offloading},
booktitle = {2021 24th Euromicro Conference on Digital System Design ({DSD})}
}Downloads
No Downloads available for this publication
Permalink
- 101. Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel C. B. Wong, Geoff V. Merrett, Yinyuan Zhao, Jiachen Wang, Xiaohang Wang, Amit Kumar Singh, "Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives", Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis, ACM, Sep 2021. [doi] [Bibtex & Downloads]
Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives
Reference
Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel C. B. Wong, Geoff V. Merrett, Yinyuan Zhao, Jiachen Wang, Xiaohang Wang, Amit Kumar Singh, "Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives", Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis, ACM, Sep 2021. [doi]
Abstract
Modern embedded systems need to cater for several needs depending upon the application domain in which they are deployed. For example, mixed-critically needs to be considered for real-time and safety-critical systems and energy for battery-operated systems. At the same time, many of these systems demand for their reliability and security as well. With electronic systems being used for increasingly varying type of applications, novel challenges have emerged. For example, with the use of embedded systems in increasingly complex applications that execute tasks with varying priorities, mixed-criticality systems present unique challenges to designing reliable systems. The large design space involved in implementing cross-layer reliability in heterogeneous systems, particularly for mixed-critical systems, poses new research problems. Further, malicious security attacks on these systems pose additional extraordinary challenges in the system design. In this paper, we cover both the industry and academia perspectives of the challenges posed by these emergent aspects of system design towards designing high-performance, energy-efficient, reliable and/or secure embedded systems. We also provide our views on paths forward.
Bibtex
@inproceedings{Sahoo_2021,
doi = {10.1145/3478684.3479246},
url = {https://doi.org/10.1145%2F3478684.3479246},
year = 2021,
month = {sep},
publisher = ,
author = {Siva Satyendra Sahoo and Akash Kumar and Martin Decky and Samuel C. B. Wong and Geoff V. Merrett and Yinyuan Zhao and Jiachen Wang and Xiaohang Wang and Amit Kumar Singh},
title = {Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives},
booktitle = {Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis}
}Downloads
ESWEEK_2021_SS [PDF]
Related Paths
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- 100. Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi] [Bibtex & Downloads]
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
Reference
Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi]
Bibtex
@article{Nambi_2021,
doi = {10.1109/access.2021.3098730},
url = {https://doi.org/10.1109%2Faccess.2021.3098730},
year = 2021,
month = {July},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Suresh Nambi and Salim Ullah and Siva Satyendra Sahoo and Aditya Lohana and Farhad Merchant and Akash Kumar},
title = {{ExPAN}(N)D: Exploring Posits for Efficient Artificial Neural Network Design in {FPGA}-based Systems},
journal = {{IEEE} Access}
}Downloads
ExPANND_Exploring_Posits_for_Efficient_Artificial_Neural_Network_Design_in_FPGA-based_Systems [PDF]
Related Paths
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- 99. Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 9, pp. 91564–91574, 2021. [doi] [Bibtex & Downloads]
A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies
Reference
Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 9, pp. 91564–91574, 2021. [doi]
Bibtex
@article{Rai_2021,
doi = {10.1109/access.2021.3092167},
url = {https://doi.org/10.1109%2Faccess.2021.3092167},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {9},
pages = {91564--91574},
author = {Shubham Rai and Pallab Nath and Ansh Rupani and Santosh Kumar Vishvakarma and Akash Kumar},
title = {A Survey of {FPGA} Logic Cell Designs in the Light of Emerging Technologies},
journal = {{IEEE} Access}
}Downloads
survey_FPGA_IEEE_access [PDF]
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- 98. S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021. [Bibtex & Downloads]
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems
Reference
S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021.
Bibtex
@INPROCEEDINGS{clapped,
author={S. {Ullah} and S. S. {Sahoo} and A. {Kumar}},
booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)},
title={CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems},
year={2021},
month={jul},
volume={},
number={},
pages={1-6}
}Downloads
CLAppED_A_Design_Framework_for_Implementing_Cross-Layer_Approximation_in_FPGA-based_Embedded_Systems [PDF]
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- 97. Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi] [Bibtex & Downloads]
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
Reference
Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi]
Bibtex
@article{Ullah_2021,
doi = {10.1109/les.2020.2995053},
url = {https://doi.org/10.1109%2Fles.2020.2995053},
year = 2021,
month = {jun},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {13},
number = {2},
pages = {41--44},
author = {Salim Ullah and Tuan Duy Anh Nguyen and Akash Kumar},
title = {Energy-Efficient Low-Latency Signed Multiplier for {FPGA}-Based Hardware Accelerators},
journal = {{IEEE} Embedded Systems Letters}
}Downloads
ESL_acc_multiplier [PDF]
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- 96. Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi] [Bibtex & Downloads]
MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems
Reference
Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi]
Bibtex
@inproceedings{10.1145/3453688.3461533,
author = {Sahoo, Siva Satyendra and Baranwal, Akhil Raj and Ullah, Salim and Kumar, Akash},
title = {MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems},
year = {2021},
month={June},
isbn = {9781450383936},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3453688.3461533},
doi = {10.1145/3453688.3461533},
pages = {339–346},
numpages = {8},
keywords = {memory-centric computing, fpga, energy-efficient computing, high-level synthesis, hardware accelerators},
location = {Virtual Event, USA},
series = {GLSVLSI '21}
}Downloads
No Downloads available for this publication
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- 95. Mark Wijtvliet, Akash Kumar, Henk Corporaal, "CGRA-EAM - Rapid energy and area estimation for coarse-grained reconfigurable architectures" (to appear), ACM, New York, NY, USA, June 2021. [Bibtex & Downloads]
CGRA-EAM - Rapid energy and area estimation for coarse-grained reconfigurable architectures
Reference
Mark Wijtvliet, Akash Kumar, Henk Corporaal, "CGRA-EAM - Rapid energy and area estimation for coarse-grained reconfigurable architectures" (to appear), ACM, New York, NY, USA, June 2021.
Bibtex
@article{wijtvliet_trets,
author={Wijtvliet, Mark and Kumar, Akash and Corporaal, Henk},
booktitle={Transactions on Reconfigurable Technology and Systems},
title={CGRA-EAM - Rapid energy and area estimation for coarse-grained reconfigurable architectures},
publisher={ACM},
month={June},
address={New York, NY, USA},
year={2021},}Downloads
No Downloads available for this publication
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- 94. Mehdi Moghaddamfar, Christian Färber, Wolfgang Lehner, Norman May, Akash Kumar, "Resource-Efficient Database Query Processing on FPGAs", Proceedings of the 17th International Workshop on Data Management on New Hardware (DaMoN 2021), ACM, Jun 2021. [doi] [Bibtex & Downloads]
Resource-Efficient Database Query Processing on FPGAs
Reference
Mehdi Moghaddamfar, Christian Färber, Wolfgang Lehner, Norman May, Akash Kumar, "Resource-Efficient Database Query Processing on FPGAs", Proceedings of the 17th International Workshop on Data Management on New Hardware (DaMoN 2021), ACM, Jun 2021. [doi]
Bibtex
@inproceedings{Moghaddamfar_2021,
doi = {10.1145/3465998.3466006},
url = {https://doi.org/10.1145%2F3465998.3466006},
year = 2021,
month = {jun},
publisher = ,
author = {Mehdi Moghaddamfar and Christian Färber and Wolfgang Lehner and Norman May and Akash Kumar},
title = {Resource-Efficient Database Query Processing on {FPGAs}},
booktitle = {Proceedings of the 17th International Workshop on Data Management on New Hardware ({DaMoN} 2021)}
}Downloads
No Downloads available for this publication
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- 93. Maartje Roosmalen, Anna Herrmann, Akash Kumar, "A review of prefabricated self-sufficient facades with integrated decentralised HVAC and renewable energy generation and storage", In Energy and Buildings, Elsevier BV, pp. 111107, May 2021. [doi] [Bibtex & Downloads]
A review of prefabricated self-sufficient facades with integrated decentralised HVAC and renewable energy generation and storage
Reference
Maartje Roosmalen, Anna Herrmann, Akash Kumar, "A review of prefabricated self-sufficient facades with integrated decentralised HVAC and renewable energy generation and storage", In Energy and Buildings, Elsevier BV, pp. 111107, May 2021. [doi]
Bibtex
@article{Roosmalen_2021,
doi = {10.1016/j.enbuild.2021.111107},
url = {https://doi.org/10.1016%2Fj.enbuild.2021.111107},
year = 2021,
month = {may},
publisher = {Elsevier {BV}},
pages = {111107},
author = {Maartje Roosmalen and Anna Herrmann and Akash Kumar},
title = {A review of prefabricated self-sufficient facades with integrated decentralised {HVAC} and renewable energy generation and storage},
journal = {Energy and Buildings}
}Downloads
SoA_Intelli_Facade_black [PDF]
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- 92. Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro, "Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. [Bibtex & Downloads]
Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design
Reference
Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro, "Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
Bibtex
@inproceedings{De_la_Parra_2021,
year = 2021,
month = may,
author = {Cecilia De la Parra and Ahmed El-Yamany and Taha Soliman and Akash Kumar and Norbert Wehn and Andre Guntoro},
title = {Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design},
booktitle = {2021 {IEEE} International Symposium on Circuits and Systems ({ISCAS})}
}Downloads
iscas-2021-cecilia [PDF]
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- 91. Zahra Ebrahimi, Akash Kumar, "BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2021. [doi] [Bibtex & Downloads]
BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge
Reference
Zahra Ebrahimi, Akash Kumar, "BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2021. [doi]
Bibtex
@inproceedings{Ebrahimi_2021,
doi = {10.1109/iscas51556.2021.9401461},
url = {https://doi.org/10.1109%2Fiscas51556.2021.9401461},
year = 2021,
month = {may},
publisher = ,
author = {Zahra Ebrahimi and Akash Kumar},
title = {{BioCare}: An Energy-Efficient {CGRA} for Bio-Signal Processing at the Edge},
booktitle = {2021 {IEEE} International Symposium on Circuits and Systems ({ISCAS})}
}Downloads
ISCAS_BioCare_2021 [PDF]
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- 90. Max Sponner, Bernd Waschneck, Akash Kumar, "Compiler Toolchains for Deep Learning Workloads on Embedded Platforms", April 2021. [Bibtex & Downloads]
Compiler Toolchains for Deep Learning Workloads on Embedded Platforms
Reference
Max Sponner, Bernd Waschneck, Akash Kumar, "Compiler Toolchains for Deep Learning Workloads on Embedded Platforms", April 2021.
Bibtex
@misc{sponner2021compiler,
title={Compiler Toolchains for Deep Learning Workloads on Embedded Platforms},
author={Max Sponner and Bernd Waschneck and Akash Kumar},
year={2021},
month={April},
eprint={2104.04576},
archivePrefix={arXiv},
primaryClass={cs.PL},
}Downloads
compiler_tool_chain [PDF]
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- 89. Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 264-269, Feb. 2021. [doi] [Bibtex & Downloads]
Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem
Reference
Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 264-269, Feb. 2021. [doi]
Bibtex
@INPROCEEDINGS{behnaz2021date,
author={Ranjbar, Behnaz and Hosseinghorban, Ali and Sahoo, Siva Satyendra and Ejlali, Alireza and Kumar, Akash},
booktitle={2021 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
title={Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem},
year={2021},
month={Feb.},
volume={},
number={},
pages={264-269},
organization={IEEE},
doi={10.23919/DATE51398.2021.9474263}}Downloads
Improving_Timing_DATE21 [PDF]
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- 88. Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. de Abreu, Isac de Souza Campos, Augusto Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit O. Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] [Bibtex & Downloads]
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
Reference
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. de Abreu, Isac de Souza Campos, Augusto Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit O. Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]
Bibtex
@inproceedings{Rai_2021,
doi = {10.23919/date51398.2021.9473972},
url = {https://doi.org/10.23919%2Fdate51398.2021.9473972},
year = 2021,
month = {feb},
publisher = ,
author = {Shubham Rai and Walter Lau Neto and Yukio Miyasaka and Xinpei Zhang and Mingfei Yu and Qingyang Yi and Masahiro Fujita and Guilherme B. Manske and Matheus F. Pontes and Leomar S. da Rosa and Marilton S. de Aguiar and Paulo F. Butzen and Po-Chun Chien and Yu-Shan Huang and Hoa-Ren Wang and Jie-Hong R. Jiang and Jiaqi Gu and Zheng Zhao and Zixuan Jiang and David Z. Pan and Brunno A. de Abreu and Isac de Souza Campos and Augusto Berndt and Cristina Meinhardt and Jonata T. Carvalho and Mateus Grellert and Sergio Bampi and Aditya Lohana and Akash Kumar and Wei Zeng and Azadeh Davoodi and Rasit O. Topaloglu and Yuan Zhou and Jordan Dotzel and Yichi Zhang and Hanyu Wang and Zhiru Zhang and Valerio Tenace and Pierre-Emmanuel Gaillardon and Alan Mishchenko and Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DATE_version_IWLS [PDF]
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- 87. Shubham Rai, Mengyun Liu, Anteneh Gebregiorgis, Debjyoti Bhattacharjee, Krishnendu Chakrabarty, Said Hamdioui, Anupam Chattopadhyay, Jens Trommer, Akash Kumar, "Perspectives on Emerging Computation-in-Memory Paradigms" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] [Bibtex & Downloads]
Perspectives on Emerging Computation-in-Memory Paradigms
Reference
Shubham Rai, Mengyun Liu, Anteneh Gebregiorgis, Debjyoti Bhattacharjee, Krishnendu Chakrabarty, Said Hamdioui, Anupam Chattopadhyay, Jens Trommer, Akash Kumar, "Perspectives on Emerging Computation-in-Memory Paradigms" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]
Bibtex
@inproceedings{Rai_2021,
doi = {10.23919/date51398.2021.9473976},
url = {https://doi.org/10.23919%2Fdate51398.2021.9473976},
year = 2021,
month = {feb},
publisher = ,
author = {Shubham Rai and Mengyun Liu and Anteneh Gebregiorgis and Debjyoti Bhattacharjee and Krishnendu Chakrabarty and Said Hamdioui and Anupam Chattopadhyay and Jens Trommer and Akash Kumar},
title = {Perspectives on Emerging Computation-in-Memory Paradigms},
booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DATE_2021_SS_In_Memory_Computing [PDF]
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- 86. Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] [Bibtex & Downloads]
Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies
Reference
Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]
Bibtex
@inproceedings{Rai_2021,
doi = {10.23919/date51398.2021.9474112},
url = {https://doi.org/10.23919%2Fdate51398.2021.9474112},
year = 2021,
month = {feb},
publisher = ,
author = {Shubham Rai and Heinz Riener and Giovanni De Micheli and Akash Kumar},
title = {Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies},
booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DATE_2021_preserving [PDF]
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- 85. Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar, "Vertical IP Protection of the Next-Generation Devices: Quo Vadis?" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] [Bibtex & Downloads]
Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Reference
Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar, "Vertical IP Protection of the Next-Generation Devices: Quo Vadis?" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]
Bibtex
@inproceedings{Rai_2021,
doi = {10.23919/date51398.2021.9474132},
url = {https://doi.org/10.23919%2Fdate51398.2021.9474132},
year = 2021,
month = {feb},
publisher = ,
author = {Shubham Rai and Siddharth Garg and Christian Pilato and Vladimir Herdt and Elmira Moussavi and Dominik Sisejkovic and Ramesh Karri and Rolf Drechsler and Farhad Merchant and Akash Kumar},
title = {Vertical {IP} Protection of the Next-Generation Devices: Quo Vadis?},
booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DATE_2021_SS_Security_Emerging(5) [PDF]
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- 84. Sadia Moriam, Elke Franz, Paul Walther, Akash Kumar, Thorsten Strufe, Gerhard Fettweis, "Efficient Communication Protection of Many-Core Systems against Active Attackers", In Electronics, MDPI AG, vol. 10, no. 3, pp. 238, Jan 2021. [doi] [Bibtex & Downloads]
Efficient Communication Protection of Many-Core Systems against Active Attackers
Reference
Sadia Moriam, Elke Franz, Paul Walther, Akash Kumar, Thorsten Strufe, Gerhard Fettweis, "Efficient Communication Protection of Many-Core Systems against Active Attackers", In Electronics, MDPI AG, vol. 10, no. 3, pp. 238, Jan 2021. [doi]
Bibtex
@article{Moriam_2021,
doi = {10.3390/electronics10030238},
url = {https://doi.org/10.3390%2Felectronics10030238},
year = 2021,
month = {jan},
publisher = {{MDPI} {AG}},
volume = {10},
number = {3},
pages = {238},
author = {Sadia Moriam and Elke Franz and Paul Walther and Akash Kumar and Thorsten Strufe and Gerhard Fettweis},
title = {Efficient Communication Protection of Many-Core Systems against Active Attackers},
journal = {Electronics}
}Downloads
electronics-10-00238-v2 [PDF]
Related Paths
Permalink
- 83. Siva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar, "Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 1, pp. 7, Jan 2021. [doi] [Bibtex & Downloads]
Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper
Reference
Siva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar, "Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 1, pp. 7, Jan 2021. [doi]
Bibtex
@article{Sahoo_2021,
doi = {10.3390/jlpea11010007},
url = {https://doi.org/10.3390%2Fjlpea11010007},
year = 2021,
month = {jan},
publisher = {{MDPI} {AG}},
volume = {11},
number = {1},
pages = {7},
author = {Siva Satyendra Sahoo and Behnaz Ranjbar and Akash Kumar},
title = {Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper},
journal = {Journal of Low Power Electronics and Applications}
}Downloads
jlpea-11-00007 [PDF]
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- 82. Cecilia De la Parra, Xuyi Wu, Akash Kumar, Andre Guntoro, "Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. [Bibtex & Downloads]
Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks
Reference
Cecilia De la Parra, Xuyi Wu, Akash Kumar, Andre Guntoro, "Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021.
Bibtex
@INPROCEEDINGS{cecilia_2021_date,
author={Cecilia De la Parra and Xuyi Wu and Akash Kumar and Andre Guntoro},
booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
title= {Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks},
year= {2021},
organization={IEEE},
}Downloads
Knowledge_Distillation_DATE21 [PDF]
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- 81. Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling", In Proceeding: 2021 Asia and South Pacific Design Automation Conference (ASPDAC), 2021. [Bibtex & Downloads]
Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling
Reference
Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling", In Proceeding: 2021 Asia and South Pacific Design Automation Conference (ASPDAC), 2021.
Bibtex
@INPROCEEDINGS{cecilia_2021_aspdac,
author={Cecilia De la Parra and Andre Guntoro and Akash Kumar},
booktitle={2021 Asia and South Pacific Design Automation Conference (ASPDAC)},
title={Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling},
year={2021},
organization={IEEE},
}Downloads
Approx_Neural_Network_ASPDAC [PDF]
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- 80. Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Herrmann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer, "Nano Security: From Nano-Electronics To Secure Systems", In Proceeding: 2021 Design and Automation & Test in Europe Conference & Exhibition (DATE), 2021. [Bibtex & Downloads]
Nano Security: From Nano-Electronics To Secure Systems
Reference
Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Herrmann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer, "Nano Security: From Nano-Electronics To Secure Systems", In Proceeding: 2021 Design and Automation & Test in Europe Conference & Exhibition (DATE), 2021.
Bibtex
@InProceedings{akash2021date-ss5,
author= {Ilia Polian and Frank Altmann and Tolga Arul and Christian Boit and Lucas Davi and Rolf Drechsler and Nan Du and Thomas Eisenbarth and Tim Güneysu and Sascha Herrmann and Matthias Hiller and Rainer Leupers and Farhad Merchant and Thomas Mussenbrock and Stefan Katzenbeisser and Akash Kumar and Wolfgang Kunz and Thomas Mikolajick and Vivek Pachauri and Jean-Pierre Seifert and Frank Sill Torres and Jens Trommer},
booktitle= {2021 Design and Automation & Test in Europe Conference & Exhibition (DATE)},
title= {Nano Security: From Nano-Electronics To Secure Systems},
year= {2021},
organization = {IEEE},
}Downloads
DATE_21_Nano_Security [PDF]
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- 79. Salim Ullah, Semeen Rehman, Muhammad Shafique, Akash Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi] [Bibtex & Downloads]
High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators
Reference
Salim Ullah, Semeen Rehman, Muhammad Shafique, Akash Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi]
Bibtex
@article{Ullah_2021,
doi = {10.1109/tcad.2021.3056337},
url = {https://doi.org/10.1109%2Ftcad.2021.3056337},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Salim Ullah and Semeen Rehman and Muhammad Shafique and Akash Kumar},
title = {High-Performance Accurate and Approximate Multipliers for {FPGA}-based Hardware Accelerators},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
}Downloads
acc_app_TCAD [PDF]
Related Paths
other
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- 78. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "RECON: Resource-Efficient CORDIC-Based Neuron Architecture", In IEEE Open Journal of Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 2, pp. 170–181, 2021. [doi] [Bibtex & Downloads]
RECON: Resource-Efficient CORDIC-Based Neuron Architecture
Reference
Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "RECON: Resource-Efficient CORDIC-Based Neuron Architecture", In IEEE Open Journal of Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 2, pp. 170–181, 2021. [doi]
Bibtex
@article{Raut_2021,
doi = {10.1109/ojcas.2020.3042743},
url = {https://doi.org/10.1109%2Fojcas.2020.3042743},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {2},
pages = {170--181},
author = {Gopal Raut and Shubham Rai and Santosh Kumar Vishvakarma and Akash Kumar},
title = {{RECON}: Resource-Efficient {CORDIC}-Based Neuron Architecture},
journal = {{IEEE} Open Journal of Circuits and Systems}
}Downloads
Recon [PDF]
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2020
- 77. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] [Bibtex & Downloads]
ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems
Reference
Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi]
Bibtex
@article{Baranwal_2020,
doi = {10.1109/tcad.2020.3028350},
url = {https://doi.org/10.1109%2Ftcad.2020.3028350},
year = 2020,
month={28 October},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Akhil Raj Baranwal and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{ReLAccS}: A Multi-level Approach to Accelerator Design for Reinforcement Learning on {FPGA}-based Systems},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
}Downloads
ReLAccS_TCAD_Author-prepared [PDF]
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- 76. Arlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors", In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi] [Bibtex & Downloads]
An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors
Reference
Arlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors", In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi]
Bibtex
@inproceedings{John_2020,
doi = {10.1109/icecs49266.2020.9294859},
url = {https://doi.org/10.1109%2Ficecs49266.2020.9294859},
year = 2020,
month = {nov},
publisher = ,
author = {Arlene John and Salim Ullah and Akash Kumar and Barry Cardiff and Deepu John},
title = {An Approximate Binary Classifier for Data Integrity Assessment in {IoT} Sensors},
booktitle = {2020 27th {IEEE} International Conference on Electronics, Circuits and Systems ({ICECS})}
}Downloads
Approximate_binary_classifier [PDF]
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- 75. Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi] [Bibtex & Downloads]
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits
Reference
Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi]
Bibtex
@article{Rai_2020,
doi = {10.1109/tetc.2020.3039375},
url = {https://doi.org/10.1109%2Ftetc.2020.3039375},
year = 2020,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Shubham Rai and Satwik Patnaik and Ansh Rupani and Johann Knechtel and Ozgur Sinanoglu and Akash Kumar},
title = {Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits},
journal = {{IEEE} Transactions on Emerging Topics in Computing}
}Downloads
TETC_Security_author-copy [PDF]
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- 74. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems", In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020. [Bibtex & Downloads]
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems
Reference
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems", In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020.
Bibtex
@InProceedings{SahooVK020,
author = {Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
title = ,
booktitle = {2020 {IEEE} {International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020}},
year = {2020},
month = {October},
}Downloads
No Downloads available for this publication
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- 73. Behnaz Ranjbar, Bardia Safaei, Alireza Ejlali, Akash Kumar, "FANTOM: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, October 2020. [doi] [Bibtex & Downloads]
FANTOM: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems
Reference
Behnaz Ranjbar, Bardia Safaei, Alireza Ejlali, Akash Kumar, "FANTOM: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, October 2020. [doi]
Bibtex
@article{Ranjbar_2020,
doi = {10.1109/access.2020.3031039},
url = {https://doi.org/10.1109%2Faccess.2020.3031039},
year = 2020,
month = {October},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Behnaz Ranjbar and Bardia Safaei and Alireza Ejlali and Akash Kumar},
title = {{FANTOM}: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems},
journal = {{IEEE} Access}
}Downloads
ACCESS3031039-author-accepted [PDF]
Related Paths
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- 72. Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Full Approximation of Deep Neural Networks through Efficient Optimization", In Proceeding: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Oct 2020. [doi] [Bibtex & Downloads]
Full Approximation of Deep Neural Networks through Efficient Optimization
Reference
Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Full Approximation of Deep Neural Networks through Efficient Optimization", In Proceeding: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Oct 2020. [doi]
Bibtex
@inproceedings{De_la_Parra_2020,
doi = {10.1109/iscas45731.2020.9181236},
url = {https://doi.org/10.1109%2Fiscas45731.2020.9181236},
year = 2020,
month = {oct},
publisher = ,
author = {Cecilia De la Parra and Andre Guntoro and Akash Kumar},
title = {Full Approximation of Deep Neural Networks through Efficient Optimization},
booktitle = {2020 {IEEE} International Symposium on Circuits and Systems ({ISCAS})}
}Downloads
iscas-2020-camera-ready [PDF]
Permalink
- 71. Zahra Ebrahimi, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", Proceedings of the 2020 on Great Lakes Symposium on VLSI, ACM, Sep 2020. [doi] [Bibtex & Downloads]
SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy
Reference
Zahra Ebrahimi, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", Proceedings of the 2020 on Great Lakes Symposium on VLSI, ACM, Sep 2020. [doi]
Bibtex
@inproceedings{Ebrahimi_2020,
doi = {10.1145/3386263.3406907},
url = {https://doi.org/10.1145%2F3386263.3406907},
year = 2020,
month = {sep},
publisher = ,
author = {Zahra Ebrahimi and Salim Ullah and Akash Kumar},
title = {{SIMDive}: Approximate {SIMD} Soft Multiplier-Divider for {FPGAs} with Tunable Accuracy},
booktitle = {Proceedings of the 2020 on Great Lakes Symposium on {VLSI}}
}Downloads
SIMDive_GLSVLSI_2020 [PDF]
Related Paths
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- 70. S. S. Sahoo, B. Veeravalli, A. Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems", In Proceeding: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2020. [doi] [Bibtex & Downloads]
CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems
Reference
S. S. Sahoo, B. Veeravalli, A. Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems", In Proceeding: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2020. [doi]
Bibtex
@INPROCEEDINGS{9218747,
author={S. S. {Sahoo} and B. {Veeravalli} and A. {Kumar}},
booktitle={2020 57th ACM/IEEE Design Automation Conference (DAC)},
title={CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems},
year={2020},
volume={},
number={},
pages={1-6},
doi={10.1109/DAC18072.2020.9218747}}Downloads
CLRIntegTMap_DAC2020_CameraReady(1) [PDF]
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- 69. Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Improving approximate neural networks for perception tasks through specialized optimization", In Future Generation Computer Systems, vol. 113, pp. 597 - 606, July 2020. [doi] [Bibtex & Downloads]
Improving approximate neural networks for perception tasks through specialized optimization
Reference
Cecilia De la Parra, Andre Guntoro, Akash Kumar, "Improving approximate neural networks for perception tasks through specialized optimization", In Future Generation Computer Systems, vol. 113, pp. 597 - 606, July 2020. [doi]
Abstract
Approximate Computing has been proven successful in reducing the energy consumption of Deep Neural Networks (DNNs) implemented in embedded systems. For efficient DNN approximation at software and hardware levels, a specialized simulation environment and optimization methodology are required, to reduce execution and optimization times, as well as to maximize energy savings. Traditional frameworks for cross-layer approximate computation of DNNs are generally built only for simulation of convolutional and fully-connected layers, limiting the DNN types to be optimized through approximations. In this work, we present a specialized simulation environment for approximate DNNs, which allows for optimization of several DNN architectures built with more complex DNN layers such as depthwise convolutions and Recurrent Neural Units (RNNs) for time series processing. Low execution time overhead is achieved hereby through efficient GPU acceleration. Additionally, we deliver an analysis of approximate DNN and RNN robustness against quantization noise and different approximation levels. Finally, through specialized approximate retraining, we achieve promising energy savings and negligible accuracy losses with highly complex DNNs for image classification with ImageNet, such as MobileNet, and RNNs for keyword spotting with the Speech Commands Dataset.
Bibtex
@article{DELAPARRA2020597,
title = "Improving approximate neural networks for perception tasks through specialized optimization",
journal = "Future Generation Computer Systems",
volume = "113",
pages = "597 - 606",
year = "2020",
month = "July",
issn = "0167-739X",
doi = "https://doi.org/10.1016/j.future.2020.07.031",
url = "http://www.sciencedirect.com/science/article/pii/S0167739X20301576",
author = "Cecilia {De la Parra} and Andre Guntoro and Akash Kumar",
keywords = "Approximate neural networks, Approximate computing, Approximate multipliers, Neural network optimization",
abstract = "Approximate Computing has been proven successful in reducing the energy consumption of Deep Neural Networks (DNNs) implemented in embedded systems. For efficient DNN approximation at software and hardware levels, a specialized simulation environment and optimization methodology are required, to reduce execution and optimization times, as well as to maximize energy savings. Traditional frameworks for cross-layer approximate computation of DNNs are generally built only for simulation of convolutional and fully-connected layers, limiting the DNN types to be optimized through approximations. In this work, we present a specialized simulation environment for approximate DNNs, which allows for optimization of several DNN architectures built with more complex DNN layers such as depthwise convolutions and Recurrent Neural Units (RNNs) for time series processing. Low execution time overhead is achieved hereby through efficient GPU acceleration. Additionally, we deliver an analysis of approximate DNN and RNN robustness against quantization noise and different approximation levels. Finally, through specialized approximate retraining, we achieve promising energy savings and negligible accuracy losses with highly complex DNNs for image classification with ImageNet, such as MobileNet, and RNNs for keyword spotting with the Speech Commands Dataset.",
}Downloads
Elsevier_Approx_DNN [PDF]
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- 68. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications", In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2020. [doi] [Bibtex & Downloads]
A CORDIC Based Configurable Activation Function for ANN Applications
Reference
Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications", In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2020. [doi]
Abstract
An efficient ASIC-based hardware design of activation function (AF) in neural networks faces the challenge of offering functional configurability and limited chip area. Therefore an area-efficient configurable architecture for an AF is imperative to fully harness the parallel processing capacity of an ASIC in contrast to a general-purpose processor. To address this, we propose a configurable AF based on the shift-and-add algorithm, collectively known as Co-ordinate Rotation Digital Computer(CORDIC) algorithm. The proposed versatile configurable activation function is designed using CORDIC architecture and implements both tan hyperbolic and sigmoid function. The derived model is synthesized and verified at 45nm technology. Further, in order to address leakage issues at lower technology nodes, we exploit the power-gating technique for the proposed AF based on CORDIC architecture. Our circuit design is extracted in cadence virtuoso and simulated for all physical parameters. With respect to the state-of-the-art, our design architecture shows improvement by 29% in area, 42% in power dissipation and 20% in latency. The used power gating technique saves 30% static power with minimal area overhead. The Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that mean and σ deviation are 180.73µW and 51.7µW respectively which is 60% of the state-of-the-art.
Bibtex
@inproceedings{Raut_2020,
doi = {10.1109/isvlsi49217.2020.00024},
url = {https://doi.org/10.1109%2Fisvlsi49217.2020.00024},
year = 2020,
month = {jul},
publisher = ,
author = {Gopal Raut and Shubham Rai and Santosh Kumar Vishvakarma and Akash Kumar},
title = {A {CORDIC} Based Configurable Activation Function for {ANN} Applications},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
}Downloads
ISVLSI 2020 Paper [PDF]
Permalink
- 67. M. Raitza, S. Märcker, J. Trommer, A. Heinzig, S. Klüppelholz, C. Baier, A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates", In IEEE Access, pp. 1-1, June 2020. [Bibtex & Downloads]
Quantitative Characterization of Reconfigurable Transistor Logic Gates
Reference
M. Raitza, S. Märcker, J. Trommer, A. Heinzig, S. Klüppelholz, C. Baier, A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates", In IEEE Access, pp. 1-1, June 2020.
Bibtex
@ARTICLE{9113477,
author={M. {Raitza} and S. {Märcker} and J. {Trommer} and A. {Heinzig} and S. {Klüppelholz} and C. {Baier} and A. {Kumar}},
journal={IEEE Access},
title={Quantitative Characterization of Reconfigurable Transistor Logic Gates},
year={2020},
month={June},
volume={},
number={},
pages={1-1},}Downloads
09113477 [PDF]
Related Paths
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- 66. S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks", In IEEE Access, vol. 8, pp. 118899-118911, June 2020. [Bibtex & Downloads]
ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks
Reference
S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks", In IEEE Access, vol. 8, pp. 118899-118911, June 2020.
Bibtex
@ARTICLE{9126777,
author={S. {Gupta} and S. {Ullah} and K. {Ahuja} and A. {Tiwari} and A. {Kumar}},
journal={IEEE Access},
title={ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks},
year={2020},
month={June},
volume={8},
number={},
pages={118899-118911},}Downloads
ALigN [PDF]
Permalink
- 65. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020. [Bibtex & Downloads]
Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures
Reference
S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020.
Bibtex
@ARTICLE{9072581,
author={S. {Ullah} and H. {Schmidl} and S. S. {Sahoo} and S. {Rehman} and A. {Kumar}},
journal={IEEE Transactions on Computers},
title={Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures},
year={2020},
month={April},}Downloads
TC_2019_Accurate_Approx_Multiplier [PDF]
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- 64. S. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]
L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS
Reference
S. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020.
Bibtex
@INPROCEEDINGS{date_salim,
author={S. Ullah and S. Gupta and K. Ahuja and A. Tiwari and A. Kumar},
booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS},
year={2020},
month={March},}Downloads
L2L_Date_2020 [PDF]
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- 63. C. D. L. Parra, A. Guntoro, A. Kumar, "PROXSIM: SIMULATION FRAMEWORK FOR CROSS-LAYER APPROXIMATE DNN OPTIMIZATION", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. (Best paper nominee) [Bibtex & Downloads]
PROXSIM: SIMULATION FRAMEWORK FOR CROSS-LAYER APPROXIMATE DNN OPTIMIZATION
Reference
C. D. L. Parra, A. Guntoro, A. Kumar, "PROXSIM: SIMULATION FRAMEWORK FOR CROSS-LAYER APPROXIMATE DNN OPTIMIZATION", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. (Best paper nominee)
Bibtex
@INPROCEEDINGS{date_Cecilia,
author={C. D. L. Parra and A. Guntoro and A. Kumar},
booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={PROXSIM: SIMULATION FRAMEWORK FOR CROSS-LAYER APPROXIMATE DNN OPTIMIZATION},
year={2020},
month={March},
}Downloads
date_framework [PDF]
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- 62. S. Potluri, A. Aysu, A. Kumar, "SeqL: Secure Scan-Locking for IP Protection", In Proceeding: 21st International Symposium on Quality Electronic Design (ISQED), March 2020. [Bibtex & Downloads]
SeqL: Secure Scan-Locking for IP Protection
Reference
S. Potluri, A. Aysu, A. Kumar, "SeqL: Secure Scan-Locking for IP Protection", In Proceeding: 21st International Symposium on Quality Electronic Design (ISQED), March 2020.
Bibtex
@INPROCEEDINGS{date_Seetal,
author={S. Potluri and A. Aysu and A. Kumar},
booktitle={21st International Symposium on Quality Electronic Design (ISQED)},
title={SeqL: Secure Scan-Locking for IP Protection},
year={2020},
month={March},}Downloads
SeqL_ISQED2020_CamReady [PDF]
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- 61. Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi] [Bibtex & Downloads]
DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies
Reference
Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi]
Bibtex
@inproceedings{Rai_2020,
doi = {10.23919/date48585.2020.9116216},
url = {https://doi.org/10.23919%2Fdate48585.2020.9116216},
year = 2020,
month = {mar},
publisher = ,
author = {Shubham Rai and Michael Raitza and Siva Satyendra Sahoo and Akash Kumar},
title = {{DiSCERN}: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DiSCERN_DATE_2020 [PDF]
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- 60. Tuan D. A. Nguyen, Akash Kumar, "Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment", In Proceeding: 28th International Symposium on Field-Programmable Gate Arrays, February 2020. [Bibtex & Downloads]
Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment
Reference
Tuan D. A. Nguyen, Akash Kumar, "Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment", In Proceeding: 28th International Symposium on Field-Programmable Gate Arrays, February 2020.
Bibtex
@INPROCEEDINGS{tuanFPGA,
author={Tuan D. A. Nguyen and Akash Kumar},
booktitle={28th International Symposium on Field-Programmable Gate Arrays},
title={Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment},
year={2020},
month={February},}Downloads
serviceability-fpga-058-2020-camera_ready [PDF]
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- 59. Zahra Ebrahimi, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, Jan 2020. [doi] [Bibtex & Downloads]
LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy
Reference
Zahra Ebrahimi, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, Jan 2020. [doi]
Bibtex
@inproceedings{Ebrahimi_2020,
doi = {10.1109/asp-dac47756.2020.9045171},
url = {https://doi.org/10.1109%2Fasp-dac47756.2020.9045171},
year = 2020,
month = {jan},
publisher = ,
author = {Zahra Ebrahimi and Salim Ullah and Akash Kumar},
title = {{LeAp}: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy},
booktitle = {2020 25th Asia and South Pacific Design Automation Conference ({ASP}-{DAC})}
}Downloads
LeAp- [PDF]
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- 58. Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies", [Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)], no. CONF, 2020. [Bibtex & Downloads]
XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies
Reference
Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies", [Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)], no. CONF, 2020.
Bibtex
@inproceedings{rai2020xmg,
title={XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies},
author={Rai, Shubham and Riener, Heinz and De Micheli, Giovanni and Kumar, Akash},
booktitle={[Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)]},
number={CONF},
year={2020}
}Downloads
XMG__Logic_Synthesis_Primitives_Exploring_Self_Duality [PDF]
Permalink
2019
- 57. Rohit Agrawal, Kapil Ahuja, Chin Hau Hoo, Tuan Duy Anh Nguyen, Akash Kumar, "ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method", In Electronics, vol. 8, no. 12, December 2019. [doi] [Bibtex & Downloads]
ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method
Reference
Rohit Agrawal, Kapil Ahuja, Chin Hau Hoo, Tuan Duy Anh Nguyen, Akash Kumar, "ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method", In Electronics, vol. 8, no. 12, December 2019. [doi]
Abstract
In the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it. In a recent work by Hoo et al., the authors have developed a linear programming (LP)-based framework that parallelizes this routing process to achieve significant speed-ups (the resulting algorithm is termed as ParaLaR). However, this approach has certain weaknesses. Namely, the constraints violation by the solution and a standard routing metric could be improved. We address these two issues here. In this paper, we use the LP framework of ParaLaR and solve it using the primal–dual sub-gradient method that better exploits the problem properties. We also propose a better way to update the size of the step taken by this iterative algorithm. We call our algorithm as ParaLarPD. We perform experiments on a set of standard benchmarks, where we show that our algorithm outperforms not just ParaLaR but the standard existing algorithm VPR as well. We perform experiments with two different configurations. We achieve 20 % average improvement in the constraints violation and the standard metric of the minimum channel width (both of which are related) when compared with ParaLaR. When compared to VPR, we get average improvements of 28 % in the minimum channel width (there is no constraints violation in VPR). We obtain the same value for the total wire length as by ParaLaR, which is 49 % better on an average than that obtained by VPR. This is the original metric to be minimized, for which ParaLaR was proposed. Next, we look at the third and easily measurable metric of critical path delay. On an average, ParaLarPD gives 2 % larger critical path delay than ParaLaR and 3 % better than VPR. We achieve maximum relative speed-ups of up to seven times when running a parallel version of our algorithm using eight threads as compared to the sequential implementation. These speed-ups are similar to those as obtained by ParaLaR.
Bibtex
@Article{electronics8121439,
AUTHOR = {Agrawal, Rohit and Ahuja , Kapil and Hau Hoo, Chin and Duy Anh Nguyen, Tuan and Kumar, Akash},
TITLE = {ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method},
JOURNAL = {Electronics},
VOLUME = {8},
YEAR = {2019},
MONTH={December},
NUMBER = {12},
ARTICLE-NUMBER = {1439},
URL = {https://www.mdpi.com/2079-9292/8/12/1439},
ISSN = {2079-9292},
ABSTRACT = {In the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it. In a recent work by Hoo et al., the authors have developed a linear programming (LP)-based framework that parallelizes this routing process to achieve significant speed-ups (the resulting algorithm is termed as ParaLaR). However, this approach has certain weaknesses. Namely, the constraints violation by the solution and a standard routing metric could be improved. We address these two issues here. In this paper, we use the LP framework of ParaLaR and solve it using the primal–dual sub-gradient method that better exploits the problem properties. We also propose a better way to update the size of the step taken by this iterative algorithm. We call our algorithm as ParaLarPD. We perform experiments on a set of standard benchmarks, where we show that our algorithm outperforms not just ParaLaR but the standard existing algorithm VPR as well. We perform experiments with two different configurations. We achieve 20 % average improvement in the constraints violation and the standard metric of the minimum channel width (both of which are related) when compared with ParaLaR. When compared to VPR, we get average improvements of 28 % in the minimum channel width (there is no constraints violation in VPR). We obtain the same value for the total wire length as by ParaLaR, which is 49 % better on an average than that obtained by VPR. This is the original metric to be minimized, for which ParaLaR was proposed. Next, we look at the third and easily measurable metric of critical path delay. On an average, ParaLarPD gives 2 % larger critical path delay than ParaLaR and 3 % better than VPR. We achieve maximum relative speed-ups of up to seven times when running a parallel version of our algorithm using eight threads as compared to the sequential implementation. These speed-ups are similar to those as obtained by ParaLaR.},
DOI = {10.3390/electronics8121439}
}Downloads
electronics-08-01439 [PDF]
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- 56. M. Mousavi, H. R. Pourshaghaghi, H. Corporaal, A. Kumar, "Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory", In Proceeding: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1-6, Oct 2019. [doi] [Bibtex & Downloads]
Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory
Reference
M. Mousavi, H. R. Pourshaghaghi, H. Corporaal, A. Kumar, "Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory", In Proceeding: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1-6, Oct 2019. [doi]
Bibtex
@INPROCEEDINGS{8875431,
author={M. {Mousavi} and H. R. {Pourshaghaghi} and H. {Corporaal} and A. {Kumar}},
booktitle={2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)},
title={Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory},
year={2019},
volume={},
number={},
pages={1-6},
keywords={Field programmable gate arrays;Redundancy;Single event upsets;Maintenance engineering;Indexes;Fault tolerant systems;FPGA;fault tolerance;SEU;scrubbing;configuration memory},
doi={10.1109/DFT.2019.8875431},
ISSN={},
month={Oct},}Downloads
08875431 [PDF]
Related Paths
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- 55. Nusrat Jahan Lisa, Tuan D. A. Nguyen, Dirk Habich, Akash Kumar, Wolfgang Lehner, "High-Throughput Bit Packing Compression", In Proceeding: Euromicro DSD, August 2019. [Bibtex & Downloads]
High-Throughput Bit Packing Compression
Reference
Nusrat Jahan Lisa, Tuan D. A. Nguyen, Dirk Habich, Akash Kumar, Wolfgang Lehner, "High-Throughput Bit Packing Compression", In Proceeding: Euromicro DSD, August 2019.
Bibtex
@InProceedings{nusrat19high,
author = {Nusrat Jahan Lisa and Tuan D. A. Nguyen and Dirk Habich and Akash Kumar and Wolfgang Lehner},
title = {High-Throughput Bit Packing Compression},
booktitle = {Euromicro DSD},
year = {2019},
month = {August},
owner = {Ranjbar},
}Downloads
dsd2019_fpga_crc [PDF]
Permalink
- 54. Behnaz Ranjbar, Tuan D. A. Nguyen, A. Ejlali, A. Kumar, "Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 546-553, August 2019. [doi] [Bibtex & Downloads]
Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems
Reference
Behnaz Ranjbar, Tuan D. A. Nguyen, A. Ejlali, A. Kumar, "Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 546-553, August 2019. [doi]
Bibtex
@InProceedings{ranjbar19online,
author = {Behnaz Ranjbar and Tuan D. A. Nguyen and A. Ejlali and A. Kumar},
title = {Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems},
booktitle = { Euromicro Conference on Digital System Design (DSD)},
year = {2019},
month = {August},
pages={546-553},
doi={10.1109/DSD.2019.00084},
owner = {Ranjbar},
}Downloads
Permalink
- 53. Ansh Rupani, Shubham Rai, Akash Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: 2019 22nd Euromicro Conference on Digital System Design (DSD), IEEE, Aug 2019. [doi] [Bibtex & Downloads]
Exploiting Emerging Reconfigurable Technologies for Secure Devices
Reference
Ansh Rupani, Shubham Rai, Akash Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: 2019 22nd Euromicro Conference on Digital System Design (DSD), IEEE, Aug 2019. [doi]
Bibtex
@inproceedings{Rupani_2019,
doi = {10.1109/dsd.2019.00107},
url = {https://doi.org/10.1109%2Fdsd.2019.00107},
year = 2019,
month = {aug},
publisher = ,
author = {Ansh Rupani and Shubham Rai and Akash Kumar},
title = {Exploiting Emerging Reconfigurable Technologies for Secure Devices},
booktitle = {2019 22nd Euromicro Conference on Digital System Design ({DSD})}
}Downloads
DSD_final [PDF]
Permalink
- 52. Shubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2019. [doi] [Bibtex & Downloads]
Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies
Reference
Shubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2019. [doi]
Bibtex
@inproceedings{Rai_2019,
doi = {10.1109/isvlsi.2019.00123},
url = {https://doi.org/10.1109%2Fisvlsi.2019.00123},
year = 2019,
month = {jul},
publisher = ,
author = {Shubham Rai and Ansh Rupani and Pallab Nath and Akash Kumar},
title = {Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
}Downloads
ISVLSI [PDF]
Permalink
- 51. S. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems", Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019. [doi] [Bibtex & Downloads]
A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems
Reference
S. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems", Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019. [doi]
Bibtex
@inproceedings{SahooVK019_1,
author = {S. S. Sahoo and B. Veeravalli and A. Kumar},
title = ,
booktitle = ,
series = {DAC '19},
year = {2019},
month={june},
isbn = {978-1-4503-6725-7/19/06},
location = {Las Vegas, NV, USA},
numpages = {6},
url = {http://doi.acm.org/10.1145/3316781.3317746},
doi = {10.1145/3316781.3317746},
acmid = {3317746},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {Cross-layer Reliability, Run-time Resource Management, Embedded Systems, Reinforcement Learning},
}Downloads
a38-Sahoo [PDF]
Permalink
- 50. Adarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks", Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi] [Bibtex & Downloads]
Design Methodology for Embedded Approximate Artificial Neural Networks
Reference
Adarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks", Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi]
Bibtex
@inproceedings{Balaji:2019:DME:3299874.3319490,
author = {Balaji, Adarsha and Ullah, Salim and Das, Anup and Kumar, Akash},
title = {Design Methodology for Embedded Approximate Artificial Neural Networks},
booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI},
series = {GLSVLSI '19},
year = {2019},
month={May},
isbn = {978-1-4503-6252-8},
location = {Tysons Corner, VA, USA},
pages = {489--494},
numpages = {6},
url = {http://doi.acm.org/10.1145/3299874.3319490},
doi = {10.1145/3299874.3319490},
acmid = {3319490},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {approximate computing, artificial neural networks (anns), fpga},
}Downloads
p489-balaji [PDF]
Permalink
- 49. Mohammed Alser, Hasan Hassan, Akash Kumar, Onur Mutlu, Can Alkan, "Shouji: a fast and efficient pre-alignment filter for sequence alignment", In Bioinformatics, vol. 35, no. 21, pp. 4255-4263, 03/2019. [doi] [Bibtex & Downloads]
Shouji: a fast and efficient pre-alignment filter for sequence alignment
Reference
Mohammed Alser, Hasan Hassan, Akash Kumar, Onur Mutlu, Can Alkan, "Shouji: a fast and efficient pre-alignment filter for sequence alignment", In Bioinformatics, vol. 35, no. 21, pp. 4255-4263, 03/2019. [doi]
Abstract
The ability to generate massive amounts of sequencing data continues to overwhelm the processing capability of existing algorithms and compute infrastructures. In this work, we explore the use of hardware/software co-design and hardware acceleration to significantly reduce the execution time of short sequence alignment, a crucial step in analyzing sequenced genomes. We introduce Shouji, a highly parallel and accurate pre-alignment filter that remarkably reduces the need for computationally-costly dynamic programming algorithms. The first key idea of our proposed pre-alignment filter is to provide high filtering accuracy by correctly detecting all common subsequences shared between two given sequences. The second key idea is to design a hardware accelerator that adopts modern field-programmable gate array (FPGA) architectures to further boost the performance of our algorithm.Shouji significantly improves the accuracy of pre-alignment filtering by up to two orders of magnitude compared to the state-of-the-art pre-alignment filters, GateKeeper and SHD. Our FPGA-based accelerator is up to three orders of magnitude faster than the equivalent CPU implementation of Shouji. Using a single FPGA chip, we benchmark the benefits of integrating Shouji with five state-of-the-art sequence aligners, designed for different computing platforms. The addition of Shouji as a pre-alignment step reduces the execution time of the five state-of-the-art sequence aligners by up to 18.8×. Shouji can be adapted for any bioinformatics pipeline that performs sequence alignment for verification. Unlike most existing methods that aim to accelerate sequence alignment, Shouji does not sacrifice any of the aligner capabilities, as it does not modify or replace the alignment step.https://github.com/CMU-SAFARI/Shouji.Supplementary data are available at Bioinformatics online.
Bibtex
@article{10.1093/bioinformatics/btz234,
author = {Alser, Mohammed and Hassan, Hasan and Kumar, Akash and Mutlu, Onur and Alkan, Can},
title = "{Shouji: a fast and efficient pre-alignment filter for sequence alignment}",
journal = {Bioinformatics},
volume = {35},
number = {21},
pages = {4255-4263},
year = {2019},
month = {03},
abstract = "{The ability to generate massive amounts of sequencing data continues to overwhelm the processing capability of existing algorithms and compute infrastructures. In this work, we explore the use of hardware/software co-design and hardware acceleration to significantly reduce the execution time of short sequence alignment, a crucial step in analyzing sequenced genomes. We introduce Shouji, a highly parallel and accurate pre-alignment filter that remarkably reduces the need for computationally-costly dynamic programming algorithms. The first key idea of our proposed pre-alignment filter is to provide high filtering accuracy by correctly detecting all common subsequences shared between two given sequences. The second key idea is to design a hardware accelerator that adopts modern field-programmable gate array (FPGA) architectures to further boost the performance of our algorithm.Shouji significantly improves the accuracy of pre-alignment filtering by up to two orders of magnitude compared to the state-of-the-art pre-alignment filters, GateKeeper and SHD. Our FPGA-based accelerator is up to three orders of magnitude faster than the equivalent CPU implementation of Shouji. Using a single FPGA chip, we benchmark the benefits of integrating Shouji with five state-of-the-art sequence aligners, designed for different computing platforms. The addition of Shouji as a pre-alignment step reduces the execution time of the five state-of-the-art sequence aligners by up to 18.8×. Shouji can be adapted for any bioinformatics pipeline that performs sequence alignment for verification. Unlike most existing methods that aim to accelerate sequence alignment, Shouji does not sacrifice any of the aligner capabilities, as it does not modify or replace the alignment step.https://github.com/CMU-SAFARI/Shouji.Supplementary data are available at Bioinformatics online.}",
issn = {1367-4803},
doi = {10.1093/bioinformatics/btz234},
url = {https://doi.org/10.1093/bioinformatics/btz234},
eprint = {https://academic.oup.com/bioinformatics/article-pdf/35/21/4255/30330769/btz234.pdf},
}Downloads
No Downloads available for this publication
Permalink
- 48. Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 27, no. 3, pp. 560–572, Mar 2019. [doi] [Bibtex & Downloads]
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors
Reference
Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 27, no. 3, pp. 560–572, Mar 2019. [doi]
Bibtex
@article{Rai_2019,
doi = {10.1109/tvlsi.2018.2884646},
url = {https://doi.org/10.1109%2Ftvlsi.2018.2884646},
year = 2019,
month = {mar},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {27},
number = {3},
pages = {560--572},
author = {Shubham Rai and Jens Trommer and Michael Raitza and Thomas Mikolajick and Walter M. Weber and Akash Kumar},
title = {Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors},
journal = {{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}
}Downloads
08580544 [PDF]
Related Paths
Permalink
- 47. Gerhard Fettweis, Meik Dörpinghaus, Jeronimo Castrillon, Akash Kumar, Christel Baier, Karlheinz Bock, Frank Ellinger, Andreas Fery, Frank H. P. Fitzek, Hermann Härtig, Kambiz Jamshidi, Thomas Kissinger, Wolfgang Lehner, Michael Mertig, Wolfgang E. Nagel, Giang T. Nguyen, Dirk Plettemeier, Michael Schröter, Thorsten Strufe, "Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy-Efficient Computing", In Proceedings of the IEEE, vol. 107, no. 1, pp. 204–231, Jan 2019. [doi] [Bibtex & Downloads]
Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy-Efficient Computing
Reference
Gerhard Fettweis, Meik Dörpinghaus, Jeronimo Castrillon, Akash Kumar, Christel Baier, Karlheinz Bock, Frank Ellinger, Andreas Fery, Frank H. P. Fitzek, Hermann Härtig, Kambiz Jamshidi, Thomas Kissinger, Wolfgang Lehner, Michael Mertig, Wolfgang E. Nagel, Giang T. Nguyen, Dirk Plettemeier, Michael Schröter, Thorsten Strufe, "Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy-Efficient Computing", In Proceedings of the IEEE, vol. 107, no. 1, pp. 204–231, Jan 2019. [doi]
Bibtex
@Article{fettweis_ieeeproc19,
author = {Gerhard Fettweis and Meik D{\"o}rpinghaus and Jeronimo Castrillon and Akash Kumar and Christel Baier and Karlheinz Bock and Frank Ellinger and Andreas Fery and Frank H. P. Fitzek and Hermann H{\"a}rtig and Kambiz Jamshidi and Thomas Kissinger and Wolfgang Lehner and Michael Mertig and Wolfgang E. Nagel and Giang T. Nguyen and Dirk Plettemeier and Michael Schr{\"o}ter and Thorsten Strufe},
title = {Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy-Efficient Computing},
journal = {Proceedings of the IEEE},
year = {2019},
volume = {107},
number = {1},
pages = {204--231},
month = jan,
doi = {10.1109/JPROC.2018.2874895},
issn = {0018-9219},
url = {https://ieeexplore.ieee.org/document/8565890}
}Downloads
1812_Fettweis_IEEEProc [PDF]
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2018
- 46. S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning", In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), pp. 230-233, Dec 2018. [doi] [Bibtex & Downloads]
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning
Reference
S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning", In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), pp. 230-233, Dec 2018. [doi]
Bibtex
@INPROCEEDINGS{8742320,
author={S. S. {Sahoo} and T. D. A. {Nguyen} and B. {Veeravalli} and A. {Kumar}},
booktitle={2018 International Conference on Field-Programmable Technology (FPT)},
title={QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning},
year={2018},
volume={},
number={},
pages={230-233},
keywords={circuit optimisation;field programmable gate arrays;integrated circuit design;integrated circuit reliability;logic design;quality of service;Dynamic Partial Reconfiguration;QoS-aware cross-layer reliability-integrated design methodology;FPGA-based DPR systems;FPGA-based dynamic partially reconfigurable system;partially reconfigurable modules;quality of service;fault-mitigation;Conferences;Cross-layer Reliability;Dynamic Partial Reconfiguration;Field Programmable Gate Array;Embedded Systems},
doi={10.1109/FPT.2018.00041},
ISSN={},
month={Dec},}Downloads
08742320 [PDF]
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- 45. Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?", Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi] [Bibtex & Downloads]
Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?
Reference
Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?", Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi]
Bibtex
@inproceedings{Rai:2018:ERN:3240765.3243472,
author = {Rai, Shubham and Srinivasa, Srivatsa and Cadareanu, Patsy and Yin, Xunzhao and Hu, Xiaobo Sharon and Gaillardon, Pierre-Emmanuel and Narayanan, Vijaykrishnan and Kumar, Akash},
title = {Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?},
booktitle = {Proceedings of the International Conference on Computer-Aided Design},
series = {ICCAD '18},
year = {2018},
month = {November},
isbn = {978-1-4503-5950-4},
location = {San Diego, California},
pages = {13:1--13:8},
articleno = {13},
numpages = {8},
url = {http://doi.acm.org/10.1145/3240765.3243472},
doi = {10.1145/3240765.3243472},
acmid = {3243472},
publisher = {ACM},
address = {New York, NY, USA},
}Downloads
PID5531423 [PDF]
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- 44. S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems", In Integration, November 2018. [doi] [Bibtex & Downloads]
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems
Reference
S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems", In Integration, November 2018. [doi]
Abstract
Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification.
Bibtex
@article{SAHOO2018,
title = "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems",
journal = "Integration",
year = "2018",
month={November},
issn = "0167-9260",
doi = "https://doi.org/10.1016/j.vlsi.2018.10.006",
url = "http://www.sciencedirect.com/science/article/pii/S0167926018302608",
author = "S.S. Sahoo and T.D.A. Nguyen and B. Veeravalli and A. Kumar",
keywords = "Dynamic partial reconfiguration, Field programmable gate arrays, Lifetime-aware scheduling, Task-graphs, Reliability, Heterogeneous systems, Real-time systems",
abstract = "Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification."
}Downloads
Multi-objective design_space_exploration [PDF]
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- 43. Rohit Agrawal, Chin Hao Hoo, Kapil Ahuja, Akash Kumar, "Parallel FPGA Router using Sub-Gradient method and Steiner tree", In arXiv preprint arXiv:1803.03885, August 2018. [Bibtex & Downloads]
Parallel FPGA Router using Sub-Gradient method and Steiner tree
Reference
Rohit Agrawal, Chin Hao Hoo, Kapil Ahuja, Akash Kumar, "Parallel FPGA Router using Sub-Gradient method and Steiner tree", In arXiv preprint arXiv:1803.03885, August 2018.
Bibtex
@article{agrawal2018parallel,
title={Parallel FPGA Router using Sub-Gradient method and Steiner tree},
author={Agrawal, Rohit and Hoo, Chin Hao and Ahuja, Kapil and Kumar, Akash},
journal={arXiv preprint arXiv:1803.03885},
year={2018},
month={August}
}Downloads
Parallel_FPGA_Router_Rohit [PDF]
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- 42. Jeronimo Castrillon, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems", In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi] [Bibtex & Downloads]
A Hardware/Software Stack for Heterogeneous Systems
Reference
Jeronimo Castrillon, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems", In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi]
Abstract
Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.
Bibtex
@Article{castrillon_tmscs17,
author = {Jeronimo Castrillon and Matthias Lieber and Sascha Kl{\"u}ppelholz and Marcus V{\"o}lp and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fr{\"o}hlich and Andr\'{e}s Goens and Sebastian Haas and Dirk Habich and Hermann H{\"a}rtig and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Akash Kumar and Wolfgang Lehner and Linda Leuschner and Siqi Ling and Steffen M{\"a}rcker and Christian Menard and Johannes Mey and Wolfgang Nagel and Benedikt N{\"o}then and Rafael Pe{\~n}aloza and Michael Raitza and J{\"o}rg Stiller and Annett Ungeth{\"u}m and Axel Voigt and Sascha Wunderlich},
title = {A Hardware/Software Stack for Heterogeneous Systems},
journal = {IEEE Transactions on Multi-Scale Computing Systems},
year = {2018},
month = jul,
volume={4},
number={3},
pages={243-259},
abstract = {Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.},
doi = {10.1109/TMSCS.2017.2771750},
issn = {2332-7766},
url = {http://ieeexplore.ieee.org/document/8103042/}
}Downloads
1711_Castrillon_TMSCS [PDF]
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- 41. Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Nguyen Duy Anh Tuan, Akash Kumar, Wolfgang Lehner, "Column Scan Optimization by Increasing Intra-Instruction Parallelism", Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA), July 2018. (Best Paper Award) [Bibtex & Downloads]
Column Scan Optimization by Increasing Intra-Instruction Parallelism
Reference
Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Nguyen Duy Anh Tuan, Akash Kumar, Wolfgang Lehner, "Column Scan Optimization by Increasing Intra-Instruction Parallelism", Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA), July 2018. (Best Paper Award)
Bibtex
@InProceedings{lisaDATA2018,
author = {Nusrat Jahan Lisa and Annett Ungethüm and Dirk Habich and Nguyen Duy Anh Tuan and Akash Kumar and Wolfgang Lehner},
title = {Column Scan Optimization by Increasing Intra-Instruction Parallelism},
booktitle = {Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA) },
month = {July},
year = {2018},
}Downloads
DATA_2018_47_CR (1) [PDF]
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- 40. Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers", Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018. [Bibtex & Downloads]
SMApproxlib: library of FPGA-based approximate multipliers
Reference
Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers", Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018.
Bibtex
@inproceedings{ullah2018smapproxlib,
title={SMApproxlib: library of FPGA-based approximate multipliers},
author={Ullah, Salim and Murthy, Sanjeev Sripadraj and Kumar, Akash},
booktitle={Proceedings of the 55th Annual Design Automation Conference},
pages={157},
year={2018},
month={June},
organization={ACM}
}Downloads
PID5307267 [PDF]
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- 39. Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators", Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018. [Bibtex & Downloads]
Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators
Reference
Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators", Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018.
Bibtex
@inproceedings{ullah2018area,
title={Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators},
author={Ullah, Salim and Rehman, Semeen and Prabakaran, Bharath Srinivas and Kriebel, Florian and Hanif, Muhammad Abdullah and Shafique, Muhammad and Kumar, Akash},
booktitle={Proceedings of the 55th Annual Design Automation Conference},
pages={159},
year={2018},
month={June},
organization={ACM}
}Downloads
PID5307263 [PDF]
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- 38. Sadia Moriam, Elke Franz, Paul Walther, Akash Kumar, Thorsten Strufe, Gerhard Fettweis, "Protecting Communication in Many-Core Systems against Active Attackers", Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp. 45–50, May 2018. [Bibtex & Downloads]
Protecting Communication in Many-Core Systems against Active Attackers
Reference
Sadia Moriam, Elke Franz, Paul Walther, Akash Kumar, Thorsten Strufe, Gerhard Fettweis, "Protecting Communication in Many-Core Systems against Active Attackers", Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp. 45–50, May 2018.
Bibtex
@inproceedings{moriam2018protecting,
title={Protecting Communication in Many-Core Systems against Active Attackers},
author={Moriam, Sadia and Franz, Elke and Walther, Paul and Kumar, Akash and Strufe, Thorsten and Fettweis, Gerhard},
booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI},
pages={45--50},
year={2018},
Month={May},
organization={ACM}
}Downloads
No Downloads available for this publication
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- 37. Anup Das, Akash Kumar, "Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware", Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp. 419–422, May 2018. [Bibtex & Downloads]
Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware
Reference
Anup Das, Akash Kumar, "Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware", Proceedings of the 2018 on Great Lakes Symposium on VLSI, pp. 419–422, May 2018.
Bibtex
@inproceedings{das2018dataflow,
title={Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware},
author={Das, Anup and Kumar, Akash},
booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI},
pages={419--422},
year={2018},
month={May},
organization={ACM}
}Downloads
No Downloads available for this publication
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- 36. Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar, YC Tay, "A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems", In Proceeding: 2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC), pp. 116–123, May 2018. [Bibtex & Downloads]
A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems
Reference
Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar, YC Tay, "A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems", In Proceeding: 2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC), pp. 116–123, May 2018.
Bibtex
@inproceedings{haque2018self,
title={A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems},
author={Haque, Mohammad Shihabul and Vasudevan, Sriram and Nihar, Alamuri Sriram and Easwaran, Arvind and Kumar, Akash and Tay, YC},
booktitle={2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)},
pages={116--123},
year={2018},
month={May},
organization={IEEE}
}Downloads
No Downloads available for this publication
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- 35. Bjorn Gottschall, Thomas PreuBer, Akash Kumar, "Reloc—An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles", In Proceeding: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 211–211, April 2018. [Bibtex & Downloads]
Reloc—An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles
Reference
Bjorn Gottschall, Thomas PreuBer, Akash Kumar, "Reloc—An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles", In Proceeding: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 211–211, April 2018.
Bibtex
@inproceedings{gottschall2018reloc,
title={Reloc—An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles},
author={Gottschall, Bjorn and PreuBer, Thomas and Kumar, Akash},
booktitle={2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
pages={211--211},
year={2018},
month={April},
organization={IEEE}
}Downloads
No Downloads available for this publication
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- 34. B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi] [Bibtex & Downloads]
DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems
Reference
B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi]
Bibtex
@INPROCEEDINGS{8342140,
author={B. S. Prabakaran and S. Rehman and M. A. Hanif and S. Ullah and G. Mazaheri and A. Kumar and M. Shafique},
booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems},
year={2018},
volume={},
number={},
pages={917-920},
keywords={adders;field programmable gate arrays;logic design;public domain software;DeMAS;FPGA community;RTL;approximate adders;area gain;behavioral model;generic design methodology;latency gain;multibit adder architectures;power-delay product gain;Adders;Approximate computing;Delays;Design methodology;Field programmable gate arrays;Hardware;Table lookup;Adders;Approximate Computing;Area;CAD;Design Flow;Efficiency;FPGA;LUTs;Optimization;Performance;Power},
doi={10.23919/DATE.2018.8342140},
ISSN={},
month={March},}Downloads
DeMAS_DATE_2018 [PDF]
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- 33. Shubham Rai, Michael Raitza, Akash Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] [Bibtex & Downloads]
Technology mapping flow for emerging reconfigurable silicon nanowire transistors
Reference
Shubham Rai, Michael Raitza, Akash Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]
Bibtex
@inproceedings{Rai_2018,
doi = {10.23919/date.2018.8342110},
url = {https://doi.org/10.23919%2Fdate.2018.8342110},
year = 2018,
month = {mar},
publisher = ,
author = {Shubham Rai and Michael Raitza and Akash Kumar},
title = {Technology mapping flow for emerging reconfigurable silicon nanowire transistors},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
Technology_Mapping_DATE_2018 [PDF]
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- 32. Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] [Bibtex & Downloads]
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs
Reference
Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]
Bibtex
@inproceedings{Rai_2018,
doi = {10.23919/date.2018.8342080},
url = {https://doi.org/10.23919%2Fdate.2018.8342080},
year = 2018,
month = {mar},
publisher = ,
author = {Shubham Rai and Ansh Rupani and Dennis Walter and Michael Raitza and Andre Heinzig and Tim Baldauf and Jens Trommer and Christian Mayr and Walter M. Weber and Akash Kumar},
title = {A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable {FETs}},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
Physical_Synthesis_DATE_2018 [PDF]
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- 31. Chin Hau Hoo, Akash Kumar, "ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling", Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 67–76, 2018. [Bibtex & Downloads]
ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling
Reference
Chin Hau Hoo, Akash Kumar, "ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling", Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 67–76, 2018.
Bibtex
@inproceedings{hoo2018paradro,
title={ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling},
author={Hoo, Chin Hau and Kumar, Akash},
booktitle={Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
pages={67--76},
year={2018},
organization={ACM}
}Downloads
ParaDRo_FPGA_18 [PDF]
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- 30. Hermann Härtig, Nils Asmussen, Jeronimo Castrillon, Adam Lackorzynski, Michael Roitzsch, Carsten Weinhold, Akash Kumar, "Extremely Heterogeneous Systems – Not Just For Niches", In Proceeding: Extreme Heterogeneity Workshop, Feb 2018. [Bibtex & Downloads]
Extremely Heterogeneous Systems – Not Just For Niches
Reference
Hermann Härtig, Nils Asmussen, Jeronimo Castrillon, Adam Lackorzynski, Michael Roitzsch, Carsten Weinhold, Akash Kumar, "Extremely Heterogeneous Systems – Not Just For Niches", In Proceeding: Extreme Heterogeneity Workshop, Feb 2018.
Bibtex
@InProceedings{haertig_ehw18,
author = {Hermann H{\"a}rtig and Nils Asmussen and Jeronimo Castrillon and Adam Lackorzynski and Michael Roitzsch and Carsten Weinhold and Akash Kumar},
title = {Extremely Heterogeneous Systems -- Not Just For Niches},
booktitle = {Extreme Heterogeneity Workshop},
year = {2018},
month = feb,
note = {(Workshop took place over remote conferencing)},
location = {Gaithersburg, MD, USA}
}Downloads
1802_Haertig_EHW [PDF]
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- 29. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems", In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018. [Bibtex & Downloads]
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems
Reference
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems", In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018.
Bibtex
@INPROCEEDINGS{VLSID2018-siva,
author={Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
booktitle={2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)},
title={CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems },
year={2018},
volume={},
number={},
pages={1-6},
keywords={Cross-layer Resilience, Real-time systems, FaultTolerance },
doi={},
ISSN={},
month={Jan},}Downloads
VLSID-2018-siva [PDF]
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- 28. Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018. [Bibtex & Downloads]
Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems
Reference
Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018.
Bibtex
@INPROCEEDINGS{dprLifeASPDAC,
author={Siva Satyendra Sahoo and Tuan Duy Anh Nguyen and B. Veeravalli and Akash Kumar},
booktitle={2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)},
title={Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems },
year={2018},
volume={},
number={},
pages={1-6},
keywords={Reconfigurable Computing, Dynamic Partial Reconfiguration, Integer Linear Programming, Network-on-Chip, FPGA Floorplanning},
month={Jan},}Downloads
ASPDAC-2018-siva [PDF]
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- 27. Anup Kumar Das, Akash Kumar, Bharadwaj Veeravalli, Francky Catthoor, "Reliable and Energy Efficient Streaming Multiprocessor Systems", Springer, 2018. [Bibtex & Downloads]
Reliable and Energy Efficient Streaming Multiprocessor Systems
Reference
Anup Kumar Das, Akash Kumar, Bharadwaj Veeravalli, Francky Catthoor, "Reliable and Energy Efficient Streaming Multiprocessor Systems", Springer, 2018.
Bibtex
@book{das2018reliable,
title={Reliable and Energy Efficient Streaming Multiprocessor Systems},
author={Das, Anup Kumar and Kumar, Akash and Veeravalli, Bharadwaj and Catthoor, Francky},
year={2018},
publisher={Springer}
}Downloads
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2017
- 26. Ang Li, Shuaiwen Leon Song, Weifeng Liu, Xu Liu, Akash Kumar, Henk Corporaal, "Locality-Aware CTA Clustering For Modern GPUs", In Proceeding: Architectural Support for Programming Languages and Operating Systems (ASPLOS '17), April 2017. [Bibtex & Downloads]
Locality-Aware CTA Clustering For Modern GPUs
Reference
Ang Li, Shuaiwen Leon Song, Weifeng Liu, Xu Liu, Akash Kumar, Henk Corporaal, "Locality-Aware CTA Clustering For Modern GPUs", In Proceeding: Architectural Support for Programming Languages and Operating Systems (ASPLOS '17), April 2017.
Bibtex
@InProceedings{ang2017asplos,
author = {Ang Li and Shuaiwen Leon Song and Weifeng Liu and Xu Liu and Akash Kumar and Henk Corporaal},
title = ,
booktitle = {Architectural Support for Programming Languages and Operating Systems (ASPLOS '17)},
year = {2017},
month = {April}
}Downloads
asplos_2017_final [PDF]
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- 25. Chin Hau Hoo, Akash Kumar, "ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding", In Proceeding: Field-Programmable Custom Computing Machines (FCCM), April 2017. [Bibtex & Downloads]
ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding
Reference
Chin Hau Hoo, Akash Kumar, "ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding", In Proceeding: Field-Programmable Custom Computing Machines (FCCM), April 2017.
Bibtex
@InProceedings{fccm2017chinhau,
author = {Chin Hau Hoo and Akash Kumar},
title = {ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding},
booktitle = {Field-Programmable Custom Computing Machines (FCCM)},
year = {2017},
month = {April}
}Downloads
fccm-2017 [PDF]
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- 24. Martin Brüstel, Akash Kumar, "Accounting for Systematic Errors in Approximate Computing", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. [Bibtex & Downloads]
Accounting for Systematic Errors in Approximate Computing
Reference
Martin Brüstel, Akash Kumar, "Accounting for Systematic Errors in Approximate Computing", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.
Bibtex
@InProceedings{martin2017date,
author = {Br\"ustel, Martin and Kumar, Akash},
title = ,
booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
year = {2017},
month = {March},
organization = {IEEE},
}Downloads
date-2017-martin [PDF]
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- 23. Walaa El-Harouni, Semeen Rehman, Bharath Srinivas Prabakaran, Akash Kumar, Rehan Hafiz, Muhammad Shafique, "Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. (Best paper nominee) [Bibtex & Downloads]
Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding
Reference
Walaa El-Harouni, Semeen Rehman, Bharath Srinivas Prabakaran, Akash Kumar, Rehan Hafiz, Muhammad Shafique, "Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. (Best paper nominee)
Bibtex
@InProceedings{semeen2017date,
author = {Walaa El-Harouni and Semeen Rehman and Bharath Srinivas Prabakaran and Akash Kumar and Rehan Hafiz and Muhammad Shafique},
title = {Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding},
booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
month = {March},
year = {2017},
organization = {IEEE},
}Downloads
DATE_2017_788_OutputPaper [PDF]
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- 22. Arun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Soft Error-Aware Architectural Exploration for Designing Reliability Adaptive Cache Hierarchies in Multi-Cores", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. [Bibtex & Downloads]
Soft Error-Aware Architectural Exploration for Designing Reliability Adaptive Cache Hierarchies in Multi-Cores
Reference
Arun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Soft Error-Aware Architectural Exploration for Designing Reliability Adaptive Cache Hierarchies in Multi-Cores", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.
Bibtex
@InProceedings{semeen2017date2,
author = {Arun Subramaniyan and Semeen Rehman and Muhammad Shafique and Akash Kumar and J\"org Henkel},
title = ,
booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
year = {2017},
month = {March},
organization = {IEEE}
}Downloads
DATE_2017_597_OutputPaper [PDF]
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- 21. Michael Raitza, Jens Trommer, Akash Kumar, Marcus Völp, Dennis Walter, Walter Weber, Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. [Bibtex & Downloads]
Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits
Reference
Michael Raitza, Jens Trommer, Akash Kumar, Marcus Völp, Dennis Walter, Walter Weber, Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.
Bibtex
@InProceedings{raitza2017date,
author = {Michael Raitza and Jens Trommer and Akash Kumar and Marcus Völp and Dennis Walter and Walter Weber and Thomas Mikolajick},
title = {Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits},
booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
year = {2017},
month = {March},
organization = {IEEE}
}Downloads
date-2017-michael [PDF]
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- 20. Rui Santos, Shyamsundar Venkataraman, Akash Kumar, "Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices", In ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017. [Bibtex & Downloads]
Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices
Reference
Rui Santos, Shyamsundar Venkataraman, Akash Kumar, "Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices", In ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017.
Bibtex
@article{rui-todaes-2017,
title = {Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices},
journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
year = {2017},
author = {Rui Santos and Shyamsundar Venkataraman and Akash Kumar}
}Downloads
todaes-2017-scrubbing [PDF]
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2016
- 19. Semeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Architectural-Space Exploration of Approximate Multipliers", Proceedings of the International Conference on Computer-Aided Design (ICCAD), Nov 2016. [Bibtex & Downloads]
Architectural-Space Exploration of Approximate Multipliers
Reference
Semeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Architectural-Space Exploration of Approximate Multipliers", Proceedings of the International Conference on Computer-Aided Design (ICCAD), Nov 2016.
Bibtex
@InProceedings{semeen2016iccad,
Title= ,
Author= {Semeen Rehman and Walaa El-Harouni and Muhammad Shafique and Akash Kumar and J{\"{o}}rg Henkel},
Booktitle= {Proceedings of the International Conference on Computer-Aided Design (ICCAD)},
month={nov},
dates={7-10},
Year= {2016}
}Downloads
ICCAD_2017_ApproxMult [PDF]
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- 18. Nam Khanh Pham, Akash Kumar, Khin Mi Mi Aung, "Automatic framework to generate reconfigurable accelerators for option pricing applications", In Proceeding: International Conference on Reconfigurable Computing and FPGAs (ReConFig), Nov 2016. [Bibtex & Downloads]
Automatic framework to generate reconfigurable accelerators for option pricing applications
Reference
Nam Khanh Pham, Akash Kumar, Khin Mi Mi Aung, "Automatic framework to generate reconfigurable accelerators for option pricing applications", In Proceeding: International Conference on Reconfigurable Computing and FPGAs (ReConFig), Nov 2016.
Bibtex
@InProceedings{Khanh-Reconfig-2016,
title = {Automatic framework to generate reconfigurable accelerators for option pricing applications},
Booktitle = {International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
year = {2016},
month={Nov},
author = {Nam Khanh Pham and Akash Kumar and Khin Mi Mi Aung}
}Downloads
ReConFig_2016 [PDF]
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- 17. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems", In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016. [Bibtex & Downloads]
Cross-layer fault-tolerant design of real-time systems
Reference
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems", In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016.
Bibtex
@INPROCEEDINGS{sssahooDFT16,
author={Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
booktitle={International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)},
title={Cross-layer fault-tolerant design of real-time systems},
year={2016},
pages={1--6},
month={Sept}}Downloads
DFT_cam_ready_Certified [PDF]
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- 16. Amit Kumar Singh, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, no. 99, pp. 1-14, Aug 2016. [doi] [Bibtex & Downloads]
Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors
Reference
Amit Kumar Singh, Muhammad Shafique, Akash Kumar, Jörg Henkel, "Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, no. 99, pp. 1-14, Aug 2016. [doi]
Bibtex
@ARTICLE{amit2016tvlsi,
author={Amit Kumar Singh and Muhammad Shafique and Akash Kumar and J{\"{o}}rg Henkel},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
title={Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors},
year={2016},
volume={PP},
number={99},
pages={1-14},
keywords={Acceleration;Correlation;Multicore processing;Prediction algorithms;Through-silicon vias;Throughput;3-D multicore;3-D video;design-time analysis;interconnect energy;synchronous dataflow;thermal-aware mapping;throughput.},
doi={10.1109/TVLSI.2016.2517025},
url={http://dx.doi.org/10.1109/TVLSI.2016.2517025},
ISSN={1063-8210},
month={aug},
}Downloads
tvlsi-2016-amit [PDF]
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- 15. Tuan D. A. Nguyen, Akash Kumar, "XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1-11, Aug 2016. [Bibtex & Downloads]
XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip
Reference
Tuan D. A. Nguyen, Akash Kumar, "XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1-11, Aug 2016.
Bibtex
@INPROCEEDINGS{xnocfpl2016,
author={Tuan D. A. Nguyen and Akash Kumar},
booktitle={International Conference on Field Programmable Logic and Applications (FPL)},
title={XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip},
year={2016},
pages={1-11},
month={Aug}}Downloads
fpl_2016_xnoc [PDF]
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- 14. Chin Hau Hoo, Yajun Ha, Akash Kumar, "ParaFRo: A Hybrid Parallel FPGA Router using Fine Grained Synchronization and Partitioning", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1–11, Aug 2016. [Bibtex & Downloads]
ParaFRo: A Hybrid Parallel FPGA Router using Fine Grained Synchronization and Partitioning
Reference
Chin Hau Hoo, Yajun Ha, Akash Kumar, "ParaFRo: A Hybrid Parallel FPGA Router using Fine Grained Synchronization and Partitioning", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1–11, Aug 2016.
Bibtex
@inproceedings{hoo2016parafro,
title={ParaFRo: A Hybrid Parallel FPGA Router using Fine Grained Synchronization and Partitioning},
author={Hoo, Chin Hau and Ha, Yajun and Kumar, Akash},
booktitle={International Conference on Field Programmable Logic and Applications (FPL)},
pages={1–11},
month={Aug},
year={2016},
organization={IEEE}
}Downloads
akumar_fpl2016_ChinHau [PDF]
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- 13. Ang Li, Shuaiwen Leon Song, Mark Wijtvliet, Akash Kumar, Henk Corporaal, "SFU-Driven Transparent Approximation Acceleration on GPUs", Proceedings of the 2016 International Conference on Supercomputing, pp. 15, Jun 2016. [Bibtex & Downloads]
SFU-Driven Transparent Approximation Acceleration on GPUs
Reference
Ang Li, Shuaiwen Leon Song, Mark Wijtvliet, Akash Kumar, Henk Corporaal, "SFU-Driven Transparent Approximation Acceleration on GPUs", Proceedings of the 2016 International Conference on Supercomputing, pp. 15, Jun 2016.
Bibtex
@inproceedings{li2016sfu,
title={SFU-Driven Transparent Approximation Acceleration on GPUs},
author={Li, Ang and Song, Shuaiwen Leon and Wijtvliet, Mark and Kumar, Akash and Corporaal, Henk},
booktitle={Proceedings of the 2016 International Conference on Supercomputing},
pages={15},
year={2016},
month={jun},
organization={ACM}
}Downloads
ICS-a15-li_camera-ready [PDF]
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- 12. Ang Li, Leon Shuaiwen Song, Eric Brugel, Akash Kumar, Daniel Chavarria, Henk Corporaal, "X: A Comprehensive Analytic Model for Parallel Machines", In Proceeding: 30th International Parallel and Distributed Processing Symposium (IPDPS), May 2016. [Bibtex & Downloads]
X: A Comprehensive Analytic Model for Parallel Machines
Reference
Ang Li, Leon Shuaiwen Song, Eric Brugel, Akash Kumar, Daniel Chavarria, Henk Corporaal, "X: A Comprehensive Analytic Model for Parallel Machines", In Proceeding: 30th International Parallel and Distributed Processing Symposium (IPDPS), May 2016.
Bibtex
@inproceedings{li2016x,
title={X: A Comprehensive Analytic Model for Parallel Machines},
author={Li, Ang and Song, Leon Shuaiwen and Brugel, Eric and Kumar, Akash and Chavarria, Daniel and Corporaal, Henk},
booktitle={30th International Parallel and Distributed Processing Symposium (IPDPS)},
year={2016},
month={may},
organization={IEEE}
}Downloads
IPDPS x-model [PDF]
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- 11. Pham Nam Khanh, Akash Kumar, Khin Mi Mi Aung, "Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms", Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES, Sankt Goar, Germany, May 23-25, 2016, pp. 127–134, May 2016. (Awarded with Best presentation award of SCOPES 2016) [doi] [Bibtex & Downloads]
Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms
Reference
Pham Nam Khanh, Akash Kumar, Khin Mi Mi Aung, "Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms", Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES, Sankt Goar, Germany, May 23-25, 2016, pp. 127–134, May 2016. (Awarded with Best presentation award of SCOPES 2016) [doi]
Bibtex
@inproceedings{DBLP:conf/scopes/KhanhKA16,
author={Khanh, Pham Nam and Kumar, Akash and Aung, Khin Mi Mi},
title={Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms},
booktitle={Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, {SCOPES}, Sankt Goar, Germany, May 23-25, 2016},
pages={127--134},
year={2016},
month={May},
crossref={DBLP:conf/scopes/2016},
url={http://doi.acm.org/10.1145/2906363.2906380},
doi={10.1145/2906363.2906380},
}Downloads
scopes_2016_camera_ready [PDF]
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- 10. Ang Li, Leon Shuaiwen Song, Akash Kumar, Eddy Z. Zhang, Daniel Chavarria Gerardo, Henk Corporaal, "Critical Points Based Register-Concurrency Autotuning for GPUs", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2016. [Bibtex & Downloads]
Critical Points Based Register-Concurrency Autotuning for GPUs
Reference
Ang Li, Leon Shuaiwen Song, Akash Kumar, Eddy Z. Zhang, Daniel Chavarria Gerardo, Henk Corporaal, "Critical Points Based Register-Concurrency Autotuning for GPUs", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2016.
Bibtex
@inproceedings{li2016date,
title={Critical Points Based Register-Concurrency Autotuning for GPUs},
author={Li, Ang and Song, Leon Shuaiwen and Kumar, Akash and Zhang, Eddy Z. and Chavarria Gerardo, Daniel and Corporaal, Henk},
booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE)},
year={2016},
month={march},
organization={IEEE}
}Downloads
DATE-16-camera-ready [PDF]
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- 9. Shyamsundar Venkataraman, Rui Santos, Akash Kumar, "A Flexible Inexact TMR Technique for SRAM-based FPGAs", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2016. [Bibtex & Downloads]
A Flexible Inexact TMR Technique for SRAM-based FPGAs
Reference
Shyamsundar Venkataraman, Rui Santos, Akash Kumar, "A Flexible Inexact TMR Technique for SRAM-based FPGAs", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2016.
Bibtex
@inproceedings{rui2016date,
title={A Flexible Inexact TMR Technique for SRAM-based FPGAs},
author={Venkataraman, Shyamsundar and Santos, Rui and Kumar, Akash},
booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE)},
year={2016},
month={march},
organization={IEEE}
}Downloads
DATE 2016 Camera ready [PDF]
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- 8. Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016. [Bibtex & Downloads]
Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults
Reference
Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016.
Bibtex
@inproceedings{siva2016date,
title={Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults},
author={Siva Satyendra Sahoo and Akash Kumar and Bharadwaj Veeravalli},
booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE)},
year={2016},
month={mar},
organization={IEEE}
}Downloads
date-2016-385-camera ready [PDF]
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- 7. Tuan D. A. Nguyen, Akash Kumar, "PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems", In Proceeding: The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb 2016. [Bibtex & Downloads]
PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems
Reference
Tuan D. A. Nguyen, Akash Kumar, "PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems", In Proceeding: The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb 2016.
Bibtex
@inproceedings{tuan2016fpga,
title={PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems},
author={Tuan D. A. Nguyen and Akash Kumar},
booktitle={The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)},
year={2016},
month={Feb},
organization={IEEE}
}Downloads
fp029-nguyenA [PDF]
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- 6. Amit Kumar Singh, Mohammad Shafique, Akash Kumar, Joerg Henkel, "Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 1, pp. 72-85, Jan 2016. [doi] [Bibtex & Downloads]
Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs
Reference
Amit Kumar Singh, Mohammad Shafique, Akash Kumar, Joerg Henkel, "Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 1, pp. 72-85, Jan 2016. [doi]
Bibtex
@article{singh2016resource,
author={Amit Kumar Singh and Mohammad Shafique and Akash Kumar and Joerg Henkel},
journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
title={Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs},
year={2016},
volume={35},
number={1},
pages={72-85},
doi={10.1109/TCAD.2015.2446938},
ISSN={0278-0070},
month={Jan},}Downloads
TCAD-2016-RunTimeTraceMatch [PDF]
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- 5. Pham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung, "Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures", In Microprocessors and Microsystems, 2016. [Bibtex & Downloads]
Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures
Reference
Pham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung, "Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures", In Microprocessors and Microsystems, 2016.
Bibtex
@article{Khanh-Micpro-2016,
title = {Leakage Aware Resource Management Approach with Machine Learning Optimization Framework for Partially Reconfigurable Architectures},
journal = {Microprocessors and Microsystems },
year = {2016},
author = {Pham Nam Khanh and Amit Kumar Singh and Akash Kumar and Khin Mi Mi Aung}
}Downloads
MICPRO-2016-Khanh [PDF]
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2015
- 4. Ang Li, Gert-Jan van den Braak, Akash Kumar, Henk Corporaal, "Adaptive and transparent cache bypassing for GPUs", Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 17, Nov 2015. [Bibtex & Downloads]
Adaptive and transparent cache bypassing for GPUs
Reference
Ang Li, Gert-Jan van den Braak, Akash Kumar, Henk Corporaal, "Adaptive and transparent cache bypassing for GPUs", Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 17, Nov 2015.
Bibtex
@inproceedings{li2015adaptive,
title={Adaptive and transparent cache bypassing for GPUs},
author={Li, Ang and van den Braak, Gert-Jan and Kumar, Akash and Corporaal, Henk},
booktitle={Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis},
pages={17},
year={2015},
month={nov},
organization={ACM}
}Downloads
SC-2015-camera-ready-a17-li [PDF]
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- 3. R. Santos, S. Venkataraman, Akash Kumar, "Generic Scrubbing-based Architecture for Custom Error Correction Algorithms", In Proceeding: Rapid System Prototyping (RSP), 2015 26th IEEE International Symposium on, Oct 2015. [Bibtex & Downloads]
Generic Scrubbing-based Architecture for Custom Error Correction Algorithms
Reference
R. Santos, S. Venkataraman, Akash Kumar, "Generic Scrubbing-based Architecture for Custom Error Correction Algorithms", In Proceeding: Rapid System Prototyping (RSP), 2015 26th IEEE International Symposium on, Oct 2015.
Bibtex
@INPROCEEDINGS{Santos2015,
author={Santos, R. and Venkataraman, S. and Kumar, Akash},
title={Generic Scrubbing-based Architecture for Custom Error Correction Algorithms},
booktitle={Rapid System Prototyping (RSP), 2015 26th IEEE International Symposium on},
Organization={IEEE},
month={oct},
year={2015}
}Downloads
RSP2015_final [PDF]
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- 2. Shakith Fernando, Mark Wijtvliet, Cedric Nugteren, Akash Kumar, Henk Corporaal, "(AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration", In Proceeding: 2015 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 305-308, 2015. [Bibtex & Downloads]
(AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration
Reference
Shakith Fernando, Mark Wijtvliet, Cedric Nugteren, Akash Kumar, Henk Corporaal, "(AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration", In Proceeding: 2015 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 305-308, 2015.
Bibtex
@INPROCEEDINGS{7092403,
author={Fernando, Shakith and Wijtvliet, Mark and Nugteren, Cedric and Kumar, Akash and Corporaal, Henk},
booktitle={2015 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={(AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration},
year={2015},
volume={},
number={},
pages={305-308},}Downloads
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2013
- 1. Shakith Fernando, Mark Wijtvliet, Firew Siyoum, Yifan He, Sander Stuijk, Akash Kumar, Henk Corporaal, "MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis", In Proceeding: 2013 23rd International Conference on Field programmable Logic and Applications, pp. 1-1, 2013. [Bibtex & Downloads]
MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis
Reference
Shakith Fernando, Mark Wijtvliet, Firew Siyoum, Yifan He, Sander Stuijk, Akash Kumar, Henk Corporaal, "MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis", In Proceeding: 2013 23rd International Conference on Field programmable Logic and Applications, pp. 1-1, 2013.
Bibtex
@INPROCEEDINGS{6645623,
author={Fernando, Shakith and Wijtvliet, Mark and Siyoum, Firew and He, Yifan and Stuijk, Sander and Kumar, Akash and Corporaal, Henk},
booktitle={2013 23rd International Conference on Field programmable Logic and Applications},
title={MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis},
year={2013},
volume={},
number={},
pages={1-1},}Downloads
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