Shubham Rai

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E-mail

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Visitor's Address

shubham.rai@tu-dresden.de

+49 351 463-43727

+49 (0)351 463-39995

Helmholtzstrasse 18, BAR-III76

Publications

  • 2021

  • 14. Shubham Rai, Mengyun Liu, Anteneh Gebregiorgis, Debjyoti Bhattacharjee, Krishnendu Chakrabarty, Said Hamdioui, Anupam Chattopadhyay, Jens Trommer, Akash Kumar, "Emerging In-Memory Computing Paradigms" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. [Bibtex & Downloads]
  • 13. Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. [Bibtex & Downloads]
  • 12. Shubham Rai, Siddharth Garg, Christian Pilato, Ramesh Karri, Vladimir Herdt, Rolf Drechsler, Elmira Moussavi, Dominik Šišejković, Farhad Merchant, Akash Kumar, "Next Generation IP Protection: from Systems Down to Devices" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. [Bibtex & Downloads]
  • 2020

  • 11. Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits" , In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi] [Bibtex & Downloads]
  • 10. G. Raut, S. Rai, S. K. Vishvakarma, A. Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications" , In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 78-83, July 2020. (Best paper nominee) [doi] [Bibtex & Downloads]
  • 9. S. Rai, M. Raitza, S. S. Sahoo, A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]
  • 8. Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies" , [Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)], no. CONF, 2020. [Bibtex & Downloads]
  • 7. Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Junior, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. de Abreu, Isac de Souza Campos, Augusto Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit O. Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization" , 2020. [Bibtex & Downloads]
  • 2019

  • 6. A. Rupani, S. Rai, A. Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices" , In Proceeding: Euromicro DSD, August 2019. [Bibtex & Downloads]
  • 5. S. Rai, A. Rupani, P. Nath, A. Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies" , In Proceeding: ISVLSI, July 2019. [Bibtex & Downloads]
  • 4. S. Rai, J. Trommer, M. Raitza, T. Mikolajick, W. M. Weber, A. Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors" , In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 560-572, March 2019. [doi] [Bibtex & Downloads]
  • 2018

  • 3. Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?" , Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi] [Bibtex & Downloads]
  • 2. S. Rai, M. Raitza, A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 767-772, March 2018. [doi] [Bibtex & Downloads]
  • 1. S. Rai, A. Rupani, D. Walter, M. Raitza, A. Heinzig, T. Baldauf, J. Trommer, C. Mayr, W. M. Weber, A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 605-608, March 2018. [doi] [Bibtex & Downloads]