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Shubham Rai |
||
Phone Fax Visitor's Address |
+49 351 463-43727 +49 (0)351 463-39995 Helmholtzstrasse 18, BAR-III76 |
Shubham Rai was working as a research associate in the group from Oct, 2016. He obtained his Ph.D. Degree (Dr. Ing.) from TU Dresden, Germany in 2022. He was with the group till January, 2023. He then joined at Robert Bosch Research Center at Renningen, Germany. He received his B.Engg. in Electrical and Electronics engineering and M.Sc. in Physics from Birla Institute of Technology and Science Pilani, India. From 2011 till 2016, he worked in an RnD role at Mentor Graphics (Now under Siemens group), Noida India. Then, he worked at Green IC group at NUS, Singapore as a research assistant for 5 months before coming to Germany. His research interests are logic synthesis, hardware security, reconfigurable platforms. He is a member of the IEEE and of the ACM.
Thesis dissertation can be downloaded here
Publications
2024
- 41. Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Thwarting GNN-based attacks against logic locking", In IEEE Transactions on Information Forensics and Security, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi] [Bibtex & Downloads]
Thwarting GNN-based attacks against logic locking
Reference
Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Thwarting GNN-based attacks against logic locking", In IEEE Transactions on Information Forensics and Security, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2024. [doi]
Bibtex
@article{Darjani_2024, title={Thwarting GNN-based attacks against logic locking}, ISSN={1556-6021}, url={http://dx.doi.org/10.1109/TIFS.2024.3431991}, DOI={10.1109/tifs.2024.3431991}, journal={IEEE Transactions on Information Forensics and Security}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Darjani, Armin and Kavand, Nima and Rai, Shubham and Kumar, Akash}, year={2024}, pages={1–1} }Downloads
No Downloads available for this publication
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2023
- 40. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers", In IEEE Embedded Systems Letters, pp. 1-1, 2023. [doi] [Bibtex & Downloads]
High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers", In IEEE Embedded Systems Letters, pp. 1-1, 2023. [doi]
Bibtex
@ARTICLE{10261986,
author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
journal={IEEE Embedded Systems Letters},
title={High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers},
year={2023},
volume={},
number={},
pages={1-1},
doi={10.1109/LES.2023.3298736}}Downloads
ESL_LB_CASES_2023 Camera ready [PDF]
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- 39. Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Discerning the Limitations of GNN-Based Attacks on Logic Locking", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi] [Bibtex & Downloads]
Discerning the Limitations of GNN-Based Attacks on Logic Locking
Reference
Armin Darjani, Nima Kavand, Shubham Rai, Akash Kumar, "Discerning the Limitations of GNN-Based Attacks on Logic Locking", In Proceeding: Design Automation Conference (DAC), pp. 1-6, July 2023. [doi]
Bibtex
@inproceedings{Darjani_DAC_2023,
year = 2023,
month = {July},
author = {Armin Darjani and Nima Kavand and Shubham Rai and Akash Kumar},
title = {Discerning the Limitations of GNN-Based Attacks on Logic Locking},
booktitle = {Design Automation Conference (DAC)},
pages={1-6},
doi={10.1109/DAC56929.2023.10247847}
}Downloads
DAC2023_Cirrostrato [PDF]
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- 38. Raghul Saravanan, Sathwika Bavikadi, Shubham Rai, Akash Kumar, Sai Manoj Pudukotai Dinakarrao, "Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications", In Proceeding: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2023. [Bibtex & Downloads]
Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications
Reference
Raghul Saravanan, Sathwika Bavikadi, Shubham Rai, Akash Kumar, Sai Manoj Pudukotai Dinakarrao, "Reconfigurable FET Approximate Computing-Based Accelerator for Deep Learning Applications", In Proceeding: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2023.
Bibtex
@inproceedings{Rai_2023,
year = 2023,
month = {may},
publisher = ,
author = {Raghul Saravanan and Sathwika Bavikadi and Shubham Rai and Akash Kumar and Sai Manoj Pudukotai Dinakarrao},
title = {Reconfigurable {FET} Approximate Computing-Based Accelerator for Deep Learning Applications},
booktitle = {IEEE International Symposium on Circuits and Systems ({ISCAS})}
}Downloads
No Downloads available for this publication
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- 37. Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers", In IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, May 2023. [doi] [Bibtex & Downloads]
Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers
Reference
Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers", In IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, May 2023. [doi]
Bibtex
@ARTICLE{Kavand2023,
author={Kavand, Nima and Darjani, Armin and Rai, Shubham and Kumar, Akash},
journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
title={Design of Energy-efficient RFET-based Exact and Approximate 4:2 Compressors and Multipliers},
year={2023},
month = {May},
volume={},
number={},
pages={1-1},
doi={10.1109/TCSII.2023.3275983}}Downloads
RFET_Compressor_TCASII_brief (5) [PDF]
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- 36. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi] [Bibtex & Downloads]
NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi]
Bibtex
@INPROCEEDINGS{10196610,
author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
booktitle={2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
title={NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs},
year={2023},
volume={},
number={},
pages={85-92},
doi={10.1109/IPDPSW59300.2023.00026}}Downloads
RAW2023-NetPU-M [PDF]
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- 35. Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed Elkacem Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski, Maciej Wiatr, "Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors", In Proceeding: Design, Automation and Test in Europe Conference (DATE), IEEE/ACM, April 2023. [Bibtex & Downloads]
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors
Reference
Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed Elkacem Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski, Maciej Wiatr, "Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors", In Proceeding: Design, Automation and Test in Europe Conference (DATE), IEEE/ACM, April 2023.
Bibtex
@inproceedings{Rai_DATE_2023,
year = 2023,
month = {April},
publisher = ,
author = {Jens Trommer and Niladri Bhattacharjee and Thomas Mikolajick and Sebastian Huhn and Marcel Merten and Mohammed Elkacem Djeridane and Muhammad Hassan and Rolf Drechsler and Shubham Rai and Nima Kavand and Armin Darjani and Akash Kumar and Violetta Sessi and Maximilian Drescher and Sabine Kolodinski and Maciej Wiatr},
title = {Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors},
booktitle = {Design, Automation and Test in Europe Conference ({DATE})}
}Downloads
DATE_2023_Cirrostrato [PDF]
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- 34. Shubham Rai, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 914–927, Mar 2023. [doi] [Bibtex & Downloads]
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits
Reference
Shubham Rai, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 42, no. 3, pp. 914–927, Mar 2023. [doi]
Bibtex
@article{Rai_2023,
doi = {10.1109/tcad.2022.3184633},
url = {https://doi.org/10.1109%2Ftcad.2022.3184633},
year = 2023,
month = {mar},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {42},
number = {3},
pages = {914--927},
author = {Shubham Rai and Alessandro Tempia Calvino and Heinz Riener and Giovanni De Micheli and Akash Kumar},
title = {Utilizing {XMG}-Based Synthesis to Preserve Self-Duality for {RFET}-Based Circuits},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
}Downloads
TCAD_2022 [PDF]
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- 33. Steffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, Akash Kumar, "Formal Analysis of Camouflaged Reconfigurable Circuits" (to appear), Proceedings 21st International NEWCAS Conference, pp. 1–4, 2023. [Bibtex & Downloads]
Formal Analysis of Camouflaged Reconfigurable Circuits
Reference
Steffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, Akash Kumar, "Formal Analysis of Camouflaged Reconfigurable Circuits" (to appear), Proceedings 21st International NEWCAS Conference, pp. 1–4, 2023.
Bibtex
@inproceedings{mrt+23,
author = {M\"arcker, Steffen and Raitza, Michael and Rai, Shubham and Galderisi, Giulio and Mikolajick, Thomas and Trommer, Jens and Kumar, Akash},
title = {Formal Analysis of Camouflaged Reconfigurable Circuits},
year = {2023},
volume = {},
number = {},
pages = {1--4},
booktitle = {Proceedings 21st International NEWCAS Conference}
}Downloads
newcas23-camouflaging [PDF]
Related Paths
Permalink
2022
- 32. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi] [Bibtex & Downloads]
NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi]
Bibtex
@INPROCEEDINGS{9974206,
author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
booktitle={2022 International Conference on Field-Programmable Technology (ICFPT)},
title={NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture},
year={2022},
month = {dec},
pages={1-1},
doi={10.1109/ICFPT56656.2022.9974206}}Downloads
NetPU_Prototyping_a_Generic_Reconfigurable_Neural_Network_Accelerator_Architecture [PDF]
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- 31. Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Securing Hardware through Reconfigurable Nano-structures", In Proceeding: International Conference on Computer-Aided Design (ICCAD), ACM/IEEE, Nov 2022. [Bibtex & Downloads]
Securing Hardware through Reconfigurable Nano-structures
Reference
Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar, "Securing Hardware through Reconfigurable Nano-structures", In Proceeding: International Conference on Computer-Aided Design (ICCAD), ACM/IEEE, Nov 2022.
Bibtex
@inproceedings{Kavand_ICCAD,
year = 2022,
month = {nov},
publisher = ,
author = {Nima Kavand and Armin Darjani and Shubham Rai and Akash Kumar},
title = {Securing Hardware through Reconfigurable Nano-structures},
booktitle = {International Conference on Computer-Aided Design ({ICCAD})}
}Downloads
ICCAD_2022_Special_Session [PDF]
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- 30. Nishant Gupta, Mohil Desai, Mark Wijtvliet, Shubham Rai, Akash Kumar, "DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,", In Proceeding: 2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear), pp. 1-6, 7/2022. [Bibtex & Downloads]
DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,
Reference
Nishant Gupta, Mohil Desai, Mark Wijtvliet, Shubham Rai, Akash Kumar, "DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,", In Proceeding: 2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear), pp. 1-6, 7/2022.
Bibtex
@INPROCEEDINGS{dac-2022-delta,
author={Gupta, Nishant and Desai, Mohil and Wijtvliet, Mark and Rai, Shubham and Kumar, Akash},
booktitle={2022 59th ACM/IEEE Design Automation Conference (DAC) (to appear)},
title={DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis,},
year={2022},
month=7,
pages={1-6}
}Downloads
Nishant_Trojan-1 [PDF]
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- 29. Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu, "SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture", In Proceeding: 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2022. [doi] [Bibtex & Downloads]
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture
Reference
Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu, "SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture", In Proceeding: 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2022. [doi]
Bibtex
@inproceedings{Rangarajan_2022,
doi = {10.1109/isvlsi54635.2022.00067},
url = {https://doi.org/10.1109%2Fisvlsi54635.2022.00067},
year = 2022,
month = {jul},
publisher = ,
author = {Nikhil Rangarajan and Satwik Patnaik and Mohammed Nabeel and Mohammed Ashraf and Shubham Rai and Gopal Raut and Heba Abunahla and Baker Mohammad and Santosh Kumar Vishvakarma and Akash Kumar and Johann Knechtel and Ozgur Sinanoglu},
title = {{SCRAMBLE}: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture},
booktitle = {2022 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
}Downloads
No Downloads available for this publication
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- 28. Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), vol. 39, no. 3, pp. 73–81, Jun 2022. [doi] [Bibtex & Downloads]
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy
Reference
Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), vol. 39, no. 3, pp. 73–81, Jun 2022. [doi]
Bibtex
@article{Lohana_2022,
doi = {10.1109/mdat.2021.3063373},
url = {https://doi.org/10.1109%2Fmdat.2021.3063373},
year = 2022,
month = {jun},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {39},
number = {3},
pages = {73--81},
author = {Aditya Lohana and Ansh Rupani and Shubham Rai and Akash Kumar},
title = {Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy},
journal = {{IEEE} Design {\&} Test}
}Downloads
DandT [PDF]
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- 27. Armin Darjani, Nima Kavand, Shubham Rai, Mark Wijtvliet, Akash Kumar, "ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks", In Proceeding: ACM Great Lakes Symposium on VLSI (GLSVLSI), 6/2022. [doi] [Bibtex & Downloads]
ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks
Reference
Armin Darjani, Nima Kavand, Shubham Rai, Mark Wijtvliet, Akash Kumar, "ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks", In Proceeding: ACM Great Lakes Symposium on VLSI (GLSVLSI), 6/2022. [doi]
Bibtex
@INPROCEEDINGS{DARJANI2022,
author = {Armin Darjani and Nima Kavand and Shubham Rai and Mark Wijtvliet and Akash Kumar},
title = {ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks},
booktitle={ACM Great Lakes Symposium on VLSI (GLSVLSI)},
doi = {10.1145/3526241.3530371},
year = 2022,
month = 6
}Downloads
author-prepared-GLSVLSI_2022_ArminDarjani [PDF]
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- 26. T. Mikolajick, G. Galderisi, S. Rai, M. Simon, R. Böckle, M. Sistani, C. Cakirlar, N. Bhattacharjee, T. Mauersberger, A. Heinzig, A. Kumar, W.M. Weber, J. Trommer, "Reconfigurable Field Effect Transistors: A Technology Enablers Perspective", In Solid-State Electronics, Elsevier BV, pp. 108381, May 2022. [doi] [Bibtex & Downloads]
Reconfigurable Field Effect Transistors: A Technology Enablers Perspective
Reference
T. Mikolajick, G. Galderisi, S. Rai, M. Simon, R. Böckle, M. Sistani, C. Cakirlar, N. Bhattacharjee, T. Mauersberger, A. Heinzig, A. Kumar, W.M. Weber, J. Trommer, "Reconfigurable Field Effect Transistors: A Technology Enablers Perspective", In Solid-State Electronics, Elsevier BV, pp. 108381, May 2022. [doi]
Bibtex
@article{Mikolajick_2022,
doi = {10.1016/j.sse.2022.108381},
url = {https://doi.org/10.1016%2Fj.sse.2022.108381},
year = 2022,
month = {may},
publisher = {Elsevier {BV}},
pages = {108381},
author = {T. Mikolajick and G. Galderisi and S. Rai and M. Simon and R. Böckle and M. Sistani and C. Cakirlar and N. Bhattacharjee and T. Mauersberger and A. Heinzig and A. Kumar and W.M. Weber and J. Trommer},
title = {Reconfigurable Field Effect Transistors: A Technology Enablers Perspective},
journal = {Solid-State Electronics}
}Downloads
SSE_Review_Full_Version [PDF]
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- 25. M. Thümmler, S. Rai, A. Kumar, "Improving Technology Mapping for And-Inverter-Cones", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), March 2022. [Bibtex & Downloads]
Improving Technology Mapping for And-Inverter-Cones
Reference
M. Thümmler, S. Rai, A. Kumar, "Improving Technology Mapping for And-Inverter-Cones", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), March 2022.
Bibtex
@InProceedings{Thuemmler2022,
Title = {Improving Technology Mapping for And-Inverter-Cones},
Author = {M. Th{\"{u}}mmler and S. Rai and A. Kumar},
Booktitle = {2022 Design, Automation Test in Europe Conference Exhibition (DATE)},
Year = {2022},
Month = {March},
Owner = {shubham},
Timestamp = {2018.04.26}
}Downloads
Martin_thuemmler_AIC(1) [PDF]
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- 24. Michael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar, "Exploring Standard-Cell Designs for Reconfigurable
Nanotechnologies: A Formal Approach", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2022. [Bibtex & Downloads]
Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach
Reference
Michael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar, "Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2022.
Bibtex
@INPROCEEDINGS{9474132,
author={Raitza, Michael and M{\"a}rcker, Steffen and Rai, Shubham and Kumar, Akash},
booktitle={2022 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={Exploring Standard-Cell Designs for Reconfigurable
Nanotechnologies: A Formal Approach},
year={2022},
month = mar,
volume={},
number={}
}Downloads
DATE_SS_2022 [PDF]
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- 23. Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli, "A Versatile Mapping Approach for Technology Mapping and Graph Optimization" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022. [Bibtex & Downloads]
A Versatile Mapping Approach for Technology Mapping and Graph Optimization
Reference
Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli, "A Versatile Mapping Approach for Technology Mapping and Graph Optimization" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022.
Bibtex
@InProceedings{alessandro_2022_aspdac,
author = {Alessandro Tempia Calvino and Heinz Riener and Shubham Rai and Akash Kumar and Giovanni De Micheli},
booktitle = {Asia and South Pacific Design Automation Conference (ASPDAC)},
title = {A Versatile Mapping Approach for Technology Mapping and Graph Optimization},
year = {2022},
month = {1},
organization = {IEEE},
}Downloads
ASP_DAC22 [PDF]
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- 22. Jorge Navarro Quijada, Tim Baldauf, Shubham Rai, Andre Heinzig, Akash Kumar, Walter M. Weber, Thomas Mikolajick, Jens Trommer, "A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation", In IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–8, 2022. [doi] [Bibtex & Downloads]
A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation
Reference
Jorge Navarro Quijada, Tim Baldauf, Shubham Rai, Andre Heinzig, Akash Kumar, Walter M. Weber, Thomas Mikolajick, Jens Trommer, "A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation", In IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–8, 2022. [doi]
Bibtex
@article{Quijada_2022,
doi = {10.1109/tnano.2022.3221836},
url = {https://doi.org/10.1109%2Ftnano.2022.3221836},
year = 2022,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--8},
author = {Jorge Navarro Quijada and Tim Baldauf and Shubham Rai and Andre Heinzig and Akash Kumar and Walter M. Weber and Thomas Mikolajick and Jens Trommer},
title = {A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation},
journal = {{IEEE} Transactions on Nanotechnology}
}Downloads
GeNW_RFET_VerilogA-TNANO [PDF]
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- 21. Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi] [Bibtex & Downloads]
END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator
Reference
Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi]
Bibtex
@incollection{Rai_2022,
doi = {10.1007/978-3-031-16818-5_9},
url = {https://doi.org/10.1007%2F978-3-031-16818-5_9},
year = 2022,
publisher = {Springer Nature Switzerland},
pages = {175--203},
author = {Shubham Rai and Nishant Gupta and Abhiroop Bhattacharjee and Ansh Rupani and Michael Raitza and Jens Trommer and Thomas Mikolajick and Akash Kumar},
title = {{END}-{TRUE}: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator},
booktitle = {{VLSI}-{SoC}: Technology Advancement on {SoC} Design}
}Downloads
No Downloads available for this publication
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2021
- 20. T. Mikolajick, G. Galderisi, M. Simon, S. Rai, A. Kumar, A. Heinzig, W.M. Weber, J. Trommer, "20 Years of reconfigurable field-effect transistors: From concepts to future applications", In Solid-State Electronics, Elsevier BV, vol. 186, pp. 108036, Dec 2021. [doi] [Bibtex & Downloads]
20 Years of reconfigurable field-effect transistors: From concepts to future applications
Reference
T. Mikolajick, G. Galderisi, M. Simon, S. Rai, A. Kumar, A. Heinzig, W.M. Weber, J. Trommer, "20 Years of reconfigurable field-effect transistors: From concepts to future applications", In Solid-State Electronics, Elsevier BV, vol. 186, pp. 108036, Dec 2021. [doi]
Bibtex
@article{Mikolajick_2021,
doi = {10.1016/j.sse.2021.108036},
url = {https://doi.org/10.1016%2Fj.sse.2021.108036},
year = 2021,
month = {dec},
publisher = {Elsevier {BV}},
volume = {186},
pages = {108036},
author = {T. Mikolajick and G. Galderisi and M. Simon and S. Rai and A. Kumar and A. Heinzig and W.M. Weber and J. Trommer},
title = {20 Years of reconfigurable field-effect transistors: From concepts to future applications},
journal = {Solid-State Electronics}
}Downloads
Solid_state_electronics_2021 [PDF]
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- 19. Yasasvi V. Peruvemba, Shubham Rai, Kapil Ahuja, Akash Kumar, "RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021. [Bibtex & Downloads]
RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis
Reference
Yasasvi V. Peruvemba, Shubham Rai, Kapil Ahuja, Akash Kumar, "RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021.
Bibtex
@INPROCEEDINGS{peruvemba2021,
author={Peruvemba, Yasasvi V. and Rai, Shubham and Ahuja, Kapil and Kumar, Akash},
booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
title={RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis},
month={Nov},
year={2021},
volume={},
number={}}Downloads
101_Final_ICCAD_Paper (1) [PDF]
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- 18. Andreas Krinke, Shubham Rai, Akash Kumar, Jens Lienig, "Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021. [Bibtex & Downloads]
Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies
Reference
Andreas Krinke, Shubham Rai, Akash Kumar, Jens Lienig, "Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2021.
Bibtex
@INPROCEEDINGS{krinke2021,
author={Krinke, Andreas and Rai, Shubham and Kumar, Akash and Lienig, Jens},
booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
title={Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies},
month={Nov},
year={2021},
volume={},
number={}}Downloads
iccad_2021_2 [PDF]
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- 17. Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi] [Bibtex & Downloads]
Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput
Reference
Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi]
Bibtex
@inproceedings{Bhattacharjee_2021,
doi = {10.1109/vlsi-soc53125.2021.9607015},
url = {https://doi.org/10.1109%2Fvlsi-soc53125.2021.9607015},
year = 2021,
month = {oct},
publisher = ,
author = {Abhiroop Bhattacharjee and Shubham Rai and Ansh Rupani and Michael Raitza and Akash Kumar},
title = {Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput},
booktitle = {2021 {IFIP}/{IEEE} 29th International Conference on Very Large Scale Integration ({VLSI}-{SoC})}
}Downloads
VLSI-SOC_2021 [PDF]
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- 16. Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 9, pp. 91564–91574, 2021. [doi] [Bibtex & Downloads]
A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies
Reference
Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 9, pp. 91564–91574, 2021. [doi]
Bibtex
@article{Rai_2021,
doi = {10.1109/access.2021.3092167},
url = {https://doi.org/10.1109%2Faccess.2021.3092167},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {9},
pages = {91564--91574},
author = {Shubham Rai and Pallab Nath and Ansh Rupani and Santosh Kumar Vishvakarma and Akash Kumar},
title = {A Survey of {FPGA} Logic Cell Designs in the Light of Emerging Technologies},
journal = {{IEEE} Access}
}Downloads
survey_FPGA_IEEE_access [PDF]
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- 15. Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar, "Vertical IP Protection of the Next-Generation Devices: Quo Vadis?" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] [Bibtex & Downloads]
Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Reference
Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar, "Vertical IP Protection of the Next-Generation Devices: Quo Vadis?" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]
Bibtex
@inproceedings{Rai_2021,
doi = {10.23919/date51398.2021.9474132},
url = {https://doi.org/10.23919%2Fdate51398.2021.9474132},
year = 2021,
month = {feb},
publisher = ,
author = {Shubham Rai and Siddharth Garg and Christian Pilato and Vladimir Herdt and Elmira Moussavi and Dominik Sisejkovic and Ramesh Karri and Rolf Drechsler and Farhad Merchant and Akash Kumar},
title = {Vertical {IP} Protection of the Next-Generation Devices: Quo Vadis?},
booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DATE_2021_SS_Security_Emerging(5) [PDF]
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- 14. Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] [Bibtex & Downloads]
Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies
Reference
Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]
Bibtex
@inproceedings{Rai_2021,
doi = {10.23919/date51398.2021.9474112},
url = {https://doi.org/10.23919%2Fdate51398.2021.9474112},
year = 2021,
month = {feb},
publisher = ,
author = {Shubham Rai and Heinz Riener and Giovanni De Micheli and Akash Kumar},
title = {Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies},
booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DATE_2021_preserving [PDF]
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- 13. Shubham Rai, Mengyun Liu, Anteneh Gebregiorgis, Debjyoti Bhattacharjee, Krishnendu Chakrabarty, Said Hamdioui, Anupam Chattopadhyay, Jens Trommer, Akash Kumar, "Perspectives on Emerging Computation-in-Memory Paradigms" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] [Bibtex & Downloads]
Perspectives on Emerging Computation-in-Memory Paradigms
Reference
Shubham Rai, Mengyun Liu, Anteneh Gebregiorgis, Debjyoti Bhattacharjee, Krishnendu Chakrabarty, Said Hamdioui, Anupam Chattopadhyay, Jens Trommer, Akash Kumar, "Perspectives on Emerging Computation-in-Memory Paradigms" (to appear), In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]
Bibtex
@inproceedings{Rai_2021,
doi = {10.23919/date51398.2021.9473976},
url = {https://doi.org/10.23919%2Fdate51398.2021.9473976},
year = 2021,
month = {feb},
publisher = ,
author = {Shubham Rai and Mengyun Liu and Anteneh Gebregiorgis and Debjyoti Bhattacharjee and Krishnendu Chakrabarty and Said Hamdioui and Anupam Chattopadhyay and Jens Trommer and Akash Kumar},
title = {Perspectives on Emerging Computation-in-Memory Paradigms},
booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DATE_2021_SS_In_Memory_Computing [PDF]
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- 12. Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. de Abreu, Isac de Souza Campos, Augusto Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit O. Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi] [Bibtex & Downloads]
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
Reference
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. de Abreu, Isac de Souza Campos, Augusto Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit O. Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Feb 2021. [doi]
Bibtex
@inproceedings{Rai_2021,
doi = {10.23919/date51398.2021.9473972},
url = {https://doi.org/10.23919%2Fdate51398.2021.9473972},
year = 2021,
month = {feb},
publisher = ,
author = {Shubham Rai and Walter Lau Neto and Yukio Miyasaka and Xinpei Zhang and Mingfei Yu and Qingyang Yi and Masahiro Fujita and Guilherme B. Manske and Matheus F. Pontes and Leomar S. da Rosa and Marilton S. de Aguiar and Paulo F. Butzen and Po-Chun Chien and Yu-Shan Huang and Hoa-Ren Wang and Jie-Hong R. Jiang and Jiaqi Gu and Zheng Zhao and Zixuan Jiang and David Z. Pan and Brunno A. de Abreu and Isac de Souza Campos and Augusto Berndt and Cristina Meinhardt and Jonata T. Carvalho and Mateus Grellert and Sergio Bampi and Aditya Lohana and Akash Kumar and Wei Zeng and Azadeh Davoodi and Rasit O. Topaloglu and Yuan Zhou and Jordan Dotzel and Yichi Zhang and Hanyu Wang and Zhiru Zhang and Valerio Tenace and Pierre-Emmanuel Gaillardon and Alan Mishchenko and Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
booktitle = {2021 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DATE_version_IWLS [PDF]
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- 11. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "RECON: Resource-Efficient CORDIC-Based Neuron Architecture", In IEEE Open Journal of Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 2, pp. 170–181, 2021. [doi] [Bibtex & Downloads]
RECON: Resource-Efficient CORDIC-Based Neuron Architecture
Reference
Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "RECON: Resource-Efficient CORDIC-Based Neuron Architecture", In IEEE Open Journal of Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 2, pp. 170–181, 2021. [doi]
Bibtex
@article{Raut_2021,
doi = {10.1109/ojcas.2020.3042743},
url = {https://doi.org/10.1109%2Fojcas.2020.3042743},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {2},
pages = {170--181},
author = {Gopal Raut and Shubham Rai and Santosh Kumar Vishvakarma and Akash Kumar},
title = {{RECON}: Resource-Efficient {CORDIC}-Based Neuron Architecture},
journal = {{IEEE} Open Journal of Circuits and Systems}
}Downloads
Recon [PDF]
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2020
- 10. Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi] [Bibtex & Downloads]
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits
Reference
Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi]
Bibtex
@article{Rai_2020,
doi = {10.1109/tetc.2020.3039375},
url = {https://doi.org/10.1109%2Ftetc.2020.3039375},
year = 2020,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Shubham Rai and Satwik Patnaik and Ansh Rupani and Johann Knechtel and Ozgur Sinanoglu and Akash Kumar},
title = {Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits},
journal = {{IEEE} Transactions on Emerging Topics in Computing}
}Downloads
TETC_Security_author-copy [PDF]
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- 9. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications", In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2020. [doi] [Bibtex & Downloads]
A CORDIC Based Configurable Activation Function for ANN Applications
Reference
Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications", In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2020. [doi]
Abstract
An efficient ASIC-based hardware design of activation function (AF) in neural networks faces the challenge of offering functional configurability and limited chip area. Therefore an area-efficient configurable architecture for an AF is imperative to fully harness the parallel processing capacity of an ASIC in contrast to a general-purpose processor. To address this, we propose a configurable AF based on the shift-and-add algorithm, collectively known as Co-ordinate Rotation Digital Computer(CORDIC) algorithm. The proposed versatile configurable activation function is designed using CORDIC architecture and implements both tan hyperbolic and sigmoid function. The derived model is synthesized and verified at 45nm technology. Further, in order to address leakage issues at lower technology nodes, we exploit the power-gating technique for the proposed AF based on CORDIC architecture. Our circuit design is extracted in cadence virtuoso and simulated for all physical parameters. With respect to the state-of-the-art, our design architecture shows improvement by 29% in area, 42% in power dissipation and 20% in latency. The used power gating technique saves 30% static power with minimal area overhead. The Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that mean and σ deviation are 180.73µW and 51.7µW respectively which is 60% of the state-of-the-art.
Bibtex
@inproceedings{Raut_2020,
doi = {10.1109/isvlsi49217.2020.00024},
url = {https://doi.org/10.1109%2Fisvlsi49217.2020.00024},
year = 2020,
month = {jul},
publisher = ,
author = {Gopal Raut and Shubham Rai and Santosh Kumar Vishvakarma and Akash Kumar},
title = {A {CORDIC} Based Configurable Activation Function for {ANN} Applications},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
}Downloads
ISVLSI 2020 Paper [PDF]
Permalink
- 8. Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi] [Bibtex & Downloads]
DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies
Reference
Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi]
Bibtex
@inproceedings{Rai_2020,
doi = {10.23919/date48585.2020.9116216},
url = {https://doi.org/10.23919%2Fdate48585.2020.9116216},
year = 2020,
month = {mar},
publisher = ,
author = {Shubham Rai and Michael Raitza and Siva Satyendra Sahoo and Akash Kumar},
title = {{DiSCERN}: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DiSCERN_DATE_2020 [PDF]
Permalink
- 7. Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies", [Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)], no. CONF, 2020. [Bibtex & Downloads]
XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies
Reference
Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar, "XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies", [Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)], no. CONF, 2020.
Bibtex
@inproceedings{rai2020xmg,
title={XMG-based Logic Synthesis for Emerging Reconfigurable Nanotechnologies},
author={Rai, Shubham and Riener, Heinz and De Micheli, Giovanni and Kumar, Akash},
booktitle={[Proceedings of the 29th International Workshop on Logic & Synthesis (IWLS 2020)]},
number={CONF},
year={2020}
}Downloads
XMG__Logic_Synthesis_Primitives_Exploring_Self_Duality [PDF]
Permalink
2019
- 6. Ansh Rupani, Shubham Rai, Akash Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: 2019 22nd Euromicro Conference on Digital System Design (DSD), IEEE, Aug 2019. [doi] [Bibtex & Downloads]
Exploiting Emerging Reconfigurable Technologies for Secure Devices
Reference
Ansh Rupani, Shubham Rai, Akash Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: 2019 22nd Euromicro Conference on Digital System Design (DSD), IEEE, Aug 2019. [doi]
Bibtex
@inproceedings{Rupani_2019,
doi = {10.1109/dsd.2019.00107},
url = {https://doi.org/10.1109%2Fdsd.2019.00107},
year = 2019,
month = {aug},
publisher = ,
author = {Ansh Rupani and Shubham Rai and Akash Kumar},
title = {Exploiting Emerging Reconfigurable Technologies for Secure Devices},
booktitle = {2019 22nd Euromicro Conference on Digital System Design ({DSD})}
}Downloads
DSD_final [PDF]
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- 5. Shubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2019. [doi] [Bibtex & Downloads]
Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies
Reference
Shubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2019. [doi]
Bibtex
@inproceedings{Rai_2019,
doi = {10.1109/isvlsi.2019.00123},
url = {https://doi.org/10.1109%2Fisvlsi.2019.00123},
year = 2019,
month = {jul},
publisher = ,
author = {Shubham Rai and Ansh Rupani and Pallab Nath and Akash Kumar},
title = {Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
}Downloads
ISVLSI [PDF]
Permalink
- 4. Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 27, no. 3, pp. 560–572, Mar 2019. [doi] [Bibtex & Downloads]
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors
Reference
Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 27, no. 3, pp. 560–572, Mar 2019. [doi]
Bibtex
@article{Rai_2019,
doi = {10.1109/tvlsi.2018.2884646},
url = {https://doi.org/10.1109%2Ftvlsi.2018.2884646},
year = 2019,
month = {mar},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {27},
number = {3},
pages = {560--572},
author = {Shubham Rai and Jens Trommer and Michael Raitza and Thomas Mikolajick and Walter M. Weber and Akash Kumar},
title = {Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors},
journal = {{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}
}Downloads
08580544 [PDF]
Related Paths
Permalink
2018
- 3. Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?", Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi] [Bibtex & Downloads]
Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?
Reference
Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?", Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi]
Bibtex
@inproceedings{Rai:2018:ERN:3240765.3243472,
author = {Rai, Shubham and Srinivasa, Srivatsa and Cadareanu, Patsy and Yin, Xunzhao and Hu, Xiaobo Sharon and Gaillardon, Pierre-Emmanuel and Narayanan, Vijaykrishnan and Kumar, Akash},
title = {Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?},
booktitle = {Proceedings of the International Conference on Computer-Aided Design},
series = {ICCAD '18},
year = {2018},
month = {November},
isbn = {978-1-4503-5950-4},
location = {San Diego, California},
pages = {13:1--13:8},
articleno = {13},
numpages = {8},
url = {http://doi.acm.org/10.1145/3240765.3243472},
doi = {10.1145/3240765.3243472},
acmid = {3243472},
publisher = {ACM},
address = {New York, NY, USA},
}Downloads
PID5531423 [PDF]
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- 2. Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] [Bibtex & Downloads]
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs
Reference
Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]
Bibtex
@inproceedings{Rai_2018,
doi = {10.23919/date.2018.8342080},
url = {https://doi.org/10.23919%2Fdate.2018.8342080},
year = 2018,
month = {mar},
publisher = ,
author = {Shubham Rai and Ansh Rupani and Dennis Walter and Michael Raitza and Andre Heinzig and Tim Baldauf and Jens Trommer and Christian Mayr and Walter M. Weber and Akash Kumar},
title = {A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable {FETs}},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
Physical_Synthesis_DATE_2018 [PDF]
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- 1. Shubham Rai, Michael Raitza, Akash Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] [Bibtex & Downloads]
Technology mapping flow for emerging reconfigurable silicon nanowire transistors
Reference
Shubham Rai, Michael Raitza, Akash Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]
Bibtex
@inproceedings{Rai_2018,
doi = {10.23919/date.2018.8342110},
url = {https://doi.org/10.23919%2Fdate.2018.8342110},
year = 2018,
month = {mar},
publisher = ,
author = {Shubham Rai and Michael Raitza and Akash Kumar},
title = {Technology mapping flow for emerging reconfigurable silicon nanowire transistors},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
Technology_Mapping_DATE_2018 [PDF]
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