Publications

• 2020

• 8. G. Raut, S. Rai, S. K. Vishvakarma, A. Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications" , In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 78-83, July 2020. (Best paper nominee) [doi] [Bibtex & Downloads]

  A CORDIC Based Configurable Activation Function for ANN Applications

  Reference

  G. Raut, S. Rai, S. K. Vishvakarma, A. Kumar, "A CORDIC Based Configurable Activation Function for ANN Applications" , In Proceeding: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 78-83, July 2020. (Best paper nominee) [doi]

  Abstract

  An efficient ASIC-based hardware design of activation function (AF) in neural networks faces the challenge of offering functional configurability and limited chip area. Therefore an area-efficient configurable architecture for an AF is imperative to fully harness the parallel processing capacity of an ASIC in contrast to a general-purpose processor. To address this, we propose a configurable AF based on the shift-and-add algorithm, collectively known as Co-ordinate Rotation Digital Computer(CORDIC) algorithm. The proposed versatile configurable activation function is designed using CORDIC architecture and implements both tan hyperbolic and sigmoid function. The derived model is synthesized and verified at 45nm technology. Further, in order to address leakage issues at lower technology nodes, we exploit the power-gating technique for the proposed AF based on CORDIC architecture. Our circuit design is extracted in cadence virtuoso and simulated for all physical parameters. With respect to the state-of-the-art, our design architecture shows improvement by 29% in area, 42% in power dissipation and 20% in latency. The used power gating technique saves 30% static power with minimal area overhead. The Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that mean and σ deviation are 180.73µW and 51.7µW respectively which is 60% of the state-of-the-art.

  Bibtex

  @INPROCEEDINGS{9155065,
  author={G. {Raut} and S. {Rai} and S. K. {Vishvakarma} and A. {Kumar}},
  booktitle={2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
  title={A CORDIC Based Configurable Activation Function for ANN Applications},
  year={2020},
  pages={78-83},
  abstract={An efficient ASIC-based hardware design of activation function (AF) in neural networks faces the challenge of offering functional configurability and limited chip area. Therefore an area-efficient configurable architecture for an AF is imperative to fully harness the parallel processing capacity of an ASIC in contrast to a general-purpose processor. To address this, we propose a configurable AF based on the shift-and-add algorithm, collectively known as Co-ordinate Rotation Digital Computer(CORDIC) algorithm. The proposed versatile configurable activation function is designed using CORDIC architecture and implements both tan hyperbolic and sigmoid function. The derived model is synthesized and verified at 45nm technology. Further, in order to address leakage issues at lower technology nodes, we exploit the power-gating technique for the proposed AF based on CORDIC architecture. Our circuit design is extracted in cadence virtuoso and simulated for all physical parameters. With respect to the state-of-the-art, our design architecture shows improvement by 29% in area, 42% in power dissipation and 20% in latency. The used power gating technique saves 30% static power with minimal area overhead. The Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that mean and σ deviation are 180.73µW and 51.7µW respectively which is 60% of the state-of-the-art.},
  keywords={Computer architecture;Hardware;Mathematical model;Biological neural networks;Neurons;Delays;Computational modeling;Artificial neural network;ASIC;CORDIC;compute efficiency;configurable architecture;multi activation function},
  doi={10.1109/ISVLSI49217.2020.00024},
  ISSN={2159-3477},
  month={July},
  }
  

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  ISVLSI 2020 Paper [PDF]

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• 7. S. Rai, M. Raitza, S. S. Sahoo, A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]

  DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES

  Reference

  S. Rai, M. Raitza, S. S. Sahoo, A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020.

  Bibtex

  @INPROCEEDINGS{date_Shubham,
  author={S. Rai and M. Raitza and S. S. Sahoo and A. Kumar},
  booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES},
  year={2020},
  month={March},}
  

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  DiSCERN_DATE_2020 [PDF]

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• 2019

• 6. A. Rupani, S. Rai, A. Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices" , In Proceeding: Euromicro DSD, August 2019. [Bibtex & Downloads]

  Exploiting Emerging Reconfigurable Technologies for Secure Devices

  Reference

  A. Rupani, S. Rai, A. Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices" , In Proceeding: Euromicro DSD, August 2019.

  Bibtex

  @InProceedings{Rai2019a,
  author = {A. Rupani and S. Rai and A. Kumar},
  title = {Exploiting Emerging Reconfigurable Technologies for Secure Devices},
  booktitle = {Euromicro DSD},
  year = {2019},
  month = {August},
  owner = {shubham},
  timestamp = {2018.04.26},
  }
  

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  DSD_final [PDF]

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• 5. S. Rai, A. Rupani, P. Nath, A. Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies" , In Proceeding: ISVLSI, July 2019. [Bibtex & Downloads]

  Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies

  Reference

  S. Rai, A. Rupani, P. Nath, A. Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies" , In Proceeding: ISVLSI, July 2019.

  Bibtex

  @InProceedings{Rai2019,
  Title = {Hardware Watermarking Using Polymorphic Inverter
  Designs Based On Reconfigurable Nanotechnologies},
  Author = {S. Rai and A. Rupani and P. Nath and A. Kumar},
  Booktitle = {ISVLSI},
  Year = {2019},
  Month = {July},
  Owner = {shubham},
  Timestamp = {2018.04.26}
  }
  

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  ISVLSI [PDF]

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• 4. S. Rai, J. Trommer, M. Raitza, T. Mikolajick, W. M. Weber, A. Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors" , In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 560-572, March 2019. [doi] [Bibtex & Downloads]

  Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

  Reference

  S. Rai, J. Trommer, M. Raitza, T. Mikolajick, W. M. Weber, A. Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors" , In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 560-572, March 2019. [doi]

  Bibtex

  @ARTICLE{8580544,
  author={S. {Rai} and J. {Trommer} and M. {Raitza} and T. {Mikolajick} and W. M. {Weber} and A. {Kumar}},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  title={Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors},
  year={2019},
  volume={27},
  number={3},
  pages={560-572},
  keywords={elemental semiconductors;field effect transistor circuits;logic circuits;logic design;logic gates;nanoelectronics;nanowires;germanium nanowire-based reconfigurable field-effect transistors;silicon nanowire-based reconfigurable field-effect transistors;power metric;arithmetic logic unit-based design;silicon nanowire reconfigurable FETs;CMOS reference design;normalized circuit delay;reconfigurable multifunctional circuit;efficient circuit designs;reconfigurable nanowire technology;functionally enhanced logic gates;exemplary designs;suboptimal designs;contemporary CMOS circuit designs;computational unit;multiple functionalities;reconfigurable nanotechnologies;runtime-reconfigurable field-effect transistors;Logic gates;Circuit synthesis;Silicon;CMOS technology;Delays;Field effect transistors;Functionally enhanced logic gates;multi-independent gate reconfigurable field-effect transistor (MIGRFET);RFET;reconfigurable transistor;silicon nanowire (SiNW) transistor;three-independent gate field-effect transistor (TIGFET)},
  doi={10.1109/TVLSI.2018.2884646},
  ISSN={1063-8210},
  month={March},}
  

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• 2018

• 3. Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?" , Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi] [Bibtex & Downloads]

  Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?

  Reference

  Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar, "Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?" , Proceedings of the International Conference on Computer-Aided Design, ACM, pp. 13:1–13:8, New York, NY, USA, November 2018. [doi]

  Bibtex

  @inproceedings{Rai:2018:ERN:3240765.3243472,
  author = {Rai, Shubham and Srinivasa, Srivatsa and Cadareanu, Patsy and Yin, Xunzhao and Hu, Xiaobo Sharon and Gaillardon, Pierre-Emmanuel and Narayanan, Vijaykrishnan and Kumar, Akash},
  title = {Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics?},
  booktitle = {Proceedings of the International Conference on Computer-Aided Design},
  series = {ICCAD '18},
  year = {2018},
  month = {November},
  isbn = {978-1-4503-5950-4},
  location = {San Diego, California},
  pages = {13:1--13:8},
  articleno = {13},
  numpages = {8},
  url = {http://doi.acm.org/10.1145/3240765.3243472},
  doi = {10.1145/3240765.3243472},
  acmid = {3243472},
  publisher = {ACM},
  address = {New York, NY, USA},
  }
  

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  PID5531423 [PDF]

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• 2. S. Rai, M. Raitza, A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), vol. , no. , pp. 767-772, March 2018. [doi] [Bibtex & Downloads]

  Technology mapping flow for emerging reconfigurable silicon nanowire transistors

  Reference

  S. Rai, M. Raitza, A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), vol. , no. , pp. 767-772, March 2018. [doi]

  Bibtex

  @INPROCEEDINGS{8342110,
  author={S. Rai and M. Raitza and A. Kumar},
  booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={Technology mapping flow for emerging reconfigurable silicon nanowire transistors},
  year={2018},
  volume={},
  number={},
  pages={767-772},
  keywords={CMOS logic circuits;elemental semiconductors;logic design;logic gates;nanoelectronics;nanowires;reconfigurable architectures;silicon;transistor circuits;CMOS based mapping;CMOS flow;HOF;Si;SiNW based genlib;SiNW based logic design;SiNW based logic gates;SiNW transistors;XOR logic family;ambipolar transistors;area-optimized technology mapping;conventional circuit design-flow;efficient circuit designs;electrical properties;extended functionality;functional flexibility;higher order functions;modified ABC tool;open source license;reconfigurable silicon nanowire transistors;single logical output;static layout;technology mapping flow;CMOS technology;Logic circuits;Logic gates;Optimization;Silicon;Tools;Transistors},
  doi={10.23919/DATE.2018.8342110},
  ISSN={},
  month={March},}
  

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• 1. S. Rai, A. Rupani, D. Walter, M. Raitza, A. Heinzig, T. Baldauf, J. Trommer, C. Mayr, W. M. Weber, A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), vol. , no. , pp. 605-608, March 2018. [doi] [Bibtex & Downloads]

  A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

  Reference

  S. Rai, A. Rupani, D. Walter, M. Raitza, A. Heinzig, T. Baldauf, J. Trommer, C. Mayr, W. M. Weber, A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), vol. , no. , pp. 605-608, March 2018. [doi]

  Bibtex

  @INPROCEEDINGS{8342080,
  author={S. Rai and A. Rupani and D. Walter and M. Raitza and A. Heinzig and T. Baldauf and J. Trommer and C. Mayr and W. M. Weber and A. Kumar},
  booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs},
  year={2018},
  volume={},
  number={},
  pages={605-608},
  keywords={field effect transistors;lithography;logic design;logic gates;nanowires;Library Exchange Format;SiNW based RFETs;SiNW based circuits;circuit designers;complete design flow;computational unit;early technology evaluation;fully symmetrical reconfigurable transistors;functionally enhanced transistors;gate terminal;independent gates;lithography steps;logic gates;logic synthesis;n-type functionality;p-type functionality;physical synthesis flow;program gate;silicon nanowire based reconfigurable FETs;silicon nanowire based reconfigurable field-effect transistors;Layout;Logic gates;Mathematical model;Nanoscale devices;Silicon;Tools;Transistors},
  doi={10.23919/DATE.2018.8342080},
  ISSN={},
  month={March},}
  

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