Zahra Ebrahimi




Visitor's Address

+49 351 463-40819

+49 (0)351 463-39995

Helmholtzstrasse 18, BAR-III62

Zahra Ebrahimi works as a research associate under the DFG-granted project "ReAp: Run-time Reconfigurable Approximate Architecture". She obtained her B.Sc. and M.Sc. degrees from Sharif University of Technology in Iran, where she also worked as a researcher in Data Storage, Networks, & Processing (DSN) LAB. Her research interests include reconfigurable computing, approximate computing, and embedded systems, and exploring a variety of application domains!

Google Scholar


Topics for thesis, master project, SHK/WHK, internship

These subjects are based on our current publications which will be extended for journal submissions in few months (Projects are adaptable depending on the level).

Requirements: High Motivation :), C++/Python, Verilog/VHDL, High-Level Synthesis
Beneficial: Background in machine learning, image processing, or other arbitrary domains

Cross-Layer Approximation of Neural Networks

In the upcoming era of Internet of Things (IoT), Federated Learning and Distributed Inference are visioned to be the pillars and key enablers for real-time processing. To enable such compute-intensive workload at the edge, the structure of NNs should be optimized without compromising the final quality of results. In this context, Approximate Computing techniques have shown to provide highly beneficial solutions by exploiting the inherent error resiliency of ML applications. Considering such potentials, the main idea in this project is to apply various approximations, efficiently, to reduce the area/power/energy of NNs and boost their performance.


High-Speed Acceleration of Object Detection and Continuous Tracking Applications

Object detection and continuous tracking are ubiquitously used in a variety of applications, from Indoor Positioning and self-tracking of Unmanned Aerial Vehicles such as Drones to Surveillance and Biometric Security use-cases. An interesting example of which is human eye's Iris, it is the most reliable biometric after DNA and has an ever-increasing potential to be ubiquitously used in many biometric/AI marketing domains such as E-banking, attendance, or presence tracking in shops, airport, etc. In particular iris-scanning related market is expected to be doubled by 2024, worth $52 Billion. The basic structure of this application shows a degree of error resiliency. The common feature of all these applications is the error-resiliency of their algorithms to approximation techniques. Our aim in this topic is then, to utilize such potentials to enable real-time processing in energy-constrained IoT edge nodes.

Light-Weight Accelerator for Anomaly Detection in Health-Monitoring Application (ECG/EEG)

Motivated by the fact that ~36% of global death stems from heart anomalies (especially in Germany as one of the first EU-countries for high heart-related diseases), the market for health monitoring apps and gadgets is growing tremendously. Interesting feature of an ECG-monitoring algorithm is its high resiliency to errors and also the fact that full accuracy is needed 24/7 (e.g. in less-activate/sleeping periods). Considering such potentials, the main idea is to apply various approximations and also optimizations on the basic structure of ECG-monitoring application to improve its performance and reduce area/power/energy cost. Such light-weight health-monitoring algorithm can be broadly used by many companies as an app in smart phone/smart watch or even as an stand alone gadgets attached to the body.

Reconfigurable Hard Logic Design

The significant increase of static power in nano-CMOS era, has put a Power Wall to the aggressive growth of transistor density in a single die. This issue referred o as the Era of Dark Silicon, as not all of transistors can be utilized at the same time. In particular, the significant traction toward edge-computing highly encourages using small-scale and energy-efficient IoT devices. In this context, cutting-edge trends have shown great resource/performance improvement can be achieved through simple Reconfigurable Hard Logic (RHL) cells. Such cells are designed to be replaced with energy-hungry SRAM-based Look-Up-Tables (LUTs) in platforms like FPGAs.




Approximate CGRA for Bio-Signal Processing (ISCAS 2021)

Approximate SIMD Multiplier-Divider (GLSVLSI 2020)

Power-Efficient Hard Logic Design for FPGAs (TC 2017)


  • 2021

  • 6. Zahra Ebrahimi, Akash Kumar, "BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge", In Proceeding: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. [Bibtex & Downloads]
  • 2020

  • 5. Zahra Ebrahimi Mamaghani, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", In Proceeding: 30th 2020 ACM Great Lakes Symposium on VLSI (GLSVLSI), September 2020. [Bibtex & Downloads]
  • 4. Zahra Ebrahimi Mamaghani, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2020. [Bibtex & Downloads]
  • 2014

  • 1. Ali Ahari, Behnam Khaleghi, Zahra Ebrahimi, Hossein Asadi, Mehdi B. Tahoori, "Towards dark silicon era in FPGAs using complementary hard logic design", In Proceeding: 2014 24th International Conference on Field Programmable Logic and Applications (FPL), IEEE, Sep 2014. [doi] [Bibtex & Downloads]



Hossein Asadi, Zahra Ebrahimi, and Behnam Khaleghi, ”Programmable Logic Design”, US Provisional Patent, US10312918B2, 2017 (Renewed 2019).


Zeinab Seifoori, Zahra Ebrahimi, Behnam Khaleghi, and Hossein Asadi. Introduction to emerging SRAM-based FPGA Architectures in Dark Silicon Era. In Advances in Computers, vol. 110, Elsevier, 2018.