Zahra Ebrahimi




Visitor's Address

+49 351 463-40819

+49 (0)351 463-39995

Helmholtzstrasse 18, BAR-III62


Zahra Ebrahimi works as a research associate under the DFG-granted project "ReAp: Run-time Reconfigurable Approximate Architecture". She obtained her B.Sc. and M.Sc. degrees from Sharif University of Technology in Iran, where she also worked as a researcher in Data Storage, Networks, & Processing (DSN) LAB. Her research interests include reconfigurable computing, approximate computing, and embedded systems.


Complete list of publications​


Google Scholar

DBLP Database



Topics for thesis, SHK/WHK, internship: 

These subjects are based on our current publications which will be extended for journal submissions in few month (Projects are adaptable depending on level).

1. From Biometric Security to Health Anomaly Detection: A Light-Weight Approximate Accelerator for Iris Recognition:

Iris is the most reliable biometric after DNA and has an ever-increasing potential to be ubiquitously used in many biometric/AI marketing domains such as E-banking, attendance or presence tracking in shops, airport, etc. In particular iris-scanning related market is expected to be doubled by 2024, worth $52 Billion. The basic structure of this application shows a degree of error resiliency. Considering such potentials, the main idea is to apply various approximations and also optimizations on the basic structure of iris-scanning to improve its performance and reduce area/power/energy cost.

2. Light-Weight Approximate Accelerator for ECG Anomaly Detection:

Motivated by the fact that ~36% of global death stems from heart anomalies (especially in Germany as one of the first EU-countries for high heart-related diseases), the market for health monitoring apps and gadgets is growing tremendously. Interesting feature of an ECG-monitoring algorithm is its high resiliency to errors and also the fact that full accuracy is needed 24/7 (e.g. in less-activate/sleeping periods). Considering such potentials, the main idea is to apply various approximations and also optimizations on the basic structure of ECG-monitoring application to improve its performance and reduce area/power/energy cost. Such light-weight health-monitoring algorithm can be broadly used by many companies as an app in smart phone/smart watch or even as an stand alone gadgets attached to the body.

3. Approximate multipliers:

Approximate multipliers are broadly in used in many error-resilient programs such as machine learning and multimedia as multiplication is the key operation in their computational core. Resource metrics such as performance, power and energy dissipation is of more importance in these applications as the output can tolerate a relaxed precision. Accelerators, such as FPGAs, are prime candidates for implementation of aforementioned multiplication-exhaustive programs. In this project, we will design resource- and performance-efficient multiplier for FPGAs/ASIC designs. One interesting approach to implement multiplication is to translate it to simple shift and addition using approximate algorithms such as Mitchell’s.

4. Approximate Dividers:

Approximate dividers have recently gained extreme attention in top conferences for two reasons. First, although they are less frequent than multiplication, they are still inevitable operations in ever-increasing machine learning and multimedia applications. Second, their resource consumption and latency are multiple times of multipliers which made them the bottleneck of application (in energy and speed). However, our analysis show with approximation techniques, we can improve resource/performance metrics substantially, while imposing a negligible impact on the accuracy of NN classification or image processing kernels.

5. Reconfigurable Hard Logic Design:

The significant increase of static power in nano-CMOS era, has put a Power Wall to the aggressive grow of transistor density in a single die. This issue referred o as the Era of Dark Silicon, as not all of transistors can be utilized at the same time. In particular, the significant traction toward edge-computing, highly encourages using small-scale and energy-efficient IoT devices. In this context, cutting-edge trends have shown great resource/performance improvement can be achieved through simple Reconfigurable Hard Logic (RHL) cells. Such cells are designed to be replaced with energy-hungry SRAM-based Look-Up-Tables (LUTs) in platforms like FPGAs.

Requirements: C++/Python, Verilog/VHDL

Beneficial: Background in machine learning, image processing



  • 2020

  • 2. Zahra Ebrahimi Mamaghani, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy" , In Proceeding: 30th 2020 ACM Great Lakes Symposium on VLSI (GLSVLSI), September 2020. [Bibtex & Downloads]
  • 1. Zahra Ebrahimi Mamaghani, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy" , In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2020. [Bibtex & Downloads]