cfaed Publications
Tutorial: Hardware-Aware Compilation and Simulation for In-Memory Computing
Reference
Asif Ali Khan, Hadjer Benmeziane, Hamid Farzaneh, João Paulo C. de Lima, William Simon, Yiyu Shi, Zheyu Yan, Abu Sebastian, X. Sharon Hu, Jeronimo Castrillon, Corey Lammie, "Tutorial: Hardware-Aware Compilation and Simulation for In-Memory Computing", Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'25), Association for Computing Machinery, pp. 31-–32, New York, NY, USA, Oct 2025. [doi]
Abstract
This brief presents an overview of recent tools and research efforts aimed at enhancing the programmability and reliability of In-Memory Computing (IMC)-based systems. We discuss hardware-aware training techniques that improve model resilience to analog device imperfections, and explore mapping strategies that balance accuracy and performance for heterogeneous IMC-based accelerators. Additionally, we examine a compiler framework that abstracts hardware complexities and enables seamless integration of these accelerators into existing deployment pipelines. By combining these approaches with advanced simulation tools, we propose an end-to-end workflow that facilitates the practical deployment and optimization of IMC technologies across diverse memory types and architectural designs.
Bibtex
author = {Khan, Asif Ali and Benmeziane, Hadjer and Farzaneh, Hamid and de Lima, João Paulo C. and Simon, William and Shi, Yiyu and Yan, Zheyu and Sebastian, Abu and Hu, X. Sharon and Castrillon, Jeronimo and Lammie, Corey},
booktitle = {Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'25)},
title = {Tutorial: Hardware-Aware Compilation and Simulation for In-Memory Computing},
doi = {10.1145/3742872.3758333},
isbn = {9798400719912},
location = {Taipei International Convention Center (TICC), Taipei, Taiwan},
pages = {31-–32},
publisher = {Association for Computing Machinery},
series = {CASES '25},
url = {https://doi.org/10.1145/3742872.3758333},
abstract = {This brief presents an overview of recent tools and research efforts aimed at enhancing the programmability and reliability of In-Memory Computing (IMC)-based systems. We discuss hardware-aware training techniques that improve model resilience to analog device imperfections, and explore mapping strategies that balance accuracy and performance for heterogeneous IMC-based accelerators. Additionally, we examine a compiler framework that abstracts hardware complexities and enables seamless integration of these accelerators into existing deployment pipelines. By combining these approaches with advanced simulation tools, we propose an end-to-end workflow that facilitates the practical deployment and optimization of IMC technologies across diverse memory types and architectural designs.},
address = {New York, NY, USA},
numpages = {2},
year = {2025},
month = oct,
}
Downloads
2510_Khan_CASES-Tutorial [PDF]
Permalink
https://cfaed.tu-dresden.de/publications?pubId=3868


