Robert Khasanov





Visitor's Address

+49 (0)351 463 39978

+49 (0)351 463 39995

Helmholtzstrasse 18
3rd floor, Room BAR III 58
01069 Dresden

Curriculum Vitae

Robert Khasanov has received his Bachelor's and Master’s degree in Computer Science from Moscow Institute of Physics and Technology in 2012 and 2014 respectively.  During the study, he also held positions at Intel where he was working on optimising binary translator system, and then in LLVM compiler project. In 2015 Robert carried out an internship at Scalable Parallel Computing Lab (ETH Zurich) where he was working on optimal data replication in fault tolerant distributed databases. Currently, he is working on the languages and compilers for energy-efficient programming, with particular focus on dataflow languages with implicit and explicit parallelism, compiler-runtime interaction and energy optimisations.

Student Thesis Topics

Some possible topics for Bachelor/Master/Diploma Thesis or SHK/WHK in the following directions:

  • A design-time/run-time system for energy-efficient execution of multiple applications

    At the Chair for Compiler Construction we are developing hybrid system called TETRiS, which aims at energy-efficient and predictable execution of multiple applications. The system exploits inherited symmetries in hardware and software to reduce the design space exploration. The approach consists of two parts, at design-time the set of pareto-optimal configurations is generated, and then depending on the current workload the configurations are selected and transformed at run-time.

    Possible project topics include:
    • Subgraph isomorphism on heterogeneous platforms
    • Efficient generation of pareto-optimal configurations
    • Symmetry analysis of the applications 

  • Implicit parallelism in Kahn Process Networks (KPN)

    Kahn process networks (KPN) are an abstraction for modeling computation which makes communication patterns explicit. They can be used to analyze applications and automatically deploy it to diverse, parallel and heterogeneous platforms. An extension of implicit parallelism for KPN allows applications to change the number of used resources at run-time in malleable way, which in turn allows applications to adapt to the changes in the environment. 

    Possible project topics include:
    • Code generation of KPN with implicit parallelism (C++ knowledge is required, LLVM is optional)
    • Implicit parallelism on a distributed memory model
    • Using SIMD instructions for KPN with implicit parallelism
    • Run-time adaptivity of KPN application with implicit parallelism in TETRiS (see previous item)

Please contact me if you are interested to work on any of these topics.


  • 2021

  • Robert Khasanov, Julian Robledo, Christian Menard, Andres Goens, Jeronimo Castrillon, "Domain-specific hybrid mapping for energy-efficient baseband processing in wireless networks", In ACM Transactions on Embedded Computing Systems (TECS). Special issue of the International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES), Association for Computing Machinery, vol. 20, no. 5s, New York, NY, USA, Sep 2021. [doi] [Bibtex & Downloads]
  • Christian Menard, Andrés Goens, Gerald Hempel, Robert Khasanov, Julian Robledo, Felix Teweleitt, Jeronimo Castrillon, "Mocasin—Rapid Prototyping of Rapid Prototyping Tools: A Framework for Exploring New Approaches in Mapping Software to Heterogeneous Multi-cores", Proceedings of the 2021 Drone Systems Engineering and Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with 16th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Association for Computing Machinery, pp. 66–73, New York, NY, USA, Jan 2021. (Video Presentation) [doi] [Bibtex & Downloads]
  • 2020

  • Robert Khasanov, Jeronimo Castrillon, "Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 909–914, Mar 2020. (Best paper award candidate E-Track, Video Presentation) [doi] [Bibtex & Downloads]
  • 2018

  • Robert Khasanov, Andrés Goens, Jeronimo Castrillon, "Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap", Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'18), co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 20–25, New York, NY, USA, Jan 2018. [doi] [Bibtex & Downloads]
  • 2017

  • Andrés Goens, Robert Khasanov, Marcus Hähnel, Till Smejkal, Hermann Härtig, Jeronimo Castrillon, "TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings", Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES'17), ACM, pp. 11–20, New York, NY, USA, Jun 2017. [doi] [Bibtex & Downloads]
  • Markus Haehnel, Frehiwot Melak Arega, Waltenegus Dargie, Robert Khasanov, Jeronimo Castrillon, "Application Interference Analysis: Towards Energy-efficient Workload Management on Heterogeneous Micro-Server Architectures", Proceedings of the 7th International Workshop on Big Data in Cloud Performance (DCPerf'17), IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS), pp. 432-437, May 2017. [doi] [Bibtex & Downloads]
  • 2016

  • Andres Goens, Robert Khasanov, Jeronimo Castrillon, Simon Polstra, Andy Pimentel, "Why Comparing System-level MPSoC Mapping Approaches is Difficult: a Case Study", Proceedings of the IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), pp. 281-288, Ecole Centrale de Lyon, Lyon, France, Sep 2016. [doi] [Bibtex & Downloads]