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Tuan Duy Anh Nguyen |
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Phone Fax Visitor's Address |
tuan_duy_anh.nguyen1@tu-dresden.de +49 351 463-43725 +49 351 463-39995 Helmholtzstrasse 18, BAR-III76 |
Publications
2021
- 9. Behnaz Ranjbar, Tuan D. A. Nguyen, Alireza Ejlali, Akash Kumar, "Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 40, no. 10, pp. 2009-2023, October 2021. [doi] [Bibtex & Downloads]
Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform
Reference
Behnaz Ranjbar, Tuan D. A. Nguyen, Alireza Ejlali, Akash Kumar, "Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Institute of Electrical and Electronics Engineers (IEEE), vol. 40, no. 10, pp. 2009-2023, October 2021. [doi]
Bibtex
@article{Ranjbar_2020,
doi = {10.1109/tcad.2020.3033374},
url = {https://doi.org/10.1109%2Ftcad.2020.3033374},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {2009-2023},
volume={40},
number={10},
month ={October},
author = {Behnaz Ranjbar and Tuan D. A. Nguyen and Alireza Ejlali and Akash Kumar},
title = {Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}
}Downloads
TCAD3033374-power-aware-accepted [PDF]
Permalink
- 8. Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi] [Bibtex & Downloads]
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
Reference
Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi]
Bibtex
@article{Ullah_2021,
doi = {10.1109/les.2020.2995053},
url = {https://doi.org/10.1109%2Fles.2020.2995053},
year = 2021,
month = {jun},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {13},
number = {2},
pages = {41--44},
author = {Salim Ullah and Tuan Duy Anh Nguyen and Akash Kumar},
title = {Energy-Efficient Low-Latency Signed Multiplier for {FPGA}-Based Hardware Accelerators},
journal = {{IEEE} Embedded Systems Letters}
}Downloads
ESL_acc_multiplier [PDF]
Permalink
2020
- 7. Tuan D. A. Nguyen, Akash Kumar, "Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment", In Proceeding: 28th International Symposium on Field-Programmable Gate Arrays, February 2020. [Bibtex & Downloads]
Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment
Reference
Tuan D. A. Nguyen, Akash Kumar, "Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment", In Proceeding: 28th International Symposium on Field-Programmable Gate Arrays, February 2020.
Bibtex
@INPROCEEDINGS{tuanFPGA,
author={Tuan D. A. Nguyen and Akash Kumar},
booktitle={28th International Symposium on Field-Programmable Gate Arrays},
title={Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment},
year={2020},
month={February},}Downloads
serviceability-fpga-058-2020-camera_ready [PDF]
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2019
- 6. Nusrat Jahan Lisa, Tuan D. A. Nguyen, Dirk Habich, Akash Kumar, Wolfgang Lehner, "High-Throughput Bit Packing Compression", In Proceeding: Euromicro DSD, August 2019. [Bibtex & Downloads]
High-Throughput Bit Packing Compression
Reference
Nusrat Jahan Lisa, Tuan D. A. Nguyen, Dirk Habich, Akash Kumar, Wolfgang Lehner, "High-Throughput Bit Packing Compression", In Proceeding: Euromicro DSD, August 2019.
Bibtex
@InProceedings{nusrat19high,
author = {Nusrat Jahan Lisa and Tuan D. A. Nguyen and Dirk Habich and Akash Kumar and Wolfgang Lehner},
title = {High-Throughput Bit Packing Compression},
booktitle = {Euromicro DSD},
year = {2019},
month = {August},
owner = {Ranjbar},
}Downloads
dsd2019_fpga_crc [PDF]
Permalink
- 5. Behnaz Ranjbar, Tuan D. A. Nguyen, A. Ejlali, A. Kumar, "Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 546-553, August 2019. [doi] [Bibtex & Downloads]
Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems
Reference
Behnaz Ranjbar, Tuan D. A. Nguyen, A. Ejlali, A. Kumar, "Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems", In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 546-553, August 2019. [doi]
Bibtex
@InProceedings{ranjbar19online,
author = {Behnaz Ranjbar and Tuan D. A. Nguyen and A. Ejlali and A. Kumar},
title = {Online Peak Power and Maximum Temperature Management in Multi-Core Mixed-Criticality Embedded Systems},
booktitle = { Euromicro Conference on Digital System Design (DSD)},
year = {2019},
month = {August},
pages={546-553},
doi={10.1109/DSD.2019.00084},
owner = {Ranjbar},
}Downloads
Permalink
2018
- 4. Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Nguyen Duy Anh Tuan, Akash Kumar, Wolfgang Lehner, "Column Scan Optimization by Increasing Intra-Instruction Parallelism", Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA), July 2018. (Best Paper Award) [Bibtex & Downloads]
Column Scan Optimization by Increasing Intra-Instruction Parallelism
Reference
Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Nguyen Duy Anh Tuan, Akash Kumar, Wolfgang Lehner, "Column Scan Optimization by Increasing Intra-Instruction Parallelism", Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA), July 2018. (Best Paper Award)
Bibtex
@InProceedings{lisaDATA2018,
author = {Nusrat Jahan Lisa and Annett Ungethüm and Dirk Habich and Nguyen Duy Anh Tuan and Akash Kumar and Wolfgang Lehner},
title = {Column Scan Optimization by Increasing Intra-Instruction Parallelism},
booktitle = {Proceedings of the 7th International Conference on Data Science, Technology and Applications (DATA) },
month = {July},
year = {2018},
}Downloads
DATA_2018_47_CR (1) [PDF]
Permalink
- 3. Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018. [Bibtex & Downloads]
Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems
Reference
Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018.
Bibtex
@INPROCEEDINGS{dprLifeASPDAC,
author={Siva Satyendra Sahoo and Tuan Duy Anh Nguyen and B. Veeravalli and Akash Kumar},
booktitle={2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)},
title={Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems },
year={2018},
volume={},
number={},
pages={1-6},
keywords={Reconfigurable Computing, Dynamic Partial Reconfiguration, Integer Linear Programming, Network-on-Chip, FPGA Floorplanning},
month={Jan},}Downloads
ASPDAC-2018-siva [PDF]
Related Paths
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2016
- 2. Tuan D. A. Nguyen, Akash Kumar, "XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1-11, Aug 2016. [Bibtex & Downloads]
XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip
Reference
Tuan D. A. Nguyen, Akash Kumar, "XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip", In Proceeding: International Conference on Field Programmable Logic and Applications (FPL), pp. 1-11, Aug 2016.
Bibtex
@INPROCEEDINGS{xnocfpl2016,
author={Tuan D. A. Nguyen and Akash Kumar},
booktitle={International Conference on Field Programmable Logic and Applications (FPL)},
title={XNoC: A Non-intrusive TDM Circuit-Switched Network-on-Chip},
year={2016},
pages={1-11},
month={Aug}}Downloads
fpl_2016_xnoc [PDF]
Related Paths
Permalink
- 1. Tuan D. A. Nguyen, Akash Kumar, "PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems", In Proceeding: The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb 2016. [Bibtex & Downloads]
PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems
Reference
Tuan D. A. Nguyen, Akash Kumar, "PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems", In Proceeding: The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb 2016.
Bibtex
@inproceedings{tuan2016fpga,
title={PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems},
author={Tuan D. A. Nguyen and Akash Kumar},
booktitle={The 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)},
year={2016},
month={Feb},
organization={IEEE}
}Downloads
fp029-nguyenA [PDF]
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