Publications
2022
- 8. Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), vol. 39, no. 3, pp. 73–81, Jun 2022. [doi] [Bibtex & Downloads]
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy
×Reference
Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), vol. 39, no. 3, pp. 73–81, Jun 2022. [doi]
Bibtex
@article{Lohana_2022,
doi = {10.1109/mdat.2021.3063373},
url = {https://doi.org/10.1109%2Fmdat.2021.3063373},
year = 2022,
month = {jun},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {39},
number = {3},
pages = {73--81},
author = {Aditya Lohana and Ansh Rupani and Shubham Rai and Akash Kumar},
title = {Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy},
journal = {{IEEE} Design {\&} Test}
}Downloads
DandT [PDF]
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- 7. Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi] [Bibtex & Downloads]
END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator
×Reference
Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi]
Bibtex
@incollection{Rai_2022,
doi = {10.1007/978-3-031-16818-5_9},
url = {https://doi.org/10.1007%2F978-3-031-16818-5_9},
year = 2022,
publisher = {Springer Nature Switzerland},
pages = {175--203},
author = {Shubham Rai and Nishant Gupta and Abhiroop Bhattacharjee and Ansh Rupani and Michael Raitza and Jens Trommer and Thomas Mikolajick and Akash Kumar},
title = {{END}-{TRUE}: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator},
booktitle = {{VLSI}-{SoC}: Technology Advancement on {SoC} Design}
}Downloads
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2021
- 6. Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi] [Bibtex & Downloads]
Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput
×Reference
Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi]
Bibtex
@inproceedings{Bhattacharjee_2021,
doi = {10.1109/vlsi-soc53125.2021.9607015},
url = {https://doi.org/10.1109%2Fvlsi-soc53125.2021.9607015},
year = 2021,
month = {oct},
publisher = ,
author = {Abhiroop Bhattacharjee and Shubham Rai and Ansh Rupani and Michael Raitza and Akash Kumar},
title = {Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput},
booktitle = {2021 {IFIP}/{IEEE} 29th International Conference on Very Large Scale Integration ({VLSI}-{SoC})}
}Downloads
VLSI-SOC_2021 [PDF]
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- 5. Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 9, pp. 91564–91574, 2021. [doi] [Bibtex & Downloads]
A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies
×Reference
Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), vol. 9, pp. 91564–91574, 2021. [doi]
Bibtex
@article{Rai_2021,
doi = {10.1109/access.2021.3092167},
url = {https://doi.org/10.1109%2Faccess.2021.3092167},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {9},
pages = {91564--91574},
author = {Shubham Rai and Pallab Nath and Ansh Rupani and Santosh Kumar Vishvakarma and Akash Kumar},
title = {A Survey of {FPGA} Logic Cell Designs in the Light of Emerging Technologies},
journal = {{IEEE} Access}
}Downloads
survey_FPGA_IEEE_access [PDF]
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2020
- 4. Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi] [Bibtex & Downloads]
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits
×Reference
Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi]
Bibtex
@article{Rai_2020,
doi = {10.1109/tetc.2020.3039375},
url = {https://doi.org/10.1109%2Ftetc.2020.3039375},
year = 2020,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Shubham Rai and Satwik Patnaik and Ansh Rupani and Johann Knechtel and Ozgur Sinanoglu and Akash Kumar},
title = {Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits},
journal = {{IEEE} Transactions on Emerging Topics in Computing}
}Downloads
TETC_Security_author-copy [PDF]
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2019
- 3. Ansh Rupani, Shubham Rai, Akash Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: 2019 22nd Euromicro Conference on Digital System Design (DSD), IEEE, Aug 2019. [doi] [Bibtex & Downloads]
Exploiting Emerging Reconfigurable Technologies for Secure Devices
×Reference
Ansh Rupani, Shubham Rai, Akash Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: 2019 22nd Euromicro Conference on Digital System Design (DSD), IEEE, Aug 2019. [doi]
Bibtex
@inproceedings{Rupani_2019,
doi = {10.1109/dsd.2019.00107},
url = {https://doi.org/10.1109%2Fdsd.2019.00107},
year = 2019,
month = {aug},
publisher = ,
author = {Ansh Rupani and Shubham Rai and Akash Kumar},
title = {Exploiting Emerging Reconfigurable Technologies for Secure Devices},
booktitle = {2019 22nd Euromicro Conference on Digital System Design ({DSD})}
}Downloads
DSD_final [PDF]
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- 2. Shubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2019. [doi] [Bibtex & Downloads]
Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies
×Reference
Shubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Jul 2019. [doi]
Bibtex
@inproceedings{Rai_2019,
doi = {10.1109/isvlsi.2019.00123},
url = {https://doi.org/10.1109%2Fisvlsi.2019.00123},
year = 2019,
month = {jul},
publisher = ,
author = {Shubham Rai and Ansh Rupani and Pallab Nath and Akash Kumar},
title = {Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on {VLSI} ({ISVLSI})}
}Downloads
ISVLSI [PDF]
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2018
- 1. Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] [Bibtex & Downloads]
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs
×Reference
Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]
Bibtex
@inproceedings{Rai_2018,
doi = {10.23919/date.2018.8342080},
url = {https://doi.org/10.23919%2Fdate.2018.8342080},
year = 2018,
month = {mar},
publisher = ,
author = {Shubham Rai and Ansh Rupani and Dennis Walter and Michael Raitza and Andre Heinzig and Tim Baldauf and Jens Trommer and Christian Mayr and Walter M. Weber and Akash Kumar},
title = {A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable {FETs}},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
Physical_Synthesis_DATE_2018 [PDF]
Related Paths
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