Publications
2021
- 7. Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. [Bibtex & Downloads]
Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput
×Reference
Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021.
Bibtex
@INPROCEEDINGS{Bhattacharjee2021,
author={Bhattacharjee, Abhiroop and Rai, Shubham and Rupani, Ansh and Raitza, Michael and Kumar, Akash},
booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC)},
title={Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput},
year={2021},
month={Oct},
volume={},
number={}}Downloads
VLSI-SOC_2021 [PDF]
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- 6. Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Vishwakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, Jul 2021. [doi] [Bibtex & Downloads]
A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies
×Reference
Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Vishwakarma, Akash Kumar, "A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, Jul 2021. [doi]
Bibtex
@article{Rai_2021,
doi = {10.1109/access.2021.3092167},
url = {https://doi.org/10.1109%2Faccess.2021.3092167},
year = 2021,
month = jul,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Shubham Rai and Pallab Nath and Ansh Rupani and Santosh Vishwakarma and Akash Kumar},
title = {A Survey of {FPGA} Logic Cell Designs in the Light of Emerging Technologies},
journal = {{IEEE} Access}
}Downloads
survey_FPGA_IEEE_access [PDF]
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- 5. Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi] [Bibtex & Downloads]
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy
×Reference
Aditya Lohana, Ansh Rupani, Shubham Rai, Akash Kumar, "Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy", In IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi]
Bibtex
@article{Lohana_2021,
doi = {10.1109/mdat.2021.3063373},
url = {https://doi.org/10.1109%2Fmdat.2021.3063373},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Aditya Lohana and Ansh Rupani and Shubham Rai and Akash Kumar},
title = {Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy},
journal = {{IEEE} Design {\&} Test}
}Downloads
DandT [PDF]
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2020
- 4. Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi] [Bibtex & Downloads]
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits
×Reference
Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits", In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi]
Bibtex
@article{9264740,
doi = {10.1109/tetc.2020.3039375},
url = {https://doi.org/10.1109%2Ftetc.2020.3039375},
year = 2020,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Shubham Rai and Satwik Patnaik and Ansh Rupani and Johann Knechtel and Ozgur Sinanoglu and Akash Kumar},
title = {Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits},
journal = {{IEEE} Transactions on Emerging Topics in Computing}
}Downloads
TETC_Security_author-copy [PDF]
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2019
- 3. A. Rupani, S. Rai, A. Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: Euromicro DSD, August 2019. [Bibtex & Downloads]
Exploiting Emerging Reconfigurable Technologies for Secure Devices
×Reference
A. Rupani, S. Rai, A. Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices", In Proceeding: Euromicro DSD, August 2019.
Bibtex
@InProceedings{Rai2019a,
author = {A. Rupani and S. Rai and A. Kumar},
title = {Exploiting Emerging Reconfigurable Technologies for Secure Devices},
booktitle = {Euromicro DSD},
year = {2019},
month = {August},
owner = {shubham},
timestamp = {2018.04.26},
}Downloads
DSD_final [PDF]
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- 2. S. Rai, A. Rupani, P. Nath, A. Kumar, "Hardware Watermarking Using Polymorphic Inverter
Designs Based On Reconfigurable Nanotechnologies", In Proceeding: ISVLSI, July 2019. [Bibtex & Downloads]
Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies
×Reference
S. Rai, A. Rupani, P. Nath, A. Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies", In Proceeding: ISVLSI, July 2019.
Bibtex
@InProceedings{Rai2019,
Title = {Hardware Watermarking Using Polymorphic Inverter
Designs Based On Reconfigurable Nanotechnologies},
Author = {S. Rai and A. Rupani and P. Nath and A. Kumar},
Booktitle = {ISVLSI},
Year = {2019},
Month = {July},
Owner = {shubham},
Timestamp = {2018.04.26}
}Downloads
ISVLSI [PDF]
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2018
- 1. S. Rai, A. Rupani, D. Walter, M. Raitza, A. Heinzig, T. Baldauf, J. Trommer, C. Mayr, W. M. Weber, A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 605-608, March 2018. [doi] [Bibtex & Downloads]
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs
×Reference
S. Rai, A. Rupani, D. Walter, M. Raitza, A. Heinzig, T. Baldauf, J. Trommer, C. Mayr, W. M. Weber, A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 605-608, March 2018. [doi]
Bibtex
@INPROCEEDINGS{8342080,
author={S. Rai and A. Rupani and D. Walter and M. Raitza and A. Heinzig and T. Baldauf and J. Trommer and C. Mayr and W. M. Weber and A. Kumar},
booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs},
year={2018},
volume={},
number={},
pages={605-608},
keywords={field effect transistors;lithography;logic design;logic gates;nanowires;Library Exchange Format;SiNW based RFETs;SiNW based circuits;circuit designers;complete design flow;computational unit;early technology evaluation;fully symmetrical reconfigurable transistors;functionally enhanced transistors;gate terminal;independent gates;lithography steps;logic gates;logic synthesis;n-type functionality;p-type functionality;physical synthesis flow;program gate;silicon nanowire based reconfigurable FETs;silicon nanowire based reconfigurable field-effect transistors;Layout;Logic gates;Mathematical model;Nanoscale devices;Silicon;Tools;Transistors},
doi={10.23919/DATE.2018.8342080},
ISSN={},
month={March},}Downloads
Physical_Synthesis_DATE_2018 [PDF]
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