Publications

• 2020

• 4. Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits" , In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi] [Bibtex & Downloads]

  Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits

  Reference

  Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar, "Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits" , In IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2020. [doi]

  Bibtex

  @article{9264740,
  doi = {10.1109/tetc.2020.3039375},
  url = {https://doi.org/10.1109%2Ftetc.2020.3039375},
  year = 2020,
  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
  pages = {1--1},
  author = {Shubham Rai and Satwik Patnaik and Ansh Rupani and Johann Knechtel and Ozgur Sinanoglu and Akash Kumar},
  title = {Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits},
  journal = {{IEEE} Transactions on Emerging Topics in Computing}
  }

  Downloads

  TETC_Security_author-copy [PDF]

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=2929

  ×

• 2019

• 3. A. Rupani, S. Rai, A. Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices" , In Proceeding: Euromicro DSD, August 2019. [Bibtex & Downloads]

  Exploiting Emerging Reconfigurable Technologies for Secure Devices

  Reference

  A. Rupani, S. Rai, A. Kumar, "Exploiting Emerging Reconfigurable Technologies for Secure Devices" , In Proceeding: Euromicro DSD, August 2019.

  Bibtex

  @InProceedings{Rai2019a,
  author = {A. Rupani and S. Rai and A. Kumar},
  title = {Exploiting Emerging Reconfigurable Technologies for Secure Devices},
  booktitle = {Euromicro DSD},
  year = {2019},
  month = {August},
  owner = {shubham},
  timestamp = {2018.04.26},
  }

  Downloads

  DSD_final [PDF]

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=2485

  ×
• 2. S. Rai, A. Rupani, P. Nath, A. Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies" , In Proceeding: ISVLSI, July 2019. [Bibtex & Downloads]

  Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies

  Reference

  S. Rai, A. Rupani, P. Nath, A. Kumar, "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies" , In Proceeding: ISVLSI, July 2019.

  Bibtex

  @InProceedings{Rai2019,
  Title = {Hardware Watermarking Using Polymorphic Inverter
  Designs Based On Reconfigurable Nanotechnologies},
  Author = {S. Rai and A. Rupani and P. Nath and A. Kumar},
  Booktitle = {ISVLSI},
  Year = {2019},
  Month = {July},
  Owner = {shubham},
  Timestamp = {2018.04.26}
  }

  Downloads

  ISVLSI [PDF]

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=2484

  ×

• 2018

• 1. S. Rai, A. Rupani, D. Walter, M. Raitza, A. Heinzig, T. Baldauf, J. Trommer, C. Mayr, W. M. Weber, A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 605-608, March 2018. [doi] [Bibtex & Downloads]

  A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

  Reference

  S. Rai, A. Rupani, D. Walter, M. Raitza, A. Heinzig, T. Baldauf, J. Trommer, C. Mayr, W. M. Weber, A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 605-608, March 2018. [doi]

  Bibtex

  @INPROCEEDINGS{8342080,
  author={S. Rai and A. Rupani and D. Walter and M. Raitza and A. Heinzig and T. Baldauf and J. Trommer and C. Mayr and W. M. Weber and A. Kumar},
  booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs},
  year={2018},
  volume={},
  number={},
  pages={605-608},
  keywords={field effect transistors;lithography;logic design;logic gates;nanowires;Library Exchange Format;SiNW based RFETs;SiNW based circuits;circuit designers;complete design flow;computational unit;early technology evaluation;fully symmetrical reconfigurable transistors;functionally enhanced transistors;gate terminal;independent gates;lithography steps;logic gates;logic synthesis;n-type functionality;p-type functionality;physical synthesis flow;program gate;silicon nanowire based reconfigurable FETs;silicon nanowire based reconfigurable field-effect transistors;Layout;Logic gates;Mathematical model;Nanoscale devices;Silicon;Tools;Transistors},
  doi={10.23919/DATE.2018.8342080},
  ISSN={},
  month={March},}

  Downloads

  Physical_Synthesis_DATE_2018 [PDF]

  Related Paths

  Silicon Nanowire Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=1658

  ×