Publications

• 2022

• 14. Michael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar, "Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2022. [Bibtex & Downloads]

  Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach

  Reference

  Michael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar, "Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach", In Proceeding: 2022 Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2022.

  Bibtex

  @INPROCEEDINGS{9474132,
  author={Raitza, Michael and M{\"a}rcker, Steffen and Rai, Shubham and Kumar, Akash},
  booktitle={2022 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={Exploring Standard-Cell Designs for Reconfigurable
  Nanotechnologies: A Formal Approach},
  year={2022},
  month = mar,
  volume={},
  number={}
  }

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  DATE_SS_2022 [PDF]

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• 13. Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi] [Bibtex & Downloads]

  END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator

  Reference

  Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar, "END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator" (to appear), Chapter in VLSI-SoC: Technology Advancement on SoC Design, Springer Nature Switzerland, pp. 175–203, 2022. [doi]

  Bibtex

  @incollection{Rai_2022,
  doi = {10.1007/978-3-031-16818-5_9},
  url = {https://doi.org/10.1007%2F978-3-031-16818-5_9},
  year = 2022,
  publisher = {Springer Nature Switzerland},
  pages = {175--203},
  author = {Shubham Rai and Nishant Gupta and Abhiroop Bhattacharjee and Ansh Rupani and Michael Raitza and Jens Trommer and Thomas Mikolajick and Akash Kumar},
  title = {{END}-{TRUE}: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator},
  booktitle = {{VLSI}-{SoC}: Technology Advancement on {SoC} Design}
  }

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• 2021

• 12. Najdet Charaf, Christoph Tietz, Michael Raitza, Akash Kumar, Diana Gohringer, "AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs", In Proceeding: 2021 International Conference on Field-Programmable Technology (ICFPT), IEEE, Dec 2021. [doi] [Bibtex & Downloads]

  AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs

  Reference

  Najdet Charaf, Christoph Tietz, Michael Raitza, Akash Kumar, Diana Gohringer, "AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs", In Proceeding: 2021 International Conference on Field-Programmable Technology (ICFPT), IEEE, Dec 2021. [doi]

  Bibtex

  @inproceedings{Charaf_2021,
  doi = {10.1109/icfpt52863.2021.9609948},
  url = {https://doi.org/10.1109%2Ficfpt52863.2021.9609948},
  year = 2021,
  month = {dec},
  publisher = ,
  author = {Najdet Charaf and Christoph Tietz and Michael Raitza and Akash Kumar and Diana Gohringer},
  title = {{AMAH}-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on {FPGAs}},
  booktitle = {2021 International Conference on Field-Programmable Technology ({ICFPT})}
  }

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  FPT-2021-AMAH-Flex_A_Modular_and_Highly_Flexible_Tool_for_Generating_Relocatable_Systems_on_FPGAs [PDF]

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• 11. Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi] [Bibtex & Downloads]

  Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput

  Reference

  Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar, "Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), IEEE, Oct 2021. [doi]

  Bibtex

  @inproceedings{Bhattacharjee_2021,
  doi = {10.1109/vlsi-soc53125.2021.9607015},
  url = {https://doi.org/10.1109%2Fvlsi-soc53125.2021.9607015},
  year = 2021,
  month = {oct},
  publisher = ,
  author = {Abhiroop Bhattacharjee and Shubham Rai and Ansh Rupani and Michael Raitza and Akash Kumar},
  title = {Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput},
  booktitle = {2021 {IFIP}/{IEEE} 29th International Conference on Very Large Scale Integration ({VLSI}-{SoC})}
  }

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  VLSI-SOC_2021 [PDF]

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• 2020

• 10. M. Raitza, S. Märcker, J. Trommer, A. Heinzig, S. Klüppelholz, C. Baier, A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates", In IEEE Access, pp. 1-1, June 2020. [Bibtex & Downloads]

  Quantitative Characterization of Reconfigurable Transistor Logic Gates

  Reference

  M. Raitza, S. Märcker, J. Trommer, A. Heinzig, S. Klüppelholz, C. Baier, A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates", In IEEE Access, pp. 1-1, June 2020.

  Bibtex

  @ARTICLE{9113477,
  author={M. {Raitza} and S. {Märcker} and J. {Trommer} and A. {Heinzig} and S. {Klüppelholz} and C. {Baier} and A. {Kumar}},
  journal={IEEE Access},
  title={Quantitative Characterization of Reconfigurable Transistor Logic Gates},
  year={2020},
  month={June},
  volume={},
  number={},
  pages={1-1},}

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  09113477 [PDF]

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• 9. Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi] [Bibtex & Downloads]

  DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies

  Reference

  Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi]

  Bibtex

  @inproceedings{Rai_2020,
  doi = {10.23919/date48585.2020.9116216},
  url = {https://doi.org/10.23919%2Fdate48585.2020.9116216},
  year = 2020,
  month = {mar},
  publisher = ,
  author = {Shubham Rai and Michael Raitza and Siva Satyendra Sahoo and Akash Kumar},
  title = {{DiSCERN}: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies},
  booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
  }

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• 2019

• 8. Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 27, no. 3, pp. 560–572, Mar 2019. [doi] [Bibtex & Downloads]

  Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

  Reference

  Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors", In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 27, no. 3, pp. 560–572, Mar 2019. [doi]

  Bibtex

  @article{Rai_2019,
  doi = {10.1109/tvlsi.2018.2884646},
  url = {https://doi.org/10.1109%2Ftvlsi.2018.2884646},
  year = 2019,
  month = {mar},
  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
  volume = {27},
  number = {3},
  pages = {560--572},
  author = {Shubham Rai and Jens Trommer and Michael Raitza and Thomas Mikolajick and Walter M. Weber and Akash Kumar},
  title = {Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors},
  journal = {{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}
  }

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  08580544 [PDF]

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• 2018

• 7. Jeronimo Castrillon, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems", In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi] [Bibtex & Downloads]

  A Hardware/Software Stack for Heterogeneous Systems

  Reference

  Jeronimo Castrillon, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems", In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi]

  Abstract

  Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.

  Bibtex

  @Article{castrillon_tmscs17,
  author = {Jeronimo Castrillon and Matthias Lieber and Sascha Kl{\"u}ppelholz and Marcus V{\"o}lp and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fr{\"o}hlich and Andr\'{e}s Goens and Sebastian Haas and Dirk Habich and Hermann H{\"a}rtig and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Akash Kumar and Wolfgang Lehner and Linda Leuschner and Siqi Ling and Steffen M{\"a}rcker and Christian Menard and Johannes Mey and Wolfgang Nagel and Benedikt N{\"o}then and Rafael Pe{\~n}aloza and Michael Raitza and J{\"o}rg Stiller and Annett Ungeth{\"u}m and Axel Voigt and Sascha Wunderlich},
  title = {A Hardware/Software Stack for Heterogeneous Systems},
  journal = {IEEE Transactions on Multi-Scale Computing Systems},
  year = {2018},
  month = jul,
  volume={4},
  number={3},
  pages={243-259},
  abstract = {Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.},
  doi = {10.1109/TMSCS.2017.2771750},
  issn = {2332-7766},
  url = {http://ieeexplore.ieee.org/document/8103042/}
  }

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  1711_Castrillon_TMSCS [PDF]

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• 6. Shubham Rai, Michael Raitza, Akash Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] [Bibtex & Downloads]

  Technology mapping flow for emerging reconfigurable silicon nanowire transistors

  Reference

  Shubham Rai, Michael Raitza, Akash Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]

  Bibtex

  @inproceedings{Rai_2018,
  doi = {10.23919/date.2018.8342110},
  url = {https://doi.org/10.23919%2Fdate.2018.8342110},
  year = 2018,
  month = {mar},
  publisher = ,
  author = {Shubham Rai and Michael Raitza and Akash Kumar},
  title = {Technology mapping flow for emerging reconfigurable silicon nanowire transistors},
  booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
  }

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  Technology_Mapping_DATE_2018 [PDF]

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• 5. Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi] [Bibtex & Downloads]

  A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

  Reference

  Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs", In Proceeding: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2018. [doi]

  Bibtex

  @inproceedings{Rai_2018,
  doi = {10.23919/date.2018.8342080},
  url = {https://doi.org/10.23919%2Fdate.2018.8342080},
  year = 2018,
  month = {mar},
  publisher = ,
  author = {Shubham Rai and Ansh Rupani and Dennis Walter and Michael Raitza and Andre Heinzig and Tim Baldauf and Jens Trommer and Christian Mayr and Walter M. Weber and Akash Kumar},
  title = {A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable {FETs}},
  booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
  }

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  Physical_Synthesis_DATE_2018 [PDF]

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• 2017

• 4. Michael Raitza, Jens Trommer, Akash Kumar, Marcus Völp, Dennis Walter, Walter Weber, Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. [Bibtex & Downloads]

  Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits

  Reference

  Michael Raitza, Jens Trommer, Akash Kumar, Marcus Völp, Dennis Walter, Walter Weber, Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits", Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.

  Bibtex

  @InProceedings{raitza2017date,
  author = {Michael Raitza and Jens Trommer and Akash Kumar and Marcus Völp and Dennis Walter and Walter Weber and Thomas Mikolajick},
  title = {Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits},
  booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
  year = {2017},
  month = {March},
  organization = {IEEE}
  }

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  date-2017-michael [PDF]

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• 2016

• 3. Marcus Völp, Sascha Klüppelholz, Jeronimo Castrillon, Hermann Härtig, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andres Goens, Sebastian Haas, Dirk Habich, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Wolfgang Lehner, Linda Leuschner, Matthias Lieber, Siqi Ling, Steffen Märcker, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, "The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware", Proceedings of the 1st International Workshop on Post-Moore's Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Salt Lake City, USA, Nov 2016. [Bibtex & Downloads]

  The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware

  Reference

  Marcus Völp, Sascha Klüppelholz, Jeronimo Castrillon, Hermann Härtig, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andres Goens, Sebastian Haas, Dirk Habich, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Wolfgang Lehner, Linda Leuschner, Matthias Lieber, Siqi Ling, Steffen Märcker, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, "The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware", Proceedings of the 1st International Workshop on Post-Moore's Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Salt Lake City, USA, Nov 2016.

  Abstract

  Future systems based on post-CMOS technologies,
  will be wildly heterogeneous, with properties largely unknown today.,
  This paper presents our design of a new hardware/software stack to address the,
  challenge of preparing software development for such systems.,
  It combines well-understood technologies from different areas, e.g., network-on-chips,
  capability operating systems, flexible programming models and model checking.,
  We describe our approach and provide details on key technologies.

  Bibtex

  @InProceedings{voelp16_pmes,
  author = {Marcus V{\"o}lp and Sascha Kl{\"u}ppelholz and Jeronimo Castrillon and Hermann H{\"a}rtig and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fr{\"o}hlich and Andres Goens and Sebastian Haas and Dirk Habich and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Wolfgang Lehner and Linda Leuschner and Matthias Lieber and Siqi Ling and Steffen M{\"a}rcker and Johannes Mey and Wolfgang Nagel and Benedikt N{\"o}then and Rafael Pe{\~n}aloza and Michael Raitza and J{\"o}rg Stiller and Annett Ungeth{\"u}m and Axel Voigt},
  title = {The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware},
  booktitle = {Proceedings of the 1st International Workshop on Post-Moore's Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16)},
  year = {2016},
  address = {Salt Lake City, USA},
  month = nov,
  url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/1611_Voelp_PMES.pdf},
  abstract = {Future systems based on post-CMOS technologies,
  will be wildly heterogeneous, with properties largely unknown today.,
  This paper presents our design of a new hardware/software stack to address the,
  challenge of preparing software development for such systems.,
  It combines well-understood technologies from different areas, e.g., network-on-chips,
  capability operating systems, flexible programming models and model checking.,
  We describe our approach and provide details on key technologies.},
  }

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• 2. Jens Trommer, Tim Baldauf, Thomas Mikolajick, Walter M Weber, Michael Raitza, others, "Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits", In Proceeding: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 169–174, 2016. [Bibtex & Downloads]

  Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits

  Reference

  Jens Trommer, Tim Baldauf, Thomas Mikolajick, Walter M Weber, Michael Raitza, others, "Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits", In Proceeding: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 169–174, 2016.

  Bibtex

  @inproceedings{trommer2016reconfigurable,
  title={Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits},
  author={Trommer, Jens and Baldauf, Tim and Mikolajick, Thomas and Weber, Walter M and Raitza, Michael and others},
  booktitle={2016 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
  pages={169--174},
  year={2016},
  organization={IEEE}
  }

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• 2015

• 1. Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck, "RAW 2014: Random Number Generators on FPGAs", In ACM Trans. Reconfigurable Technol. Syst., ACM, vol. 9, no. 2, pp. 15:1–15:21, New York, NY, USA, Dec 2015. [doi] [Bibtex & Downloads]

  RAW 2014: Random Number Generators on FPGAs

  Reference

  Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck, "RAW 2014: Random Number Generators on FPGAs", In ACM Trans. Reconfigurable Technol. Syst., ACM, vol. 9, no. 2, pp. 15:1–15:21, New York, NY, USA, Dec 2015. [doi]

  Bibtex

  @article{Raitza:2015:RRN:2854101.2807699,
  author={Raitza, Michael and Vogt, Markus and Hochberger, Christian and Pionteck, Thilo},
  title={RAW 2014: Random Number Generators on FPGAs},
  journal={ACM Trans. Reconfigurable Technol. Syst.},
  issue_date={January 2016},
  volume={9},
  number={2},
  month=dec,
  year={2015},
  issn={1936-7406},
  pages={15:1--15:21},
  articleno={15},
  numpages={21},
  url={http://doi.acm.org/10.1145/2807699},
  doi={10.1145/2807699},
  acmid={2807699},
  publisher={ACM},
  address={New York, NY, USA},
  keywords={Entropy source, FPGA, X-radiation, active attack on random number generator, cryptography, magnetic field, power supply, technology invariance, temperature, true random number generator},
  }

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