Publications

• 2020

• 10. M. Raitza and S. Märcker and J. Trommer and A. Heinzig and S. Klüppelholz and C. Baier and A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates" , In IEEE Access, pp. 1-1, June 2020. [Bibtex & Downloads]

  Quantitative Characterization of Reconfigurable Transistor Logic Gates

  Reference

  M. Raitza and S. Märcker and J. Trommer and A. Heinzig and S. Klüppelholz and C. Baier and A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates" , In IEEE Access, pp. 1-1, June 2020.

  Bibtex

  @ARTICLE{9113477,
  author={M. {Raitza} and S. {Märcker} and J. {Trommer} and A. {Heinzig} and S. {Klüppelholz} and C. {Baier} and A. {Kumar}},
  journal={IEEE Access},
  title={Quantitative Characterization of Reconfigurable Transistor Logic Gates},
  year={2020},
  month={June},
  volume={},
  number={},
  pages={1-1},}

  Downloads

  09113477 [PDF]

  Related Paths

  Silicon Nanowire Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=2815

  ×
• 9. S. Rai and M. Raitza and S. S. Sahoo and A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]

  DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES

  Reference

  S. Rai and M. Raitza and S. S. Sahoo and A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020.

  Bibtex

  @INPROCEEDINGS{date_Shubham,
  author={S. Rai and M. Raitza and S. S. Sahoo and A. Kumar},
  booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES},
  year={2020},
  month={March},}

  Downloads

  DiSCERN_DATE_2020 [PDF]

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=2593

  ×

• 2019

• 8. S. Rai and J. Trommer and M. Raitza and T. Mikolajick and W. M. Weber and A. Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors" , In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 560-572, March 2019. [doi] [Bibtex & Downloads]

  Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

  Reference

  S. Rai and J. Trommer and M. Raitza and T. Mikolajick and W. M. Weber and A. Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors" , In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 560-572, March 2019. [doi]

  Bibtex

  @ARTICLE{8580544,
  author={S. {Rai} and J. {Trommer} and M. {Raitza} and T. {Mikolajick} and W. M. {Weber} and A. {Kumar}},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  title={Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors},
  year={2019},
  volume={27},
  number={3},
  pages={560-572},
  keywords={elemental semiconductors;field effect transistor circuits;logic circuits;logic design;logic gates;nanoelectronics;nanowires;germanium nanowire-based reconfigurable field-effect transistors;silicon nanowire-based reconfigurable field-effect transistors;power metric;arithmetic logic unit-based design;silicon nanowire reconfigurable FETs;CMOS reference design;normalized circuit delay;reconfigurable multifunctional circuit;efficient circuit designs;reconfigurable nanowire technology;functionally enhanced logic gates;exemplary designs;suboptimal designs;contemporary CMOS circuit designs;computational unit;multiple functionalities;reconfigurable nanotechnologies;runtime-reconfigurable field-effect transistors;Logic gates;Circuit synthesis;Silicon;CMOS technology;Delays;Field effect transistors;Functionally enhanced logic gates;multi-independent gate reconfigurable field-effect transistor (MIGRFET);RFET;reconfigurable transistor;silicon nanowire (SiNW) transistor;three-independent gate field-effect transistor (TIGFET)},
  doi={10.1109/TVLSI.2018.2884646},
  ISSN={1063-8210},
  month={March},}

  Downloads

  08580544 [PDF]

  Related Paths

  Silicon Nanowire Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=2247

  ×

• 2018

• 7. Jeronimo Castrillon and Matthias Lieber and Sascha Klüppelholz and Marcus Völp and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fröhlich and Andrés Goens and Sebastian Haas and Dirk Habich and Hermann Härtig and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Akash Kumar and Wolfgang Lehner and Linda Leuschner and Siqi Ling and Steffen Märcker and Christian Menard and Johannes Mey and Wolfgang Nagel and Benedikt Nöthen and Rafael Peñaloza and Michael Raitza and Jörg Stiller and Annett Ungethüm and Axel Voigt and Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems" , In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi] [Bibtex & Downloads]

  A Hardware/Software Stack for Heterogeneous Systems

  Reference

  Jeronimo Castrillon and Matthias Lieber and Sascha Klüppelholz and Marcus Völp and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fröhlich and Andrés Goens and Sebastian Haas and Dirk Habich and Hermann Härtig and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Akash Kumar and Wolfgang Lehner and Linda Leuschner and Siqi Ling and Steffen Märcker and Christian Menard and Johannes Mey and Wolfgang Nagel and Benedikt Nöthen and Rafael Peñaloza and Michael Raitza and Jörg Stiller and Annett Ungethüm and Axel Voigt and Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems" , In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi]

  Abstract

  Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.

  Bibtex

  @Article{castrillon_tmscs17,
  author = {Jeronimo Castrillon and Matthias Lieber and Sascha Kl{\"u}ppelholz and Marcus V{\"o}lp and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fr{\"o}hlich and Andr\'{e}s Goens and Sebastian Haas and Dirk Habich and Hermann H{\"a}rtig and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Akash Kumar and Wolfgang Lehner and Linda Leuschner and Siqi Ling and Steffen M{\"a}rcker and Christian Menard and Johannes Mey and Wolfgang Nagel and Benedikt N{\"o}then and Rafael Pe{\~n}aloza and Michael Raitza and J{\"o}rg Stiller and Annett Ungeth{\"u}m and Axel Voigt and Sascha Wunderlich},
  title = {A Hardware/Software Stack for Heterogeneous Systems},
  journal = {IEEE Transactions on Multi-Scale Computing Systems},
  year = {2018},
  month = jul,
  volume={4},
  number={3},
  pages={243-259},
  abstract = {Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This paper discusses a programming stack for heterogeneous systems that combines and adapts well-understood principles from different areas, including capability-based operating systems, adaptive application runtimes, dataflow programming models, and model checking. We argue why we think that these principles built into the stack and the interfaces among the layers will also be applicable to future systems that integrate heterogeneous technologies. The programming stack is evaluated on a tiled heterogeneous multicore.},
  doi = {10.1109/TMSCS.2017.2771750},
  issn = {2332-7766},
  url = {http://ieeexplore.ieee.org/document/8103042/}
  }

  Downloads

  1711_Castrillon_TMSCS [PDF]

  Related Paths

  Orchestration Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=1597

  ×
• 6. S. Rai and M. Raitza and A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 767-772, March 2018. [doi] [Bibtex & Downloads]

  Technology mapping flow for emerging reconfigurable silicon nanowire transistors

  Reference

  S. Rai and M. Raitza and A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 767-772, March 2018. [doi]

  Bibtex

  @INPROCEEDINGS{8342110,
  author={S. Rai and M. Raitza and A. Kumar},
  booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={Technology mapping flow for emerging reconfigurable silicon nanowire transistors},
  year={2018},
  volume={},
  number={},
  pages={767-772},
  keywords={CMOS logic circuits;elemental semiconductors;logic design;logic gates;nanoelectronics;nanowires;reconfigurable architectures;silicon;transistor circuits;CMOS based mapping;CMOS flow;HOF;Si;SiNW based genlib;SiNW based logic design;SiNW based logic gates;SiNW transistors;XOR logic family;ambipolar transistors;area-optimized technology mapping;conventional circuit design-flow;efficient circuit designs;electrical properties;extended functionality;functional flexibility;higher order functions;modified ABC tool;open source license;reconfigurable silicon nanowire transistors;single logical output;static layout;technology mapping flow;CMOS technology;Logic circuits;Logic gates;Optimization;Silicon;Tools;Transistors},
  doi={10.23919/DATE.2018.8342110},
  ISSN={},
  month={March},}

  Downloads

  Technology_Mapping_DATE_2018 [PDF]

  Related Paths

  Silicon Nanowire Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=1657

  ×
• 5. S. Rai and A. Rupani and D. Walter and M. Raitza and A. Heinzig and T. Baldauf and J. Trommer and C. Mayr and W. M. Weber and A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 605-608, March 2018. [doi] [Bibtex & Downloads]

  A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

  Reference

  S. Rai and A. Rupani and D. Walter and M. Raitza and A. Heinzig and T. Baldauf and J. Trommer and C. Mayr and W. M. Weber and A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 605-608, March 2018. [doi]

  Bibtex

  @INPROCEEDINGS{8342080,
  author={S. Rai and A. Rupani and D. Walter and M. Raitza and A. Heinzig and T. Baldauf and J. Trommer and C. Mayr and W. M. Weber and A. Kumar},
  booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs},
  year={2018},
  volume={},
  number={},
  pages={605-608},
  keywords={field effect transistors;lithography;logic design;logic gates;nanowires;Library Exchange Format;SiNW based RFETs;SiNW based circuits;circuit designers;complete design flow;computational unit;early technology evaluation;fully symmetrical reconfigurable transistors;functionally enhanced transistors;gate terminal;independent gates;lithography steps;logic gates;logic synthesis;n-type functionality;p-type functionality;physical synthesis flow;program gate;silicon nanowire based reconfigurable FETs;silicon nanowire based reconfigurable field-effect transistors;Layout;Logic gates;Mathematical model;Nanoscale devices;Silicon;Tools;Transistors},
  doi={10.23919/DATE.2018.8342080},
  ISSN={},
  month={March},}

  Downloads

  Physical_Synthesis_DATE_2018 [PDF]

  Related Paths

  Silicon Nanowire Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=1658

  ×

• 2017

• 4. Michael Raitza and Jens Trommer and Akash Kumar and Marcus Völp and Dennis Walter and Walter Weber and Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits" , Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. [Bibtex & Downloads]

  Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits

  Reference

  Michael Raitza and Jens Trommer and Akash Kumar and Marcus Völp and Dennis Walter and Walter Weber and Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits" , Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017.

  Bibtex

  @InProceedings{raitza2017date,
  author = {Michael Raitza and Jens Trommer and Akash Kumar and Marcus Völp and Dennis Walter and Walter Weber and Thomas Mikolajick},
  title = {Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits},
  booktitle = {Proceedings of the 2017 Design, Automation \& Test in Europe Conference \& Exhibition},
  year = {2017},
  month = {March},
  organization = {IEEE}
  }

  Downloads

  date-2017-michael [PDF]

  Related Paths

  Orchestration Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=1252

  ×

• 2016

• 3. Marcus Völp, Sascha Klüppelholz, Jeronimo Castrillon, Hermann Härtig, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andres Goens, Sebastian Haas, Dirk Habich, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Wolfgang Lehner, Linda Leuschner, Matthias Lieber, Siqi Ling, Steffen Märcker, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, "The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware" , Proceedings of the 1st International Workshop on Post-Moore s Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Salt Lake City, USA, Nov 2016. [Bibtex & Downloads]

  The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware

  Reference

  Marcus Völp, Sascha Klüppelholz, Jeronimo Castrillon, Hermann Härtig, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andres Goens, Sebastian Haas, Dirk Habich, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Wolfgang Lehner, Linda Leuschner, Matthias Lieber, Siqi Ling, Steffen Märcker, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, "The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware" , Proceedings of the 1st International Workshop on Post-Moore s Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Salt Lake City, USA, Nov 2016.

  Abstract

  Future systems based on post-CMOS technologies will be wildly heterogeneous, with properties largely unknown today. This paper presents our design of a new hardware/software stack to address the challenge of preparing software development for such systems. It combines well-understood technologies from different areas, e.g., network-on-chips, capability operating systems, flexible programming models and model checking. We describe our approach and provide details on key technologies.

  Bibtex

  @InProceedings{voelp16_pmes,
  author = {Marcus V{\"o}lp and Sascha Kl{\"u}ppelholz and Jeronimo Castrillon and Hermann H{\"a}rtig and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fr{\"o}hlich and Andres Goens and Sebastian Haas and Dirk Habich and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Wolfgang Lehner and Linda Leuschner and Matthias Lieber and Siqi Ling and Steffen M{\"a}rcker and Johannes Mey and Wolfgang Nagel and Benedikt N{\"o}then and Rafael Pe{\~n}aloza and Michael Raitza and J{\"o}rg Stiller and Annett Ungeth{\"u}m and Axel Voigt},
  title = {The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware},
  booktitle = {Proceedings of the 1st International Workshop on Post-Moore's Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16)},
  year = {2016},
  address = {Salt Lake City, USA},
  month = nov,
  url = {https://cfaed.tu-dresden.de/files/user/jcastrillon/publications/1611_Voelp_PMES.pdf}
  abstract = {Future systems based on post-CMOS technologies
  will be wildly heterogeneous, with properties largely unknown today.
  This paper presents our design of a new hardware/software stack to address the
  challenge of preparing software development for such systems.
  It combines well-understood technologies from different areas, e.g., network-on-chips,
  capability operating systems, flexible programming models and model checking.
  We describe our approach and provide details on key technologies.},
  }
  

  Downloads

  1611_Voelp_PMES [PDF]

  Related Paths

  Orchestration Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=923

  ×
• 2. Trommer, Jens and Baldauf, Tim and Mikolajick, Thomas and Weber, Walter M and Raitza, Michael and others, "Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits" , In Proceeding: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 169–174, 2016. [Bibtex & Downloads]

  Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits

  Reference

  Trommer, Jens and Baldauf, Tim and Mikolajick, Thomas and Weber, Walter M and Raitza, Michael and others, "Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits" , In Proceeding: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 169–174, 2016.

  Bibtex

  @inproceedings{trommer2016reconfigurable,
  title={Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits},
  author={Trommer, Jens and Baldauf, Tim and Mikolajick, Thomas and Weber, Walter M and Raitza, Michael and others},
  booktitle={2016 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
  pages={169--174},
  year={2016},
  organization={IEEE}
  }

  Downloads

  No Downloads available for this publication

  Related Paths

  Silicon Nanowire Path, Silicon Nanowire Path, Silicon Nanowire Path, Silicon Nanowire Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=830

  ×

• 2015

• 1. Raitza, Michael and Vogt, Markus and Hochberger, Christian and Pionteck, Thilo, "RAW 2014: Random Number Generators on FPGAs" , In ACM Trans. Reconfigurable Technol. Syst., ACM, vol. 9, no. 2, pp. 15:1–15:21, New York, NY, USA, Dec 2015. [doi] [Bibtex & Downloads]

  RAW 2014: Random Number Generators on FPGAs

  Reference

  Raitza, Michael and Vogt, Markus and Hochberger, Christian and Pionteck, Thilo, "RAW 2014: Random Number Generators on FPGAs" , In ACM Trans. Reconfigurable Technol. Syst., ACM, vol. 9, no. 2, pp. 15:1–15:21, New York, NY, USA, Dec 2015. [doi]

  Bibtex

  @article{Raitza:2015:RRN:2854101.2807699,
  author={Raitza, Michael and Vogt, Markus and Hochberger, Christian and Pionteck, Thilo},
  title={RAW 2014: Random Number Generators on FPGAs},
  journal={ACM Trans. Reconfigurable Technol. Syst.},
  issue_date={January 2016},
  volume={9},
  number={2},
  month=dec,
  year={2015},
  issn={1936-7406},
  pages={15:1--15:21},
  articleno={15},
  numpages={21},
  url={http://doi.acm.org/10.1145/2807699},
  doi={10.1145/2807699},
  acmid={2807699},
  publisher={ACM},
  address={New York, NY, USA},
  keywords={Entropy source, FPGA, X-radiation, active attack on random number generator, cryptography, magnetic field, power supply, technology invariance, temperature, true random number generator},
  }

  Downloads

  No Downloads available for this publication

  Related Paths

  Orchestration Path

  Permalink

  https://cfaed.tu-dresden.de/publications?pubId=681

  ×