Michael Raitza

E-mail

Phone

Fax

Visitor's Address

michael.raitza (-) tu-dresden.de

+49 (351) 463-43527

+49 (0)351 463-39995

Helmholtzstrasse 18, BAR-III75

Publications

  • 2020

  • 10. M. Raitza and S. Märcker and J. Trommer and A. Heinzig and S. Klüppelholz and C. Baier and A. Kumar, "Quantitative Characterization of Reconfigurable Transistor Logic Gates" , In IEEE Access, pp. 1-1, June 2020. [Bibtex & Downloads]
  • 9. S. Rai and M. Raitza and S. S. Sahoo and A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]
  • 2019

  • 8. S. Rai and J. Trommer and M. Raitza and T. Mikolajick and W. M. Weber and A. Kumar, "Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors" , In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 560-572, March 2019. [doi] [Bibtex & Downloads]
  • 2018

  • 7. Jeronimo Castrillon and Matthias Lieber and Sascha Klüppelholz and Marcus Völp and Nils Asmussen and Uwe Assmann and Franz Baader and Christel Baier and Gerhard Fettweis and Jochen Fröhlich and Andrés Goens and Sebastian Haas and Dirk Habich and Hermann Härtig and Mattis Hasler and Immo Huismann and Tomas Karnagel and Sven Karol and Akash Kumar and Wolfgang Lehner and Linda Leuschner and Siqi Ling and Steffen Märcker and Christian Menard and Johannes Mey and Wolfgang Nagel and Benedikt Nöthen and Rafael Peñaloza and Michael Raitza and Jörg Stiller and Annett Ungethüm and Axel Voigt and Sascha Wunderlich, "A Hardware/Software Stack for Heterogeneous Systems" , In IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 3, pp. 243-259, Jul 2018. [doi] [Bibtex & Downloads]
  • 6. S. Rai and M. Raitza and A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 767-772, March 2018. [doi] [Bibtex & Downloads]
  • 5. S. Rai and A. Rupani and D. Walter and M. Raitza and A. Heinzig and T. Baldauf and J. Trommer and C. Mayr and W. M. Weber and A. Kumar, "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 605-608, March 2018. [doi] [Bibtex & Downloads]
  • 2017

  • 4. Michael Raitza and Jens Trommer and Akash Kumar and Marcus Völp and Dennis Walter and Walter Weber and Thomas Mikolajick, "Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits" , Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition, March 2017. [Bibtex & Downloads]
  • 2016

  • 3. Marcus Völp, Sascha Klüppelholz, Jeronimo Castrillon, Hermann Härtig, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andres Goens, Sebastian Haas, Dirk Habich, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Wolfgang Lehner, Linda Leuschner, Matthias Lieber, Siqi Ling, Steffen Märcker, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, "The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware" , Proceedings of the 1st International Workshop on Post-Moore s Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Salt Lake City, USA, Nov 2016. [Bibtex & Downloads]
  • 2. Trommer, Jens and Baldauf, Tim and Mikolajick, Thomas and Weber, Walter M and Raitza, Michael and others, "Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits" , In Proceeding: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 169–174, 2016. [Bibtex & Downloads]
  • 2015

  • 1. Raitza, Michael and Vogt, Markus and Hochberger, Christian and Pionteck, Thilo, "RAW 2014: Random Number Generators on FPGAs" , In ACM Trans. Reconfigurable Technol. Syst., ACM, vol. 9, no. 2, pp. 15:1–15:21, New York, NY, USA, Dec 2015. [doi] [Bibtex & Downloads]