Yuhao Liu

E-mail

Phone

Fax

Visitor's Address

yuhao.liu1@tu-dresden.de

+49 (0)351 463-43731

+49 (0)351 463-39995

Helmholtzstrasse 18, BAR-III78

Yuhao Liu is a research assistant. He obtained his B.Sc. degree in Electronic and Information Engineering from Zhengzhou University in China and his M.Sc. degree in Embedded System Engineering from the University of Duisburg-Essen in Germany. His current research interest is the implementation of FPGA-based Neural Network Accelerators.

LinkedIn: http://www.linkedin.com/in/yuhao-liu-horizon776

 

Publications

  • 2024

  • 5. Yuhao Liu, Salim Ullah, Akash Kumar, "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators", In Proceeding: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp. 220–220, May 2024. [doi] [Bibtex & Downloads]
  • 4. Maryam Eslami, Yuhao Liu, Salim Ullah, Mostafa Ersali Salehi Nasab, Reshad Hosseini, Seyed Ahmad Mirsalari, Akash Kumar, "MONO: Enhancing Bit-Flip Resilience with Bit Homogeneity for Neural Networks" (to appear), In IEEE Embedded Systems Letters, pp. 1-1, 2024. [Bibtex & Downloads]