Run-time Reconfigurable Approximate Architecture

Project Abstract

Approximate Computing or Inexact Computing can be seen as one solution for building highly energy-efficient systems. With continuous technology scaling, roadblocks on reducing supply voltage, and escalating power density and thermal issues, traditional low power techniques like dynamic voltage and frequency scaling (DVFS) and power-gating no longer suffice to provide a significant reduction in total chip power consumption. With approximate computing, accuracy and precision bounds of computation can be relaxed, enabling significant improvements in the area, power, and performance (e.g. circuit delay) of on-chip systems while keeping output quality within an acceptable range.

The relevant ongoing works in the area of approximate computing (AC) consider both the hardware and software level. A major limitation of these works is that hardware-wise, only fine-grained elements, and only a few specific circuit techniques are considered, rather than complex embedded architectures. Furthermore, the existing techniques are restricted or at least best-suited to specific applications whose behavior is well understood statically. In more general contexts where the accuracy requirement can change dynamically, such static techniques need to be extended to dynamic methods. In this project, we intend to provide a systematic approach to support run-time accuracy reconfigurable designs in hardware. We intend to improve energy efficiency as much as possible where the runtime system  (RTS) will use the accuracy requirements of the application and reconfigure the architectural components with the desired level of inaccuracy. Our approach is orthogonal to any software optimizations. Even for optimized algorithms, we expect substantial savings by reconfiguring the hardware to the precisely needed accuracy.


Project title: Run-time Reconfigurable Approximate Architecture

Acronym: ReAp

Research Grant: Funded by Deutsche Forschungsgemeinschaft (DFG). Amount: 191,900 Euros

Project Duration:  February 2018 -- August 2020


Project Related Publications
  1. Prabakaran, Bharath Srinivas, Semeen Rehman, Muhammad Abdullah Hanif, Salim Ullah, Ghazal Mazaheri, Akash Kumar, and Muhammad Shafique. "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems." In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 917-920. IEEE, 2018. (PDF Download)
  2. Ullah, Salim, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, and Akash Kumar. "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators." In Proceedings of the 55th Annual Design Automation Conference, pp. 1-6. 2018. (PDF Download)
  3. Ullah, Salim, Sanjeev Sripadraj Murthy, and Akash Kumar. "SMApproxlib: library of FPGA-based approximate multipliers." In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2018. (PDF Download)
  4. Ebrahimi, Zahra, Salim Ullah, and Akash Kumar. "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy." In 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 605-610. IEEE, 2020. (PDF Download)
  5. Ullah, Salim, Hendrik Schmidl, Siva Satyendra Sahoo, Semeen Rehman, and Akash Kumar. "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures." IEEE Transactions on Computers (2020). (PDF Download)
  6. Ullah, Salim, Tuan Duy Anh Nguyen, and Akash Kumar. "Energy-Efficient Low-Latency Signed Multiplier for FPGA-based Hardware Accelerators." IEEE Embedded Systems Letters (2020). (PDF Download)
  7. Gupta, Siddharth, Salim Ullah, Kapil Ahuja, Aruna Tiwari, and Akash Kumar. "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks." IEEE Access 8 (2020): 118899-118911. (PDF Download)
  8. Ebrahimi, Zahra, Salim Ullah, and Akash Kumar. "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy." In Proceedings of the 2020 on Great Lakes Symposium on VLSI, pp. 151-156. 2020. (PDF Download)
  9. De la Parra, Cecilia, Andre Guntoro, and Akash Kumar. "ProxSim: GPU-based simulation framework for cross-layer approximate DNN optimization." In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1193-1198. IEEE, 2020. (PDF Download)
  10. Nguyen, Tuan DA, and Akash Kumar. "Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment." In The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 29-39. 2020. (PDF Download)
  11. Cecilia De la Parra, Andre Guntoro and Akash Kumar, "Improving approximate neural networks for perception tasks through specialized optimization," in Future Generation Computer Systems, 2020. (PDF Download)