Publications

• 2025

• 34. Yuhao Liu, Salim Ullah, Akash Kumar, "BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs" (to appear), In Proceeding: 2025 IEEE 33nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, May 2025. [Bibtex & Downloads]

  BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs

  Reference

  Yuhao Liu, Salim Ullah, Akash Kumar, "BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs" (to appear), In Proceeding: 2025 IEEE 33nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, May 2025.

  Bibtex

  @inproceedings{Liu_2024, title={BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs}, booktitle={2025 IEEE 33nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Liu, Yuhao and Ullah, Salim and Kumar, Akash}, year={2025}, month=may}

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• 33. Yuhao Liu, Salim Ullah, Akash Kumar, "Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators" (to appear), In Proceeding: 2025 26th International Symposium on Quality Electronic Design (ISQED), pp. 1-8, 2025. [Bibtex & Downloads]

  Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators

  Reference

  Yuhao Liu, Salim Ullah, Akash Kumar, "Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators" (to appear), In Proceeding: 2025 26th International Symposium on Quality Electronic Design (ISQED), pp. 1-8, 2025.

  Bibtex

  @INPROCEEDINGS{BitSys2,
  author={Liu, Yuhao and Ullah, Salim and Kumar, Akash},
  booktitle={2025 26th International Symposium on Quality Electronic Design (ISQED)},
  title={Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators},
  year={2025},
  volume={},
  number={},
  pages={1-8},
  keywords={Mixed-precision;Quantized Neural Network;Multiplier;Runtime-Reconfigurable;Accelerator;FPGA},
  doi={}}

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  BitSys_ISQED [PDF]

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• 2024

• 32. Maryam Eslami, Yuhao Liu, Salim Ullah, Mostafa E. Salehi, Reshad Hosseini, Seyed Ahmad Mirsalari, Akash Kumar, "MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 16, no. 4, pp. 333–336, Dec 2024. [doi] [Bibtex & Downloads]

  MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks

  Reference

  Maryam Eslami, Yuhao Liu, Salim Ullah, Mostafa E. Salehi, Reshad Hosseini, Seyed Ahmad Mirsalari, Akash Kumar, "MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 16, no. 4, pp. 333–336, Dec 2024. [doi]

  Bibtex

  @article{Eslami_2024, title={MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks}, volume={16}, ISSN={1943-0671}, url={http://dx.doi.org/10.1109/LES.2024.3444921}, DOI={10.1109/les.2024.3444921}, number={4}, journal={IEEE Embedded Systems Letters}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Eslami, Maryam and Liu, Yuhao and Ullah, Salim and Salehi, Mostafa E. and Hosseini, Reshad and Ahmad Mirsalari, Seyed and Kumar, Akash}, year={2024}, month=dec, pages={333–336} }

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• 31. Yuhao Liu, Salim Ullah, Akash Kumar, "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators", In Proceeding: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp. 220–220, May 2024. [doi] [Bibtex & Downloads]

  BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators

  Reference

  Yuhao Liu, Salim Ullah, Akash Kumar, "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators", In Proceeding: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp. 220–220, May 2024. [doi]

  Bibtex

  @inproceedings{Liu_2024, title={BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators}, url={http://dx.doi.org/10.1109/fccm60383.2024.00042}, DOI={10.1109/fccm60383.2024.00042}, booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Liu, Yuhao and Ullah, Salim and Kumar, Akash}, year={2024}, month=may, pages={220–220} }

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  FCCM_Poster_Final_3 [PDF]

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• 30. Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming", In ACM Transactions on Reconfigurable Technology and Systems (TRETS), pp. 1–28, April 2024. [Bibtex & Downloads]

  AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming

  Reference

  Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming", In ACM Transactions on Reconfigurable Technology and Systems (TRETS), pp. 1–28, April 2024.

  Bibtex

  @article{siva_trets_2024,
  title={AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming},
  author={Sahoo, Siva Satyendra and Ullah, Salim and Kumar, Akash},
  journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
  volume={},
  number={},
  pages={1--28},
  year={2024},
  month={April}
  }

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• 2023

• 29. Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations", Chapter in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer International Publishing, pp. 89–119, Oct 2023. [doi] [Bibtex & Downloads]

  Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations

  Reference

  Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations", Chapter in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer International Publishing, pp. 89–119, Oct 2023. [doi]

  Bibtex

  @incollection{Ullah_2023,
  doi = {10.1007/978-3-031-19568-6_4},
  url = {https://doi.org/10.1007%2F978-3-031-19568-6_4},
  year = 2023,
  month = {oct},
  publisher = {Springer International Publishing},
  pages = {89--119},
  author = {Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
  title = {Designing Resource-Efficient Hardware Arithmetic for {FPGA}-Based Accelerators Leveraging Approximations and Mixed Quantizations},
  booktitle = {Embedded Machine Learning for Cyber-Physical, {IoT}, and Edge Computing}
  }

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• 28. Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators", In ACM Trans. Embed. Comput. Syst., Association for Computing Machinery, vol. 22, no. 5s, New York, NY, USA, Sep 2023. [doi] [Bibtex & Downloads]

  AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators

  Reference

  Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators", In ACM Trans. Embed. Comput. Syst., Association for Computing Machinery, vol. 22, no. 5s, New York, NY, USA, Sep 2023. [doi]

  Bibtex

  @article{10.1145/3609096,
  author = {Sahoo, Siva Satyendra and Ullah, Salim and Kumar, Akash},
  title = {AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators},
  year = {2023},
  issue_date = {October 2023},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  volume = {22},
  number = {5s},
  issn = {1539-9087},
  url = {https://doi.org/10.1145/3609096},
  doi = {10.1145/3609096},
  journal = {ACM Trans. Embed. Comput. Syst.},
  month = sep,
  articleno = {101},
  numpages = {26},
  keywords = {Monte Carlo Tree Search, AI-based exploration, Approximate computing, circuit synthesis, automated hardware design, arithmetic operator design, computer arithmetic}
  }

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  AxOTreeS-cases-esweek-tecs-2023 [PDF]

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• 27. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers", In IEEE Embedded Systems Letters, pp. 1-1, 2023. [doi] [Bibtex & Downloads]

  High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers

  Reference

  Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers", In IEEE Embedded Systems Letters, pp. 1-1, 2023. [doi]

  Bibtex

  @ARTICLE{10261986,
  author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
  journal={IEEE Embedded Systems Letters},
  title={High Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers},
  year={2023},
  volume={},
  number={},
  pages={1-1},
  doi={10.1109/LES.2023.3298736}}

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  ESL_LB_CASES_2023 Camera ready [PDF]

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• 26. Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi] [Bibtex & Downloads]

  NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories

  Reference

  Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "NvMISC: Towards an FPGA-Based Emulation Platform for RISC-V and Non-Volatile Memories", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2023. [doi]

  Bibtex

  @article{Zhao_2023,
  doi = {10.1109/les.2023.3299202},
  url = {https://doi.org/10.1109%2Fles.2023.3299202},
  year = 2023,
  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
  pages = {1--1},
  author = {Yuankang Zhao and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
  title = {{NvMISC}: Towards an {FPGA}-Based Emulation Platform for {RISC}-V and Non-Volatile Memories},
  journal = {{IEEE} Embedded Systems Letters}
  }

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  NvMISC_Towards_an_FPGA-Based_Emulation_Platform_for_RISC-V_and_Non-Volatile_Memories_ESL [PDF]

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• 25. Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators", Proceedings of the Great Lakes Symposium on VLSI 2023, ACM, Jun 2023. [doi] [Bibtex & Downloads]

  CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators

  Reference

  Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators", Proceedings of the Great Lakes Symposium on VLSI 2023, ACM, Jun 2023. [doi]

  Bibtex

  @inproceedings{Ullah_2023,
  doi = {10.1145/3583781.3590222},
  url = {https://doi.org/10.1145%2F3583781.3590222},
  year = 2023,
  month = {jun},
  publisher = ,
  author = {Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
  title = {{CoOAx}: Correlation-aware Synthesis of {FPGA}-based Approximate Operators},
  booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023}
  }

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  Application_specific_AI_inference_on_FPGAs-5 [PDF]

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• 24. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi] [Bibtex & Downloads]

  NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs

  Reference

  Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi]

  Bibtex

  @INPROCEEDINGS{10196610,
  author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
  booktitle={2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
  title={NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs},
  year={2023},
  volume={},
  number={},
  pages={85-92},
  doi={10.1109/IPDPSW59300.2023.00026}}

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  RAW2023-NetPU-M [PDF]

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• 23. Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks", Proceedings of the 28th Asia and South Pacific Design Automation Conference, ACM, Jan 2023. [doi] [Bibtex & Downloads]

  SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks

  Reference

  Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks", Proceedings of the 28th Asia and South Pacific Design Automation Conference, ACM, Jan 2023. [doi]

  Bibtex

  @inproceedings{Ranjan_2023,
  doi = {10.1145/3566097.3567891},
  url = {https://doi.org/10.1145%2F3566097.3567891},
  year = 2023,
  month = {jan},
  publisher = ,
  author = {Rohit Ranjan and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
  title = {{SyFAxO}-{GeN}: Synthesizing FPGA-based Approximate Operators with Generative Networks},
  booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference}
  }

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• 22. Salim Ullah, Akash Kumar, "Approximate Arithmetic Circuit Architectures for FPGA-based Systems", Springer International Publishing, 2023. [doi] [Bibtex & Downloads]

  Approximate Arithmetic Circuit Architectures for FPGA-based Systems

  Reference

  Salim Ullah, Akash Kumar, "Approximate Arithmetic Circuit Architectures for FPGA-based Systems", Springer International Publishing, 2023. [doi]

  Bibtex

  @book{Ullah_2023,
  doi = {10.1007/978-3-031-21294-9},
  url = {https://doi.org/10.1007%2F978-3-031-21294-9},
  year = 2023,
  publisher = {Springer International Publishing},
  author = {Salim Ullah and Akash Kumar},
  title = {Approximate Arithmetic Circuit Architectures for {FPGA}-based Systems}
  }

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• 2022

• 21. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi] [Bibtex & Downloads]

  NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture

  Reference

  Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi]

  Bibtex

  @INPROCEEDINGS{9974206,
  
  author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
  
  booktitle={2022 International Conference on Field-Programmable Technology (ICFPT)},
  
  title={NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture},
  
  year={2022},
  month = {dec},
  pages={1-1},
  doi={10.1109/ICFPT56656.2022.9974206}}

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  NetPU_Prototyping_a_Generic_Reconfigurable_Neural_Network_Accelerator_Architecture [PDF]

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• 20. Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, "ERMES: Efficient Racetrack Memory Emulation System based on FPGA", In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022. [Bibtex & Downloads]

  ERMES: Efficient Racetrack Memory Emulation System based on FPGA

  Reference

  Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, "ERMES: Efficient Racetrack Memory Emulation System based on FPGA", In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022.

  Bibtex

  @INPROCEEDINGS{ERMES,
  author={Fanny Spagnolo and Salim Ullah and Pasquale Corsonello and Akash Kumar},
  booktitle={2022 International Conference on Field-Programmable Logic and Applications (FPL)},
  title={ERMES: Efficient Racetrack Memory Emulation System based on FPGA},
  year={2022},
  month={aug},
  volume={},
  number={},
  pages={1-6}
  }

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  RTM_Emulator_FPL [PDF]

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• 19. Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022. [Bibtex & Downloads]

  PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML

  Reference

  Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022.

  Bibtex

  @InProceedings{posax,
  author = {Amritha Immaneni and Salim Ullah and Suresh Nambi and Siva Satyendra Sahoo and Akash Kumar},
  title = {PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML},
  booktitle = {Euromicro Conference on Digital System Design (DSD)},
  year = {2022},
  month = {Aug},
  pages={1-6},
  }

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  PosAx_O [PDF]

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• 18. Negar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar, "Multi-Precision Deep Neural Network Acceleration on FPGAs" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022. [Bibtex & Downloads]

  Multi-Precision Deep Neural Network Acceleration on FPGAs

  Reference

  Negar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar, "Multi-Precision Deep Neural Network Acceleration on FPGAs" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022.

  Bibtex

  @InProceedings{mehdi_2022_aspdac,
  author = {Negar Neda and Salim Ullah and Azam Ghanbari and Hoda Mahdiani and Mehdi Modarressi and Akash Kumar},
  booktitle = {Asia and South Pacific Design Automation Conference (ASPDAC)},
  title = {Multi-Precision Deep Neural Network Acceleration on {FPGAs}},
  year = {2022},
  month=1,
  organization = {IEEE},
  }

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• 17. Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022. [Bibtex & Downloads]

  AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems

  Reference

  Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022.

  Bibtex

  @article{ullah2022appaxo,
  title={AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems},
  author={Ullah, Salim and Sahoo, Siva Satyendra and Ahmed, Nemath and Chaudhury, Debabrata and Kumar, Akash},
  journal={ACM Transactions on Embedded Computing Systems (TECS)},
  volume={},
  number={},
  pages={1--31},
  year={2022},
  month={January}
  }

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  AppAxO [PDF]

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• 2021

• 16. Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi] [Bibtex & Downloads]

  ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems

  Reference

  Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi]

  Bibtex

  @article{Nambi_2021,
  doi = {10.1109/access.2021.3098730},
  url = {https://doi.org/10.1109%2Faccess.2021.3098730},
  year = 2021,
  month = {July},
  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
  pages = {1--1},
  author = {Suresh Nambi and Salim Ullah and Siva Satyendra Sahoo and Aditya Lohana and Farhad Merchant and Akash Kumar},
  title = {{ExPAN}(N)D: Exploring Posits for Efficient Artificial Neural Network Design in {FPGA}-based Systems},
  journal = {{IEEE} Access}
  }

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  ExPANND_Exploring_Posits_for_Efficient_Artificial_Neural_Network_Design_in_FPGA-based_Systems [PDF]

  Related Paths

  Orchestration Path

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• 15. S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021. [Bibtex & Downloads]

  CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems

  Reference

  S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021.

  Bibtex

  @INPROCEEDINGS{clapped,
  author={S. {Ullah} and S. S. {Sahoo} and A. {Kumar}},
  booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)},
  title={CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems},
  year={2021},
  month={jul},
  volume={},
  number={},
  pages={1-6}
  }

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• 14. Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi] [Bibtex & Downloads]

  Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators

  Reference

  Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi]

  Bibtex

  @article{Ullah_2021,
  doi = {10.1109/les.2020.2995053},
  url = {https://doi.org/10.1109%2Fles.2020.2995053},
  year = 2021,
  month = {jun},
  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
  volume = {13},
  number = {2},
  pages = {41--44},
  author = {Salim Ullah and Tuan Duy Anh Nguyen and Akash Kumar},
  title = {Energy-Efficient Low-Latency Signed Multiplier for {FPGA}-Based Hardware Accelerators},
  journal = {{IEEE} Embedded Systems Letters}
  }

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• 13. Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi] [Bibtex & Downloads]

  MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems

  Reference

  Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi]

  Bibtex

  @inproceedings{10.1145/3453688.3461533,
  author = {Sahoo, Siva Satyendra and Baranwal, Akhil Raj and Ullah, Salim and Kumar, Akash},
  title = {MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems},
  year = {2021},
  month={June},
  isbn = {9781450383936},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/3453688.3461533},
  doi = {10.1145/3453688.3461533},
  pages = {339–346},
  numpages = {8},
  keywords = {memory-centric computing, fpga, energy-efficient computing, high-level synthesis, hardware accelerators},
  location = {Virtual Event, USA},
  series = {GLSVLSI '21}
  }

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• 12. Salim Ullah, Semeen Rehman, Muhammad Shafique, Akash Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi] [Bibtex & Downloads]

  High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators

  Reference

  Salim Ullah, Semeen Rehman, Muhammad Shafique, Akash Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi]

  Bibtex

  @article{Ullah_2021,
  doi = {10.1109/tcad.2021.3056337},
  url = {https://doi.org/10.1109%2Ftcad.2021.3056337},
  year = 2021,
  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
  pages = {1--1},
  author = {Salim Ullah and Semeen Rehman and Muhammad Shafique and Akash Kumar},
  title = {High-Performance Accurate and Approximate Multipliers for {FPGA}-based Hardware Accelerators},
  journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
  }

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• 2020

• 11. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] [Bibtex & Downloads]

  ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems

  Reference

  Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi]

  Bibtex

  @article{Baranwal_2020,
  doi = {10.1109/tcad.2020.3028350},
  url = {https://doi.org/10.1109%2Ftcad.2020.3028350},
  year = 2020,
  month={28 October},
  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
  pages = {1--1},
  author = {Akhil Raj Baranwal and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
  title = {{ReLAccS}: A Multi-level Approach to Accelerator Design for Reinforcement Learning on {FPGA}-based Systems},
  journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  }

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• 10. Arlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors", In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi] [Bibtex & Downloads]

  An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors

  Reference

  Arlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors", In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi]

  Bibtex

  @inproceedings{John_2020,
  doi = {10.1109/icecs49266.2020.9294859},
  url = {https://doi.org/10.1109%2Ficecs49266.2020.9294859},
  year = 2020,
  month = {nov},
  publisher = ,
  author = {Arlene John and Salim Ullah and Akash Kumar and Barry Cardiff and Deepu John},
  title = {An Approximate Binary Classifier for Data Integrity Assessment in {IoT} Sensors},
  booktitle = {2020 27th {IEEE} International Conference on Electronics, Circuits and Systems ({ICECS})}
  }

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• 9. Zahra Ebrahimi, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", Proceedings of the 2020 on Great Lakes Symposium on VLSI, ACM, Sep 2020. [doi] [Bibtex & Downloads]

  SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy

  Reference

  Zahra Ebrahimi, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", Proceedings of the 2020 on Great Lakes Symposium on VLSI, ACM, Sep 2020. [doi]

  Bibtex

  @inproceedings{Ebrahimi_2020,
  doi = {10.1145/3386263.3406907},
  url = {https://doi.org/10.1145%2F3386263.3406907},
  year = 2020,
  month = {sep},
  publisher = ,
  author = {Zahra Ebrahimi and Salim Ullah and Akash Kumar},
  title = {{SIMDive}: Approximate {SIMD} Soft Multiplier-Divider for {FPGAs} with Tunable Accuracy},
  booktitle = {Proceedings of the 2020 on Great Lakes Symposium on {VLSI}}
  }

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• 8. S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks", In IEEE Access, vol. 8, pp. 118899-118911, June 2020. [Bibtex & Downloads]

  ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks

  Reference

  S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks", In IEEE Access, vol. 8, pp. 118899-118911, June 2020.

  Bibtex

  @ARTICLE{9126777,
  author={S. {Gupta} and S. {Ullah} and K. {Ahuja} and A. {Tiwari} and A. {Kumar}},
  journal={IEEE Access},
  title={ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks},
  year={2020},
  month={June},
  volume={8},
  number={},
  pages={118899-118911},}

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• 7. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020. [Bibtex & Downloads]

  Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures

  Reference

  S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020.

  Bibtex

  @ARTICLE{9072581,
  author={S. {Ullah} and H. {Schmidl} and S. S. {Sahoo} and S. {Rehman} and A. {Kumar}},
  journal={IEEE Transactions on Computers},
  title={Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures},
  year={2020},
  month={April},}

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  TC_2019_Accurate_Approx_Multiplier [PDF]

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• 6. S. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]

  L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS

  Reference

  S. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020.

  Bibtex

  @INPROCEEDINGS{date_salim,
  author={S. Ullah and S. Gupta and K. Ahuja and A. Tiwari and A. Kumar},
  booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS},
  year={2020},
  month={March},}

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  L2L_Date_2020 [PDF]

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• 5. Zahra Ebrahimi, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, Jan 2020. [doi] [Bibtex & Downloads]

  LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy

  Reference

  Zahra Ebrahimi, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, Jan 2020. [doi]

  Bibtex

  @inproceedings{Ebrahimi_2020,
  doi = {10.1109/asp-dac47756.2020.9045171},
  url = {https://doi.org/10.1109%2Fasp-dac47756.2020.9045171},
  year = 2020,
  month = {jan},
  publisher = ,
  author = {Zahra Ebrahimi and Salim Ullah and Akash Kumar},
  title = {{LeAp}: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy},
  booktitle = {2020 25th Asia and South Pacific Design Automation Conference ({ASP}-{DAC})}
  }

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• 2019

• 4. Adarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks", Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi] [Bibtex & Downloads]

  Design Methodology for Embedded Approximate Artificial Neural Networks

  Reference

  Adarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks", Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi]

  Bibtex

  @inproceedings{Balaji:2019:DME:3299874.3319490,
  author = {Balaji, Adarsha and Ullah, Salim and Das, Anup and Kumar, Akash},
  title = {Design Methodology for Embedded Approximate Artificial Neural Networks},
  booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI},
  series = {GLSVLSI '19},
  year = {2019},
  month={May},
  isbn = {978-1-4503-6252-8},
  location = {Tysons Corner, VA, USA},
  pages = {489--494},
  numpages = {6},
  url = {http://doi.acm.org/10.1145/3299874.3319490},
  doi = {10.1145/3299874.3319490},
  acmid = {3319490},
  publisher = {ACM},
  address = {New York, NY, USA},
  keywords = {approximate computing, artificial neural networks (anns), fpga},
  }

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• 2018

• 3. Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers", Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018. [Bibtex & Downloads]

  SMApproxlib: library of FPGA-based approximate multipliers

  Reference

  Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers", Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018.

  Bibtex

  @inproceedings{ullah2018smapproxlib,
  title={SMApproxlib: library of FPGA-based approximate multipliers},
  author={Ullah, Salim and Murthy, Sanjeev Sripadraj and Kumar, Akash},
  booktitle={Proceedings of the 55th Annual Design Automation Conference},
  pages={157},
  year={2018},
  month={June},
  organization={ACM}
  }

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• 2. Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators", Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018. [Bibtex & Downloads]

  Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators

  Reference

  Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators", Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018.

  Bibtex

  @inproceedings{ullah2018area,
  title={Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators},
  author={Ullah, Salim and Rehman, Semeen and Prabakaran, Bharath Srinivas and Kriebel, Florian and Hanif, Muhammad Abdullah and Shafique, Muhammad and Kumar, Akash},
  booktitle={Proceedings of the 55th Annual Design Automation Conference},
  pages={159},
  year={2018},
  month={June},
  organization={ACM}
  }

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• 1. B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi] [Bibtex & Downloads]

  DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems

  Reference

  B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi]

  Bibtex

  @INPROCEEDINGS{8342140,
  author={B. S. Prabakaran and S. Rehman and M. A. Hanif and S. Ullah and G. Mazaheri and A. Kumar and M. Shafique},
  booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
  title={DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems},
  year={2018},
  volume={},
  number={},
  pages={917-920},
  keywords={adders;field programmable gate arrays;logic design;public domain software;DeMAS;FPGA community;RTL;approximate adders;area gain;behavioral model;generic design methodology;latency gain;multibit adder architectures;power-delay product gain;Adders;Approximate computing;Delays;Design methodology;Field programmable gate arrays;Hardware;Table lookup;Adders;Approximate Computing;Area;CAD;Design Flow;Efficiency;FPGA;LUTs;Optimization;Performance;Power},
  doi={10.23919/DATE.2018.8342140},
  ISSN={},
  month={March},}

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  DeMAS_DATE_2018 [PDF]

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