Salim Ullah

E-mail

Phone

Fax

Visitor's Address

salim.ullah@tu-dresden.de

+49 351 463-40819

+49 (0)351 463-39995

Helmholtzstrasse 18,  BAR-III62

 

Publications

  • 2020

  • 13. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems" , In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] [Bibtex & Downloads]
  • 12. Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems" , 27 October 2020. [Bibtex & Downloads]
  • 11. Arlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors" , In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi] [Bibtex & Downloads]
  • 10. Zahra Ebrahimi Mamaghani, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy" , In Proceeding: 30th 2020 ACM Great Lakes Symposium on VLSI (GLSVLSI), September 2020. [Bibtex & Downloads]
  • 9. S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks" , In IEEE Access, vol. 8, pp. 118899-118911, June 2020. [Bibtex & Downloads]
  • 8. S. Ullah, T. D. A. Nguyen, A. Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-based Hardware Accelerators" , In IEEE Embedded Systems Letters, May 2020. [Bibtex & Downloads]
  • 7. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures" , In IEEE Transactions on Computers, April 2020. [Bibtex & Downloads]
  • 6. S. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]
  • 5. Zahra Ebrahimi Mamaghani, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy" , In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2020. [Bibtex & Downloads]
  • 2019

  • 4. Adarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks" , Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi] [Bibtex & Downloads]
  • 2018

  • 3. Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers" , Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018. [Bibtex & Downloads]
  • 2. Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators" , Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018. [Bibtex & Downloads]
  • 1. B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems" , In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi] [Bibtex & Downloads]