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Salim Ullah |
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Phone Fax Visitor's Address |
+49 351 463-40811 Helmholtzstrasse 18, BAR-III62 |
Ph.D. Thesis Title: Design, Analysis, and Applications of Approximate Arithmetic Modules
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Publications
2023
- 28. Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "NvMISC: Towards an FPGA-based Emulation Platform for RISC-V and Non-volatile Memories", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), Sep 2023. [Bibtex & Downloads]
NvMISC: Towards an FPGA-based Emulation Platform for RISC-V and Non-volatile Memories
Reference
Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "NvMISC: Towards an FPGA-based Emulation Platform for RISC-V and Non-volatile Memories", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), Sep 2023.
Bibtex
@article{Ullah_misc_2023,
year = 2023,
month = {sep},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
author = {Yuankang Zhao , Salim Ullah , Siva Satyendra Sahoo , and Akash Kumar},
title = ,
journal = {{IEEE} Embedded Systems Letters}
}Downloads
No Downloads available for this publication
Permalink
- 27. Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators", In ACM Trans. Embed. Comput. Syst., Association for Computing Machinery, vol. 22, no. 5s, New York, NY, USA, Sep 2023. [doi] [Bibtex & Downloads]
AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators
Reference
Siva Satyendra Sahoo, Salim Ullah, Akash Kumar, "AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators", In ACM Trans. Embed. Comput. Syst., Association for Computing Machinery, vol. 22, no. 5s, New York, NY, USA, Sep 2023. [doi]
Bibtex
@article{10.1145/3609096,
author = {Sahoo, Siva Satyendra and Ullah, Salim and Kumar, Akash},
title = {AxOTreeS: A Tree Search Approach to Synthesizing FPGA-Based Approximate Operators},
year = {2023},
issue_date = {October 2023},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {22},
number = {5s},
issn = {1539-9087},
url = {https://doi.org/10.1145/3609096},
doi = {10.1145/3609096},
journal = {ACM Trans. Embed. Comput. Syst.},
month = sep,
articleno = {101},
numpages = {26},
keywords = {Monte Carlo Tree Search, AI-based exploration, Approximate computing, circuit synthesis, automated hardware design, arithmetic operator design, computer arithmetic}
}Downloads
AxOTreeS-cases-esweek-tecs-2023 [PDF]
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- 26. Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators", Proceedings of the Great Lakes Symposium on VLSI 2023, ACM, Jun 2023. [doi] [Bibtex & Downloads]
CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators
Reference
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators", Proceedings of the Great Lakes Symposium on VLSI 2023, ACM, Jun 2023. [doi]
Bibtex
@inproceedings{Ullah_2023,
doi = {10.1145/3583781.3590222},
url = {https://doi.org/10.1145%2F3583781.3590222},
year = 2023,
month = {jun},
publisher = ,
author = {Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{CoOAx}: Correlation-aware Synthesis of {FPGA}-based Approximate Operators},
booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023}
}Downloads
Application_specific_AI_inference_on_FPGAs-5 [PDF]
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- 25. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi] [Bibtex & Downloads]
NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs", In Proceeding: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 85-92, 2023. [doi]
Bibtex
@INPROCEEDINGS{10196610,
author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
booktitle={2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
title={NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs},
year={2023},
volume={},
number={},
pages={85-92},
doi={10.1109/IPDPSW59300.2023.00026}}Downloads
RAW2023-NetPU-M [PDF]
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- 24. Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Network", In Proceeding: Asia and South Pacific Design Automation Conference (ASP-DAC), ACM/IEEE, Jan 2023. [Bibtex & Downloads]
SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Network
Reference
Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Network", In Proceeding: Asia and South Pacific Design Automation Conference (ASP-DAC), ACM/IEEE, Jan 2023.
Bibtex
@inproceedings{Rohit_ASPDAC,
year = {2023},
month = {jan},
publisher = ,
author = {Rohit Ranjan and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Network},
booktitle = {Asia and South Pacific Design Automation Conference ({ASP-DAC})}
}Downloads
No Downloads available for this publication
Permalink
- 23. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-precision Multipliers" (to appear), In IEEE Embedded Systems Letters, 2023. [doi] [Bibtex & Downloads]
High Flexibility Designs of Quantized Runtime Reconfigurable Multi-precision Multipliers
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "High Flexibility Designs of Quantized Runtime Reconfigurable Multi-precision Multipliers" (to appear), In IEEE Embedded Systems Letters, 2023. [doi]
Bibtex
@ARTICLE{r2m2,
author={Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar},
journal={IEEE Embedded Systems Letters},
title={High Flexibility Designs of Quantized Runtime Reconfigurable Multi-precision Multipliers},
year={2023},
volume={},
number={},
pages={},
doi={10.1109/LES.2023.3298736}}Downloads
No Downloads available for this publication
Permalink
- 22. Salim Ullah, Akash Kumar, "Approximate Arithmetic Circuit Architectures for FPGA-based Systems", Springer, 2023. [Bibtex & Downloads]
Approximate Arithmetic Circuit Architectures for FPGA-based Systems
Reference
Salim Ullah, Akash Kumar, "Approximate Arithmetic Circuit Architectures for FPGA-based Systems", Springer, 2023.
Bibtex
@book{ullah2023approximate,
title={Approximate Arithmetic Circuit Architectures for FPGA-based Systems},
author={Ullah, Salim and Kumar, Akash},
year={2023},
publisher={Springer}
}Downloads
No Downloads available for this publication
Permalink
2022
- 21. Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi] [Bibtex & Downloads]
NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture
Reference
Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar, "NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture", In Proceeding: 2022 International Conference on Field-Programmable Technology (ICFPT), pp. 1-1, Dec 2022. [doi]
Bibtex
@INPROCEEDINGS{9974206,
author={Liu, Yuhao and Rai, Shubham and Ullah, Salim and Kumar, Akash},
booktitle={2022 International Conference on Field-Programmable Technology (ICFPT)},
title={NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture},
year={2022},
month = {dec},
pages={1-1},
doi={10.1109/ICFPT56656.2022.9974206}}Downloads
NetPU_Prototyping_a_Generic_Reconfigurable_Neural_Network_Accelerator_Architecture [PDF]
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- 20. Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022. [Bibtex & Downloads]
PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML
Reference
Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022.
Bibtex
@InProceedings{posax,
author = {Amritha Immaneni and Salim Ullah and Suresh Nambi and Siva Satyendra Sahoo and Akash Kumar},
title = {PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML},
booktitle = {Euromicro Conference on Digital System Design (DSD)},
year = {2022},
month = {Aug},
pages={1-6},
}Downloads
PosAx_O [PDF]
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- 19. Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, "ERMES: Efficient Racetrack Memory Emulation System based on FPGA", In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022. [Bibtex & Downloads]
ERMES: Efficient Racetrack Memory Emulation System based on FPGA
Reference
Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar, "ERMES: Efficient Racetrack Memory Emulation System based on FPGA", In Proceeding: 2022 International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-6, Aug 2022.
Bibtex
@INPROCEEDINGS{ERMES,
author={Fanny Spagnolo and Salim Ullah and Pasquale Corsonello and Akash Kumar},
booktitle={2022 International Conference on Field-Programmable Logic and Applications (FPL)},
title={ERMES: Efficient Racetrack Memory Emulation System based on FPGA},
year={2022},
month={aug},
volume={},
number={},
pages={1-6}
}Downloads
RTM_Emulator_FPL [PDF]
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- 18. Negar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar, "Multi-Precision Deep Neural Network Acceleration on FPGAs" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022. [Bibtex & Downloads]
Multi-Precision Deep Neural Network Acceleration on FPGAs
Reference
Negar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar, "Multi-Precision Deep Neural Network Acceleration on FPGAs" (to appear), In Proceeding: Asia and South Pacific Design Automation Conference (ASPDAC), 1/2022.
Bibtex
@InProceedings{mehdi_2022_aspdac,
author = {Negar Neda and Salim Ullah and Azam Ghanbari and Hoda Mahdiani and Mehdi Modarressi and Akash Kumar},
booktitle = {Asia and South Pacific Design Automation Conference (ASPDAC)},
title = {Multi-Precision Deep Neural Network Acceleration on {FPGAs}},
year = {2022},
month=1,
organization = {IEEE},
}Downloads
No Downloads available for this publication
Permalink
- 17. Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022. [Bibtex & Downloads]
AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems
Reference
Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022.
Bibtex
@article{ullah2022appaxo,
title={AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems},
author={Ullah, Salim and Sahoo, Siva Satyendra and Ahmed, Nemath and Chaudhury, Debabrata and Kumar, Akash},
journal={ACM Transactions on Embedded Computing Systems (TECS)},
volume={},
number={},
pages={1--31},
year={2022},
month={January}
}Downloads
AppAxO [PDF]
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2021
- 16. Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi] [Bibtex & Downloads]
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
Reference
Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi]
Bibtex
@article{Nambi_2021,
doi = {10.1109/access.2021.3098730},
url = {https://doi.org/10.1109%2Faccess.2021.3098730},
year = 2021,
month = {July},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Suresh Nambi and Salim Ullah and Siva Satyendra Sahoo and Aditya Lohana and Farhad Merchant and Akash Kumar},
title = {{ExPAN}(N)D: Exploring Posits for Efficient Artificial Neural Network Design in {FPGA}-based Systems},
journal = {{IEEE} Access}
}Downloads
ExPANND_Exploring_Posits_for_Efficient_Artificial_Neural_Network_Design_in_FPGA-based_Systems [PDF]
Related Paths
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- 15. S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021. [Bibtex & Downloads]
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems
Reference
S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021.
Bibtex
@INPROCEEDINGS{clapped,
author={S. {Ullah} and S. S. {Sahoo} and A. {Kumar}},
booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)},
title={CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems},
year={2021},
month={jul},
volume={},
number={},
pages={1-6}
}Downloads
CLAppED_A_Design_Framework_for_Implementing_Cross-Layer_Approximation_in_FPGA-based_Embedded_Systems [PDF]
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- 14. Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi] [Bibtex & Downloads]
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
Reference
Salim Ullah, Tuan Duy Anh Nguyen, Akash Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators", In IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers (IEEE), vol. 13, no. 2, pp. 41–44, Jun 2021. [doi]
Bibtex
@article{Ullah_2021,
doi = {10.1109/les.2020.2995053},
url = {https://doi.org/10.1109%2Fles.2020.2995053},
year = 2021,
month = {jun},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
volume = {13},
number = {2},
pages = {41--44},
author = {Salim Ullah and Tuan Duy Anh Nguyen and Akash Kumar},
title = {Energy-Efficient Low-Latency Signed Multiplier for {FPGA}-Based Hardware Accelerators},
journal = {{IEEE} Embedded Systems Letters}
}Downloads
ESL_acc_multiplier [PDF]
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- 13. Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi] [Bibtex & Downloads]
MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems
Reference
Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi]
Bibtex
@inproceedings{10.1145/3453688.3461533,
author = {Sahoo, Siva Satyendra and Baranwal, Akhil Raj and Ullah, Salim and Kumar, Akash},
title = {MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems},
year = {2021},
month={June},
isbn = {9781450383936},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3453688.3461533},
doi = {10.1145/3453688.3461533},
pages = {339–346},
numpages = {8},
keywords = {memory-centric computing, fpga, energy-efficient computing, high-level synthesis, hardware accelerators},
location = {Virtual Event, USA},
series = {GLSVLSI '21}
}Downloads
No Downloads available for this publication
Permalink
- 12. Salim Ullah, Semeen Rehman, Muhammad Shafique, Akash Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi] [Bibtex & Downloads]
High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators
Reference
Salim Ullah, Semeen Rehman, Muhammad Shafique, Akash Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-based Hardware Accelerators", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 2021. [doi]
Bibtex
@article{Ullah_2021,
doi = {10.1109/tcad.2021.3056337},
url = {https://doi.org/10.1109%2Ftcad.2021.3056337},
year = 2021,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Salim Ullah and Semeen Rehman and Muhammad Shafique and Akash Kumar},
title = {High-Performance Accurate and Approximate Multipliers for {FPGA}-based Hardware Accelerators},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
}Downloads
acc_app_TCAD [PDF]
Related Paths
other
Permalink
2020
- 11. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] [Bibtex & Downloads]
ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems
Reference
Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi]
Bibtex
@article{Baranwal_2020,
doi = {10.1109/tcad.2020.3028350},
url = {https://doi.org/10.1109%2Ftcad.2020.3028350},
year = 2020,
month={28 October},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Akhil Raj Baranwal and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{ReLAccS}: A Multi-level Approach to Accelerator Design for Reinforcement Learning on {FPGA}-based Systems},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
}Downloads
ReLAccS_TCAD_Author-prepared [PDF]
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- 10. Arlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors", In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi] [Bibtex & Downloads]
An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors
Reference
Arlene John, Salim Ullah, Akash Kumar, Barry Cardiff, Deepu John, "An Approximate Binary Classifier for Data Integrity Assessment in IoT Sensors", In Proceeding: 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), IEEE, Nov 2020. [doi]
Bibtex
@inproceedings{John_2020,
doi = {10.1109/icecs49266.2020.9294859},
url = {https://doi.org/10.1109%2Ficecs49266.2020.9294859},
year = 2020,
month = {nov},
publisher = ,
author = {Arlene John and Salim Ullah and Akash Kumar and Barry Cardiff and Deepu John},
title = {An Approximate Binary Classifier for Data Integrity Assessment in {IoT} Sensors},
booktitle = {2020 27th {IEEE} International Conference on Electronics, Circuits and Systems ({ICECS})}
}Downloads
Approximate_binary_classifier [PDF]
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- 9. Zahra Ebrahimi, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", Proceedings of the 2020 on Great Lakes Symposium on VLSI, ACM, Sep 2020. [doi] [Bibtex & Downloads]
SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy
Reference
Zahra Ebrahimi, Salim Ullah, Akash Kumar, "SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy", Proceedings of the 2020 on Great Lakes Symposium on VLSI, ACM, Sep 2020. [doi]
Bibtex
@inproceedings{Ebrahimi_2020,
doi = {10.1145/3386263.3406907},
url = {https://doi.org/10.1145%2F3386263.3406907},
year = 2020,
month = {sep},
publisher = ,
author = {Zahra Ebrahimi and Salim Ullah and Akash Kumar},
title = {{SIMDive}: Approximate {SIMD} Soft Multiplier-Divider for {FPGAs} with Tunable Accuracy},
booktitle = {Proceedings of the 2020 on Great Lakes Symposium on {VLSI}}
}Downloads
SIMDive_GLSVLSI_2020 [PDF]
Related Paths
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- 8. S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks", In IEEE Access, vol. 8, pp. 118899-118911, June 2020. [Bibtex & Downloads]
ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks
Reference
S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, A. Kumar, "ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks", In IEEE Access, vol. 8, pp. 118899-118911, June 2020.
Bibtex
@ARTICLE{9126777,
author={S. {Gupta} and S. {Ullah} and K. {Ahuja} and A. {Tiwari} and A. {Kumar}},
journal={IEEE Access},
title={ALigN: A Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks},
year={2020},
month={June},
volume={8},
number={},
pages={118899-118911},}Downloads
ALigN [PDF]
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- 7. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020. [Bibtex & Downloads]
Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures
Reference
S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020.
Bibtex
@ARTICLE{9072581,
author={S. {Ullah} and H. {Schmidl} and S. S. {Sahoo} and S. {Rehman} and A. {Kumar}},
journal={IEEE Transactions on Computers},
title={Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures},
year={2020},
month={April},}Downloads
TC_2019_Accurate_Approx_Multiplier [PDF]
Permalink
- 6. S. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]
L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS
Reference
S. Ullah, S. Gupta, K. Ahuja, A. Tiwari, A. Kumar, "L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS", In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020.
Bibtex
@INPROCEEDINGS{date_salim,
author={S. Ullah and S. Gupta and K. Ahuja and A. Tiwari and A. Kumar},
booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={L2L: A HIGHLY ACCURATE LOG_2_LEAD QUANTIZATION OF PRE-TRAINED NEURAL NETWORKS},
year={2020},
month={March},}Downloads
L2L_Date_2020 [PDF]
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- 5. Zahra Ebrahimi, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, Jan 2020. [doi] [Bibtex & Downloads]
LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy
Reference
Zahra Ebrahimi, Salim Ullah, Akash Kumar, "LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy", In Proceeding: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, Jan 2020. [doi]
Bibtex
@inproceedings{Ebrahimi_2020,
doi = {10.1109/asp-dac47756.2020.9045171},
url = {https://doi.org/10.1109%2Fasp-dac47756.2020.9045171},
year = 2020,
month = {jan},
publisher = ,
author = {Zahra Ebrahimi and Salim Ullah and Akash Kumar},
title = {{LeAp}: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy},
booktitle = {2020 25th Asia and South Pacific Design Automation Conference ({ASP}-{DAC})}
}Downloads
LeAp- [PDF]
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2019
- 4. Adarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks", Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi] [Bibtex & Downloads]
Design Methodology for Embedded Approximate Artificial Neural Networks
Reference
Adarsha Balaji, Salim Ullah, Anup Das, Akash Kumar, "Design Methodology for Embedded Approximate Artificial Neural Networks", Proceedings of the 2019 on Great Lakes Symposium on VLSI, ACM, pp. 489–494, New York, NY, USA, May 2019. [doi]
Bibtex
@inproceedings{Balaji:2019:DME:3299874.3319490,
author = {Balaji, Adarsha and Ullah, Salim and Das, Anup and Kumar, Akash},
title = {Design Methodology for Embedded Approximate Artificial Neural Networks},
booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI},
series = {GLSVLSI '19},
year = {2019},
month={May},
isbn = {978-1-4503-6252-8},
location = {Tysons Corner, VA, USA},
pages = {489--494},
numpages = {6},
url = {http://doi.acm.org/10.1145/3299874.3319490},
doi = {10.1145/3299874.3319490},
acmid = {3319490},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {approximate computing, artificial neural networks (anns), fpga},
}Downloads
p489-balaji [PDF]
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2018
- 3. Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators", Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018. [Bibtex & Downloads]
Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators
Reference
Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar, "Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators", Proceedings of the 55th Annual Design Automation Conference, pp. 159, June 2018.
Bibtex
@inproceedings{ullah2018area,
title={Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators},
author={Ullah, Salim and Rehman, Semeen and Prabakaran, Bharath Srinivas and Kriebel, Florian and Hanif, Muhammad Abdullah and Shafique, Muhammad and Kumar, Akash},
booktitle={Proceedings of the 55th Annual Design Automation Conference},
pages={159},
year={2018},
month={June},
organization={ACM}
}Downloads
PID5307263 [PDF]
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- 2. Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers", Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018. [Bibtex & Downloads]
SMApproxlib: library of FPGA-based approximate multipliers
Reference
Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar, "SMApproxlib: library of FPGA-based approximate multipliers", Proceedings of the 55th Annual Design Automation Conference, pp. 157, June 2018.
Bibtex
@inproceedings{ullah2018smapproxlib,
title={SMApproxlib: library of FPGA-based approximate multipliers},
author={Ullah, Salim and Murthy, Sanjeev Sripadraj and Kumar, Akash},
booktitle={Proceedings of the 55th Annual Design Automation Conference},
pages={157},
year={2018},
month={June},
organization={ACM}
}Downloads
PID5307267 [PDF]
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- 1. B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi] [Bibtex & Downloads]
DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems
Reference
B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems", In Proceeding: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 917-920, March 2018. [doi]
Bibtex
@INPROCEEDINGS{8342140,
author={B. S. Prabakaran and S. Rehman and M. A. Hanif and S. Ullah and G. Mazaheri and A. Kumar and M. Shafique},
booktitle={2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems},
year={2018},
volume={},
number={},
pages={917-920},
keywords={adders;field programmable gate arrays;logic design;public domain software;DeMAS;FPGA community;RTL;approximate adders;area gain;behavioral model;generic design methodology;latency gain;multibit adder architectures;power-delay product gain;Adders;Approximate computing;Delays;Design methodology;Field programmable gate arrays;Hardware;Table lookup;Adders;Approximate Computing;Area;CAD;Design Flow;Efficiency;FPGA;LUTs;Optimization;Performance;Power},
doi={10.23919/DATE.2018.8342140},
ISSN={},
month={March},}Downloads
DeMAS_DATE_2018 [PDF]
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