Andrés Goens

portrait andres goens




Visitor's Address

+49 (0)351 463 43710

+49 (0)351 463 39995

Georg-Schumann-Str. 7A
2nd floor, room 205
01187 Dresden


Curriculum Vitae

Andrés Goens received a Bachelor of Science degree in Physics and one in Mathematics from RWTH Aachen University in Germany in 2012. In 2014 he received his Master's degree in Mathematics also from RWTH Aachen University.
In October 2014 he joined the Chair for Compiler Construction at cfaed in TU Dresden as a Ph.D. student.

In the field of computer science, Goens has worked on numerous projects including the FLINT fast library for number theory, as part of the DFG Priority program SPP1489 with Universtität Kaiserslautern. Between 2013 and 2014 he worked optimizing memory allocation for multicore architectures with the Institute for Communication Technologies and Embeded Systems (ICE) at RWTH Aachen University.

Open Topics

Some possible topics for a Bachelor/Master/Diploma Thesis or SHK/WHK. Projects adaptable depending on level (just ask):

  • MIMO Iterative Decoder as KPN:

    Kahn process networks
    (KPN) are an abstraction for modeling computation which makes communication patterns explicit. They can be used to analyze applications and automatically deploy it to diverse, parallel and heterogeneous platforms. In this project you would port a MIMO Decoder to a KPN formalism and collaborate to modify it for being an iterative decoder. 

    Requirements: Good knowledge of C/C++
    Beneficial: background in signal processing

    Source: Wikipedia
    [source: Wikipedia]

  • Synchronous data flow subgraph recognition:

    Synchronous data flow (SDF) is a way of modeling computation in which so-called actors execute in parallel and exchange fixed amounts of data in a defined manner. They can be seen as a special case of Kahn process networks, a formalism which does not require defined, fixed exchanges of data. This behavior allows greater analysis to be done to optimize execution of algorithms expressed as SDF. In this project you would use static code analysis (control- and dataflow) to recognize this behavior, allowing for greater optimization in executing algorithms.

    Requirements: Good knowledge of C/C++ or  Haskell (fun project!) or Python (maybe, ask me!), 
    Beneficial: basic compiler construction knowledge (control-flow graph, data-flow analysis)
    Source: Wikpedia
    [source: Wikipedia]

  • Symmetries in Architectures:

    Computer architectures are growing to include several different processing cores. Mostly, however, many of the cores are identical, which gives symmetries to the architectures. In this project you would use the mathematical methods of group theory to exploit these symmetries. You would work using the GAP software tool

    Requirements: Programming experience (any language), mathematical affinity
    Beneficial: Basic knowledge of rigorous mathematics, in particular, group theory

    Source: Wikipedia
    [source: Wikipedia]

In case of interest do not hesitate to contact me:


  • 2017

  • Andrés Goens, Sergio Siccha, Jeronimo Castrillon, "Symmetry in Software Synthesis" , In ACM Transactions on Architecture and Code Optimization (TACO), ACM, vol. 14, no. 2, pp. 20:1–20:26, New York, NY, USA, Jul 2017. [doi] [Bibtex & Downloads]
  • Andrés Goens, Robert Khasanov, Marcus Hähnel, Till Smejkal, Hermann Härtig, Jeronimo Castrillon, "TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings" , Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES 17), ACM, pp. 11–20, New York, NY, USA, Jun 2017. [doi] [Bibtex & Downloads]
  • Gerald Hempel, Andrés Goens, Josefine Asmus, Jeronimo Castrillon, Ivo F. Sbalzarini, "Robust Mapping of Process Networks to Many-Core Systems Using Bio-Inspired Design Centering" , Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES 17), ACM, pp. 21–30, New York, NY, USA, Jun 2017. [doi] [Bibtex & Downloads]
  • Andrés Goens, Jeronimo Castrillon, "Optimizing for Data-Parallelism in Kahn Process Networks" , In Proceeding: ACM SRC at International Symposium on Code Generationand Optimization (CGO), Feb 2017. [Bibtex & Downloads]
  • 2016

  • Marcus Völp, Sascha Klüppelholz, Jeronimo Castrillon, Hermann Härtig, Nils Asmussen, Uwe Assmann, Franz Baader, Christel Baier, Gerhard Fettweis, Jochen Fröhlich, Andres Goens, Sebastian Haas, Dirk Habich, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Wolfgang Lehner, Linda Leuschner, Matthias Lieber, Siqi Ling, Steffen Märcker, Johannes Mey, Wolfgang Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, "The Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware" , Proceedings of the 1st International Workshop on Post-Moore s Era Supercomputing (PMES), Co-located with The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16), Salt Lake City, USA, Nov 2016. [Bibtex & Downloads]
  • Christian Menard, Andrés Goens, Jeronimo Castrillon, "High-Level NoC Model for MPSoC Compilers" , Proceedings of the IEEE Nordic Circuits and Systems Conference (NORCAS 16), pp. 1-6, Copenhagen, Denmark, Nov 2016. [doi] [Bibtex & Downloads]
  • Andres Goens, Robert Khasanov, Jeronimo Castrillon, Simon Polstra, Andy Pimentel, "Why Comparing System-level MPSoC Mapping Approaches is Difficult: a Case Study" , Proceedings of the IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), pp. 281-288, Ecole Centrale de Lyon, Lyon, France, Sep 2016. [doi] [Bibtex & Downloads]
  • Andrés Goens, Jeronimo Castrillon, Maximilian Odendahl, Rainer Leupers, "An Optimal Allocation of Memory Buffers for Complex Multicore Platforms" , In Journal of Systems Architecture, Elsevier, vol. 66-67, pp. 69–83, May 2016. [doi] [Bibtex & Downloads]
  • 2015

  • Andrés Goens, Jeronimo Castrillon, "Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs" , In Proceeding: IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), November 3 - 6, 2015, Foz do Iguaçu, Brazil, 2015. [Bibtex & Downloads]
  • 2014

  • Maximilian Odendahl, Andrés Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vöcking, Tomas Henriksson, "Optimized buffer allocation in multicore platforms" , Proceedings of the conference on Design, Automation & Test in Europe, pp. 324, 2014. [Bibtex & Downloads]