Siva Satyendra Sahoo |
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Fax Visitor's Address |
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Siva Satyendra is currently working as a Postdoctoral Researcher for the project "Predictive Self-learning Control for Building Facades Using FPGAs (PRÄKLIMA FASSADE)". He has obtained his Ph.D. from the National University of Singapore, Singapore. His doctoral thesis focused on Cross-layer Reliability for Heterogeneous Embedded Systems and spanned from 2015-2019. He completed his masters (M.Tech) from the Indian Institute of Science, Bangalore in 2010-2012 in the specialization Electronics Design Technology. His master's thesis focused on Hardware Accelerator for Support Vector Machines. He has also worked with Intel India, Bangalore during 2012-2014 in the domain of Physical Design. His work at Intel focused on improving reliability during SoC Integration of dense integrated circuits for smartphones/tablets. His research interests include Embedded Systems, Machine Learning, Reconfigurable Computing, Reliability-aware Computing Systems, and System-level Design.
Recent Talks/Tutorials
DAC 2020 (PhD Forum)
DAC 2020 (Research Contribution)
DFTS 2020
Publications
2022
- 21. Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), January 2022. [doi] [Bibtex & Downloads]
BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems
×Reference
Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), January 2022. [doi]
Bibtex
@article{Ranjbar_2022_tcad,
year = 2022,
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
month ={January},
author = {Behnaz Ranjbar and Ali Hosseinghorban and Siva Satyendra Sahoo and Alireza Ejlali and Akash Kumar},
title = {BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
doi={10.1109/TCAD.2021.3127867}
}Downloads
Behnaz_TCAD_DATE2021_Extension_Camera_ready [PDF]
Permalink
2021
- 20. Siva Satyendra Sahoo, Akash Kumar, "CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. [Bibtex & Downloads]
CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems
×Reference
Siva Satyendra Sahoo, Akash Kumar, "CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021.
Bibtex
@INPROCEEDINGS{siva-vlsisoc2021-cleocode,
author={Siva Satyendra Sahoo and Akash Kumar},
booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC)},
title={CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems},
year={2021},
month={Oct},
volume={},
number={}}Downloads
CLEOCoDe [PDF]
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- 19. Siva Satyendra Sahoo, Akash Kumar, "Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. [Bibtex & Downloads]
Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems
×Reference
Siva Satyendra Sahoo, Akash Kumar, "Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021.
Bibtex
@INPROCEEDINGS{siva-vlsisoc2021-mctsclr,
author={Siva Satyendra Sahoo and Akash Kumar},
booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC)},
title={Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems},
year={2021},
month={Oct},
volume={},
number={}}Downloads
MCTS_CLRIntegTMap [PDF]
Permalink
- 18. Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel Chang Bing Wong, Geoff Merrett, Yinyuan Zhao, Xiaohang Wang, Amit Kumar Singh, "Emergent design challenges for embedded systems and paths forward: Mixed-criticality, energy, reliability and security perspectives: Special Session Paper" (to appear), In Proceeding: The International Conference on Hardware/Software Codesign and System Synthesis 2021 (10/10/21 - 13/10/21), October 2021. [Bibtex & Downloads]
Emergent design challenges for embedded systems and paths forward: Mixed-criticality, energy, reliability and security perspectives: Special Session Paper
×Reference
Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel Chang Bing Wong, Geoff Merrett, Yinyuan Zhao, Xiaohang Wang, Amit Kumar Singh, "Emergent design challenges for embedded systems and paths forward: Mixed-criticality, energy, reliability and security perspectives: Special Session Paper" (to appear), In Proceeding: The International Conference on Hardware/Software Codesign and System Synthesis 2021 (10/10/21 - 13/10/21), October 2021.
Abstract
Modern embedded systems need to cater for several needs depending upon the application domain in which they are deployed. For example, mixed-critically needs to be considered for real-time and safety-critical systems and energy for battery-operated systems. At the same time, many of these systems demand for their reliability and security as well. With electronic systems being used for increasingly varying type of applications, novel challenges have emerged. For example, with the use of embedded systems in increasingly complex applications that execute tasks with varying priorities, mixed-criticality systems present unique challenges to designing reliable systems. The large design space involved in implementing cross-layer reliability in heterogeneous systems, particularly for mixed-critical systems, poses new research problems. Further, malicious security attacks on these systems pose additional extraordinary challenges in the system design. In this paper, we cover both the industry and academia perspectives of the challenges posed by these emergent aspects of system design towards designing high-performance, energy-efficient, reliable and/or secure embedded systems. We also provide our views on paths forward.
Bibtex
@inproceedings{esweek2021,
booktitle = {The International Conference on Hardware/Software Codesign and System Synthesis 2021 (10/10/21 - 13/10/21)},
month = {October},
title = {Emergent design challenges for embedded systems and paths forward: Mixed-criticality, energy, reliability and security perspectives: Special Session Paper},
author = {Siva Satyendra Sahoo and Akash Kumar and Martin Decky and Samuel Chang Bing Wong and Geoff Merrett and Yinyuan Zhao and Xiaohang Wang and Amit Kumar Singh},
year = {2021},
keywords = {Mixed-criticality, reliability, energy-efficiency, aging attack, covert channel attack, attack mitigation},
abstract = {Modern embedded systems need to cater for several needs depending upon the application domain in which they are deployed. For example, mixed-critically needs to be considered for real-time and safety-critical systems and energy for battery-operated systems. At the same time, many of these systems demand for their reliability and security as well. With electronic systems being used for increasingly varying type of applications, novel challenges have emerged. For example, with the use of embedded systems in increasingly complex applications that execute tasks with varying priorities, mixed-criticality systems present unique challenges to designing reliable systems. The large design space involved in implementing cross-layer reliability in heterogeneous systems, particularly for mixed-critical systems, poses new research problems. Further, malicious security attacks on these systems pose additional extraordinary challenges in the system design. In this paper, we cover both the industry and academia perspectives of the challenges posed by these emergent aspects of system design towards designing high-performance, energy-efficient, reliable and/or secure embedded systems. We also provide our views on paths forward.}
}Downloads
ESWEEK_2021_SS [PDF]
Related Paths
Permalink
- 17. S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems" (to appear), In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021. [Bibtex & Downloads]
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems
×Reference
S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems" (to appear), In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021.
Bibtex
@INPROCEEDINGS{clapped,
author={S. {Ullah} and S. S. {Sahoo} and A. {Kumar}},
booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)},
title={CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems},
year={2021},
month={jul},
volume={},
number={},
pages={1-6}
}Downloads
No Downloads available for this publication
Permalink
- 16. Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi] [Bibtex & Downloads]
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
×Reference
Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi]
Bibtex
@article{Nambi_2021,
doi = {10.1109/access.2021.3098730},
url = {https://doi.org/10.1109%2Faccess.2021.3098730},
year = 2021,
month = {July},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Suresh Nambi and Salim Ullah and Siva Satyendra Sahoo and Aditya Lohana and Farhad Merchant and Akash Kumar},
title = {{ExPAN}(N)D: Exploring Posits for Efficient Artificial Neural Network Design in {FPGA}-based Systems},
journal = {{IEEE} Access}
}Downloads
ExPANND_Exploring_Posits_for_Efficient_Artificial_Neural_Network_Design_in_FPGA-based_Systems [PDF]
Related Paths
Permalink
- 15. Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi] [Bibtex & Downloads]
MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems
×Reference
Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi]
Bibtex
@inproceedings{10.1145/3453688.3461533,
author = {Sahoo, Siva Satyendra and Baranwal, Akhil Raj and Ullah, Salim and Kumar, Akash},
title = {MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems},
year = {2021},
month={June},
isbn = {9781450383936},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3453688.3461533},
doi = {10.1145/3453688.3461533},
pages = {339–346},
numpages = {8},
keywords = {memory-centric computing, fpga, energy-efficient computing, high-level synthesis, hardware accelerators},
location = {Virtual Event, USA},
series = {GLSVLSI '21}
}Downloads
No Downloads available for this publication
Permalink
- 14. Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 264-269, Feb. 2021. [doi] [Bibtex & Downloads]
Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem
×Reference
Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 264-269, Feb. 2021. [doi]
Bibtex
@INPROCEEDINGS{behnaz2021date,
author={Ranjbar, Behnaz and Hosseinghorban, Ali and Sahoo, Siva Satyendra and Ejlali, Alireza and Kumar, Akash},
booktitle={2021 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
title={Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem},
year={2021},
month={Feb.},
volume={},
number={},
pages={264-269},
organization={IEEE},
doi={10.23919/DATE51398.2021.9474263}}Downloads
Improving_Timing_DATE21 [PDF]
Permalink
- 13. Siva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar, "Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 1, pp. 7, Jan 2021. [doi] [Bibtex & Downloads]
Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper
×Reference
Siva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar, "Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 1, pp. 7, Jan 2021. [doi]
Bibtex
@article{Sahoo_2021,
doi = {10.3390/jlpea11010007},
url = {https://doi.org/10.3390%2Fjlpea11010007},
year = 2021,
month = {jan},
publisher = {{MDPI} {AG}},
volume = {11},
number = {1},
pages = {7},
author = {Siva Satyendra Sahoo and Behnaz Ranjbar and Akash Kumar},
title = {Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper},
journal = {Journal of Low Power Electronics and Applications}
}Downloads
jlpea-11-00007 [PDF]
Permalink
2020
- 12. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] [Bibtex & Downloads]
ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems
×Reference
Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi]
Bibtex
@article{Baranwal_2020,
doi = {10.1109/tcad.2020.3028350},
url = {https://doi.org/10.1109%2Ftcad.2020.3028350},
year = 2020,
month={28 October},
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Akhil Raj Baranwal and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{ReLAccS}: A Multi-level Approach to Accelerator Design for Reinforcement Learning on {FPGA}-based Systems},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems},
}Downloads
No Downloads available for this publication
Permalink
- 11. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems", In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020. [Bibtex & Downloads]
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems
×Reference
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems", In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020.
Bibtex
@InProceedings{SahooVK020,
author = {Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
title = ,
booktitle = {2020 {IEEE} {International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020}},
year = {2020},
month = {October},
}Downloads
No Downloads available for this publication
Permalink
- 10. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems", Proceedings of the 57th Annual Design Automation Conference 2020, Association for Computing Machinery, New York, NY, USA, July 2020. [Bibtex & Downloads]
CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems
×Reference
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems", Proceedings of the 57th Annual Design Automation Conference 2020, Association for Computing Machinery, New York, NY, USA, July 2020.
Bibtex
@INPROCEEDINGS{9218747,
author={S. S. {Sahoo} and B. {Veeravalli} and A. {Kumar}},
booktitle={2020 57th ACM/IEEE Design Automation Conference (DAC)},
title={CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems},
year={2020},
volume={},
number={},
pages={1-6},
doi={10.1109/DAC18072.2020.9218747}}Downloads
CLRIntegTMap_DAC2020_CameraReady(1) [PDF]
Related Paths
Permalink
- 9. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020. [Bibtex & Downloads]
Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures
×Reference
S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020.
Bibtex
@ARTICLE{9072581,
author={S. {Ullah} and H. {Schmidl} and S. S. {Sahoo} and S. {Rehman} and A. {Kumar}},
journal={IEEE Transactions on Computers},
title={Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures},
year={2020},
month={April},}Downloads
TC_2019_Accurate_Approx_Multiplier [PDF]
Permalink
- 8. Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi] [Bibtex & Downloads]
DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies
×Reference
Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi]
Bibtex
@inproceedings{Rai_2020,
doi = {10.23919/date48585.2020.9116216},
url = {https://doi.org/10.23919%2Fdate48585.2020.9116216},
year = 2020,
month = {mar},
publisher = ,
author = {Shubham Rai and Michael Raitza and Siva Satyendra Sahoo and Akash Kumar},
title = {{DiSCERN}: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&} Exhibition ({DATE})}
}Downloads
DiSCERN_DATE_2020 [PDF]
Permalink
2019
- 7. S. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems", Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019. [doi] [Bibtex & Downloads]
A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems
×Reference
S. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems", Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019. [doi]
Bibtex
@inproceedings{SahooVK019_1,
author = {S. S. Sahoo and B. Veeravalli and A. Kumar},
title = ,
booktitle = ,
series = {DAC '19},
year = {2019},
month={june},
isbn = {978-1-4503-6725-7/19/06},
location = {Las Vegas, NV, USA},
numpages = {6},
url = {http://doi.acm.org/10.1145/3316781.3317746},
doi = {10.1145/3316781.3317746},
acmid = {3317746},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {Cross-layer Reliability, Run-time Resource Management, Embedded Systems, Reinforcement Learning},
}Downloads
a38-Sahoo [PDF]
Permalink
2018
- 6. S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning", In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), pp. 230-233, Dec 2018. [doi] [Bibtex & Downloads]
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning
×Reference
S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning", In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), pp. 230-233, Dec 2018. [doi]
Bibtex
@INPROCEEDINGS{8742320,
author={S. S. {Sahoo} and T. D. A. {Nguyen} and B. {Veeravalli} and A. {Kumar}},
booktitle={2018 International Conference on Field-Programmable Technology (FPT)},
title={QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning},
year={2018},
volume={},
number={},
pages={230-233},
keywords={circuit optimisation;field programmable gate arrays;integrated circuit design;integrated circuit reliability;logic design;quality of service;Dynamic Partial Reconfiguration;QoS-aware cross-layer reliability-integrated design methodology;FPGA-based DPR systems;FPGA-based dynamic partially reconfigurable system;partially reconfigurable modules;quality of service;fault-mitigation;Conferences;Cross-layer Reliability;Dynamic Partial Reconfiguration;Field Programmable Gate Array;Embedded Systems},
doi={10.1109/FPT.2018.00041},
ISSN={},
month={Dec},}Downloads
08742320 [PDF]
Permalink
- 5. S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems", In Integration, November 2018. [doi] [Bibtex & Downloads]
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems
×Reference
S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems", In Integration, November 2018. [doi]
Abstract
Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification.
Bibtex
@article{SAHOO2018,
title = "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems",
journal = "Integration",
year = "2018",
month={November},
issn = "0167-9260",
doi = "https://doi.org/10.1016/j.vlsi.2018.10.006",
url = "http://www.sciencedirect.com/science/article/pii/S0167926018302608",
author = "S.S. Sahoo and T.D.A. Nguyen and B. Veeravalli and A. Kumar",
keywords = "Dynamic partial reconfiguration, Field programmable gate arrays, Lifetime-aware scheduling, Task-graphs, Reliability, Heterogeneous systems, Real-time systems",
abstract = "Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification."
}Downloads
Multi-objective design_space_exploration [PDF]
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- 4. Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018. [Bibtex & Downloads]
Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems
×Reference
Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018.
Bibtex
@INPROCEEDINGS{dprLifeASPDAC,
author={Siva Satyendra Sahoo and Tuan Duy Anh Nguyen and B. Veeravalli and Akash Kumar},
booktitle={2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)},
title={Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems },
year={2018},
volume={},
number={},
pages={1-6},
keywords={Reconfigurable Computing, Dynamic Partial Reconfiguration, Integer Linear Programming, Network-on-Chip, FPGA Floorplanning},
month={Jan},}Downloads
ASPDAC-2018-siva [PDF]
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- 3. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems", In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018. [Bibtex & Downloads]
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems
×Reference
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems", In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018.
Bibtex
@INPROCEEDINGS{VLSID2018-siva,
author={Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
booktitle={2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)},
title={CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems },
year={2018},
volume={},
number={},
pages={1-6},
keywords={Cross-layer Resilience, Real-time systems, FaultTolerance },
doi={},
ISSN={},
month={Jan},}Downloads
VLSID-2018-siva [PDF]
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2016
- 2. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems", In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016. [Bibtex & Downloads]
Cross-layer fault-tolerant design of real-time systems
×Reference
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems", In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016.
Bibtex
@INPROCEEDINGS{sssahooDFT16,
author={Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
booktitle={International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)},
title={Cross-layer fault-tolerant design of real-time systems},
year={2016},
pages={1--6},
month={Sept}}Downloads
DFT_cam_ready_Certified [PDF]
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- 1. Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016. [Bibtex & Downloads]
Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults
×Reference
Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016.
Bibtex
@inproceedings{siva2016date,
title={Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults},
author={Siva Satyendra Sahoo and Akash Kumar and Bharadwaj Veeravalli},
booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE)},
year={2016},
month={mar},
organization={IEEE}
}Downloads
date-2016-385-camera ready [PDF]
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