Siva Satyendra Sahoo

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siva_satyendra.sahoo@tu-dresden.de

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Siva Satyendra is currently working as a Postdoctoral Researcher for the project "Predictive Self-learning Control for Building Facades Using FPGAs (PRÄKLIMA FASSADE)". He has obtained his Ph.D. from the National University of Singapore, Singapore. His doctoral thesis focused on Cross-layer Reliability for Heterogeneous Embedded Systems and spanned from 2015-2019.  He completed his masters (M.Tech) from the Indian Institute of Science, Bangalore in 2010-2012 in the specialization Electronics Design Technology.  His master's thesis focused on Hardware Accelerator for Support Vector Machines. He has also worked with Intel India, Bangalore  during 2012-2014 in the domain of Physical Design. His work at Intel focused on improving reliability during SoC Integration of dense integrated circuits for smartphones/tablets. His research interests include Embedded Systems, Machine Learning, Reconfigurable Computing, Reliability-aware Computing Systems, and System-level Design.

Complete list of publications

 

Recent Talks/Tutorials

DAC 2020 (PhD Forum)

DAC 2020 (Research Contribution)

DFTS 2020

 

Publications

  • 2023

  • 24. Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Network", In Proceeding: Asia and South Pacific Design Automation Conference (ASP-DAC), ACM/IEEE, Nov 2023. [Bibtex & Downloads]
  • 2022

  • 23. Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), vol. 41, no. 10, pp. 3239-3251, October 2022. [doi] [Bibtex & Downloads]
  • 22. Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar, "PosAx-O: Exploring Operator-level Approximatons for Posit Arithmetic in Embedded AI/ML" (to appear), In Proceeding: Euromicro Conference on Digital System Design (DSD), pp. 1-6, Aug 2022. [Bibtex & Downloads]
  • 21. Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar, "AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems", In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–31, January 2022. [Bibtex & Downloads]
  • 2021

  • 20. Siva Satyendra Sahoo, Akash Kumar, "CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. [Bibtex & Downloads]
  • 19. Siva Satyendra Sahoo, Akash Kumar, "Using Monte Carlo Tree Search for CAD - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems", In Proceeding: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2021. [Bibtex & Downloads]
  • 18. Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel C. B. Wong, Geoff V. Merrett, Yinyuan Zhao, Jiachen Wang, Xiaohang Wang, Amit Kumar Singh, "Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives", Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis, ACM, Sep 2021. [doi] [Bibtex & Downloads]
  • 17. S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021. [Bibtex & Downloads]
  • 16. Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", In IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, July 2021. [doi] [Bibtex & Downloads]
  • 15. Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar, "MemOReL: A Memory-Oriented Optimization Approach to Reinforcement Learning on FPGA-Based Embedded Systems", Association for Computing Machinery, pp. 339–346, New York, NY, USA, June 2021. [doi] [Bibtex & Downloads]
  • 14. Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem", In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 264-269, Feb. 2021. [doi] [Bibtex & Downloads]
  • 13. Siva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar, "Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper", In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 1, pp. 7, Jan 2021. [doi] [Bibtex & Downloads]
  • 2020

  • 12. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] [Bibtex & Downloads]
  • 11. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems", In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020. [Bibtex & Downloads]
  • 10. S. S. Sahoo, B. Veeravalli, A. Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems", In Proceeding: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2020. [doi] [Bibtex & Downloads]
  • 9. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020. [Bibtex & Downloads]
  • 8. Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar, "DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies", In Proceeding: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar 2020. [doi] [Bibtex & Downloads]
  • 2018

  • 6. S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning", In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), pp. 230-233, Dec 2018. [doi] [Bibtex & Downloads]
  • 5. S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems", In Integration, November 2018. [doi] [Bibtex & Downloads]
  • 4. Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems", In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018. [Bibtex & Downloads]
  • 3. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems", In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018. [Bibtex & Downloads]
  • 2016

  • 2. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems", In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016. [Bibtex & Downloads]
  • 1. Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults", In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016. [Bibtex & Downloads]