Siva Satyendra Sahoo

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Phone

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siva_satyendra.sahoo@tu-dresden.de

+49 (0)351 463-43731

+49 (0)351 463-39995

Helmholtzstrasse 18, BAR-III78

 

Siva Satyendra is currently working as a Postdoctoral Researcher for the project "Predictive Self-learning Control for Building Facades Using FPGAs (PRÄKLIMA FASSADE)". He has obtained his Ph.D. from the National University of Singapore, Singapore. His doctoral thesis focused on Cross-layer Reliability for Heterogeneous Embedded Systems and spanned from 2015-2019.  He completed his masters (M.Tech) from the Indian Institute of Science, Bangalore in 2010-2012 in the specialization Electronics Design Technology.  His master's thesis focused on Hardware Accelerator for Support Vector Machines. He has also worked with Intel India, Bangalore  during 2012-2014 in the domain of Physical Design. His work at Intel focused on improving reliability during SoC Integration of dense integrated circuits for smartphones/tablets. His research interests include Embedded Systems, Machine Learning, Reconfigurable Computing, Reliability-aware Computing Systems, and System-level Design.

Complete list of publications

 
Topics for Thesis/Project/SHK/WHK

Please contact me if you are interested in working on any of the following projects as part of your Project/Thesis and for SHK/WHK positions. Some of the topics (indicated along with the title) are applicable for only SHK/WHK positions as they involve only extending already published research works. For the other topics, the participants can work under Thesis/Project or SHK/WHK positions.

Cross-layer Approximation for Embedded Machine Learning
  • Description: While Machine learning algorithms are being used for virtually every application, the high implementation costs of such algorithms still hinder their widespread use in resource-constrained Embedded systems. Approximate Computing (AxC) allows the designers to use low-energy (power and area) implementations with a slight degradation in results quality. Still better, Cross-layer Approximation (CLAx) offers the scope for much more improvements in power and energy reduction by using methods such as loop perforations, along with approximate hardware. Finding the proper combination of approximation techniques in hardware and software and across the layers of a DNN to provide just enough accuracy at the lowest cost poses an interesting research problem. In our research efforts towards solving this problem, we have implemented a DSE framework for 2D convolution. We would like to implement a similar framework for Convolution and Fully connected layers of a DNN.
  • Pre-requisites:
    • Digital Design, FPGA-based accelerator design, HLS
    • Python, C++/ SystemC
  • Skills that will be acquired during project-work:
    • Hardware design for ML
    • Multi-objective optimization of hardware accelerators.
    • System-level design
    • Technical writing for research publications.
  • Related Publications:
    • DSE for implementing Cross-layer Approximation. (Submitted for double-blind review)
    • Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures", In IEEE Transactions on Computers, April 2020.
    • Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems", 27 October 2020.
AI for healthcare: A hardware-software co-design approach
  • Description: The Covid-19 situation around the world has shown the extreme shortage and the vulnerability of man-power and existing diagnostic methods in current healthcare systems. Artificial intelligence (AI) presents scope for improving the healthcare system by augmenting the diagnosis stage and thereby helping radiologists and pathologists in providing timely feedback. This project explores the impact of a hardware/software co-design approach to improve the performance of AI systems to increase their effectiveness in terms of saving precious time for critical patients.
  • Pre-requisites:
    • AI/ML algorithms (Signal processing)
    • ML framework: Tensorflow/PyTorch/Scipy
    • Hardware Design, Computer Architecture
  • Skills that will be acquired during project-work:
    • Hardware/software co-design for critical systems
    • Exploration of novel AI algorithms for healthcare
    • Computer Vision
    • Hardware Accelerator design
    • Technical writing for research publications.
Design of AI/ML-based Biomedical Signal Processing Systems
  • Description: The range of applications that use AI/ML is increasing every day. The wide availability of medical data makes bio-medical systems a prime candidate for using machine learning. Paradigms such as online learning allow modern bio-medical systems to be customized for individual patients and are increasingly being used for monitoring systems. However, naïve implementations of ML algorithms can result in costly designs that can make such systems infeasible for wearables and similar battery-operated monitoring systems. This project involves a hardware-software co-design approach to implementing low-cost Signal processing for biomedical applications. Software techniques that explore algorithms, quantization, etc., and hardware techniques of approximate circuit design, ultra-low power RISC-V microarchitecture, low-energy accelerators, etc. will be explored in the project.
  • Pre-requisites:
    • Digital Design, Computer Architecture: RISC-V (preferred
    • FPGA architecture and design with VHDL/Verilog
    • Basic understanding of Signal Processing and Machine Learning
  • Skills that will be acquired during project-work:
    • RISC-V based SoC design
    • Accelerator design (HLS/HDL)
    • Bio-medical systems
    • Technical writing for research publications.
Accelerator design for ML-based NLP
  • Description: There has been a recent push towards newer ML-based NLP models that can exploit the parallelism of accelerators. From bag-of-words to RNNs to LSTMs and most recently transformers, the models for NLP have evolved rapidly. In this project, we plan to explore the suitability of FPGA-based accelerators for modern NLP models. We aim to design NLP accelerators that exploit precision scaling and approximate computing.
  • Pre-requisites:
    • Digital Design, Computer Architecture
    • FPGA architecture and design with VHDL/Verilog, HLS knowledge preferable
    • Basic understanding of Machine Learning, specifically NLP
  • Skills that will be acquired during project-work:
    • Accelerator design (HLS/HDL)
    • Modern NLP algorithms and their implementation
    • Approximate Computing
    • Technical writing for research publications.
Reconfigurable Architecture design for Emerging Technologies
  • Description: Design of novel application/domain-specific reconfigurable architectures for implementing emerging applications. the project also explores the impact of emerging devices in this perspective.
  • Pre-requisites:
    • Computer Architecture
    • FPGA architecture
    • Hardware Design (Verilog)
    • Python
  • Skills that will be acquired during project-work:
    • Reconfigurable System Design
    • Logic Synthesis
    • FPGA design algorithms (VPR)
Implementing application-specific approximate computing with RISC-V
  • Description: : The project involves implementing approximate arithmetic in RISC V-based application-specific system design. The major components of the project include:
    • Implementing custom RISC V implementations on an FPGA-based system
    • Integrating approximate components into standard RISC V microarchitectures
    • Familiarizing with the RISC V toolchain for enabling compilation for custom micro-architecture
    • Low-cost AI/ML accelerator design for RISC V SoC
    • Characterizing the microarchitecture for ASIC-based implementation (synthesis-only)
  • Pre-requisites:
    • Computer Architecture
    • Digital Design
    • Verilog/ VHDL/ SystemC)
    • Some scripting language (preferably Python)
  • Skills that will be acquired during project-work:
    • FPGA Design tools (Xilinx)
    • Extending RISC-V instructions
    • ASIC-based design
Resiliency (Reliability & Security)-aware System-level design for Neuromorphic Computing
  • Description: The project involves research into the design of resilient systems for Neuromorphic computing. Multiple aspects such as reliability and security of systems implementing Artificial Neural Networks and Spiking Neural Networks
  • Pre-requisites:
    • Machine Learning
    • SystemC /System Verilog
    • Digital Design
  • Skills that will be acquired during project-work:
    • Hands-on learning with HLS tools like Xilinx Vitis
    • System-level design and optimization
    • Resiliency design for critical systems
    • Technical writing for research publications
Operating Environment-aware Partitioning in FPGA-based Systems for Improving Lifetime Reliability
  • Description: FPGAs (Field Programmable Gate Arrays) are being increasingly used across diverse application areas -- Healthcare, Military, Telecom, Automobiles, etc. Such diversity results in widely varying operating conditions for such FPGA-based embedded systems. Consequently, the rate of different types of physical faults witnessed by the system can differ by large margins. Further, in areas such as space exploration, repair by replacement can be near-impossible. Therefore, the mission life of systems can be one of the major design objectives. In addition, with the predicted growth in the number of IoT devices and the rising usage of FPGA-based edge devices, an increase in the system’s operational life can lead to lower electronic waste and more sustainable computing. The project goals include:
    • Optimization across multiple system partitioning methods --- HW/HW, SW/SW, and HW/SW --- for designing lifetime aware FPGA-based systems.
    • Modeling the impact of external and internal physical fault-causing mechanisms on a Dynamic Partially Reconfigurable (DPR)-based system.
    • Simulate/Emulate a functional DPR system on FPGAs with relevant fault-injection fault-diagnosis and repair mechanisms.
  • Pre-requisites:
    • Knowledge of FPGA architecture.
    • Knowledge of real-time scheduling and related concepts
    • Programming skills: C/C++, Python, SystemC/System Verilog, Verilog/VHDL
  • Skills that will be acquired during project-work:
    • Hands-on development with FPGA-based systems.
    • System-level modeling and design.
    • Multi-objective optimization across different system goals – performance, reliability, power dissipation etc.
    • Technical writing for research publications
  • Related Publications:
    • Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems" , In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), vol. , no. , pp. 1-6, Jan 2018.
    • S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems", In Integration, November 2018.
    • S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli and A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning," 2018 International Conference on Field-Programmable Technology (FPT), Naha, Okinawa, Japan, 2018, pp. 230-233.
Using AI for Cyber-physical Systems
  • Description: The project involves the exploration of the applicability of various Machine Learning methods in the optimization of the controller design for cyber-physical systems. A sample problem of controlling various actuators in an office-building environment for minimizing energy consumption and maximizing user-comfort will be used as a test-case for testing the performance of traditional, predictive, and self-learning algorithms.
  • Pre-requisites:
    • Knowledge of AI/ML methods and some background in control systems.
    • Python with ML tools (Scikit/Tensorflow/Pytorch/OpenAI)
  • Skills that will be acquired during project-work:
    • Design of cyber-physical systems
    • Application of AI/ML methods for dynamic systems
    • Hardware design and impact of accelerators on cyber-physical systems' performance.
  • Related Publications:
    • Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020.
Cross-layer Design of Heterogeneous Embedded Systems *

*Please note that this is planned as a short-term project as it involves extending current research results and may not be suitable as a complete thesis topic. Suitable for Project SHK/WHK positions.

  • Description: The project involves the system-level design of embedded systems that considers design choices across multiple layers of the system stack. The project will focus on both traditional and machine learning applications as test applications for performance metrics such as latency, power, throughput, reliability, and energy.
  • Pre-requisites:
    • Python/C++
    • Optimization basics
  • Skills that will be acquired during project-work:
    • System-level modeling and analysis.
    • Multi-objective optimization across different system goals – performance, reliability, power dissipation, etc.
    • Technical writing for research publications.
  • Related Publications:
    • DSE for Cross-layer Low-power design in Heterogeneous Embedded Systems (Article Submitted for peer-review)
    • Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems" , In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016
Storage-aware Hybrid Design Space exploration for Heterogeneous Embedded Systems *

*Please note that this is planned as a short-term project as it involves extending current research results and may not be suitable as a complete thesis topic. Suitable for Project SHK/WHK positions.

  • Description: The project involves the system-level design of embedded systems that use a hybrid DSE approach for enabling storage-aware task-mapping in resource-constrained Heterogeneous Systems. The project will focus on both traditional and machine learning applications as test applications for performance metrics such as latency, power, throughput, reliability, and energy. The main focus will be to build on the published work cited below.
  • Pre-requisites:
    • Python/C++
    • Optimization basics
  • Skills that will be acquired during project-work:
    • System-level modeling and analysis.
    • Multi-objective optimization across different system goals – performance, reliability, power dissipation, etc.
    • Technical writing for research publications.
  • Related Publications:
    • S. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems" , Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019.
Implementing Multi-objective Bayesian Optimization for System-level DSE *

*Please note that this is planned as a short-term project as it involves extending current research results and may not be suitable as a complete thesis topic. Suitable for Project SHK/WHK positions.

  • Description: The project involves the system-level design of embedded systems and focuses on traversing a large design space through multi-objective Bayesian optimization The project will focus on both traditional and machine learning applications as test applications for performance metrics such as latency, power, throughput, reliability, and energy. The main focus will be to build on the published work cited below.
  • Pre-requisites:
    • Python/C++
    • Optimization basics
  • Skills that will be acquired during project-work:
    • System-level modeling and analysis.
    • Multi-objective optimization across different system goals – performance, reliability, power dissipation, etc.
    • Technical writing for research publications.
  • Related Publications:
    • Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems", Proceedings of the 57th Annual Design Automation Conference 2020, Association for Computing Machinery, New York, NY, USA, July 2020.
Probabilistic Modeling for Cross-layer Reliability in Heterogeneous Embedded systems *

*Please note that this is planned as a short-term project as it involves extending current research results and may not be suitable as a complete thesis topic. Suitable for Project SHK/WHK positions.

  • Description: The project involves the probabilistic system-level modeling for improving reliability in heterogeneous Embedded Systems. The project will focus on both traditional and machine learning applications as test applications for performance metrics such as latency, power, throughput, reliability, and energy. The main focus will be to build on the published work cited below.
  • Pre-requisites:
    • Python/C++
    • Optimization basics
    • Probabilistic Modeling
  • Skills that will be acquired during project-work:
    • System-level modeling and analysis.
    • Multi-objective optimization across different system goals – performance, reliability, power dissipation, etc.
    • Technical writing for research publications.
  • Related Publications:
    • Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems", In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020.
    • Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems", In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018.
An agent-based lifetime optimization-aware run-time adaptation approach to QoS-constrained Heterogeneous Embedded Systems *

*Please note that this is planned as a short-term project as it involves extending current research results and may not be suitable as a complete thesis topic. Suitable for Project SHK/WHK positions.

  • Description: The project involves the system-level optimization for improving lifetime reliability in heterogeneous Embedded Systems. The project will focus on both traditional and machine learning applications as test applications and will involve improving the run-time optimization methodology. The main focus will be to build on the published work cited below.
  • Pre-requisites:
    • Python/C++
    • Optimization basics
  • Skills that will be acquired during project-work:
    • AI/ML for EDA
    • System-level modeling and analysis.
    • Multi-objective optimization across different system goals – performance, reliability, power dissipation, etc.
    • Technical writing for research publications.
  • Related Publications:
    • Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs using Time-Series Analysis of Intermittent faults", In Proceeding: Design, Automation, and Test in Europe Conference and Exhibition (DATE), Mar 2016.
 

Publications

  • 2021

  • 15. Siva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar, "Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper" , In Journal of Low Power Electronics and Applications, MDPI AG, vol. 11, no. 1, pp. 7, Jan 2021. [doi] [Bibtex & Downloads]
  • 14. Behnaz Ranjbar, Ali Hoseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar, "Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem" , In Proceeding: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. [Bibtex & Downloads]
  • 2020

  • 13. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems" , In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] [Bibtex & Downloads]
  • 12. Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems" , 27 October 2020. [Bibtex & Downloads]
  • 11. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems" , In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020. [Bibtex & Downloads]
  • 10. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems" , Proceedings of the 57th Annual Design Automation Conference 2020, Association for Computing Machinery, New York, NY, USA, July 2020. [Bibtex & Downloads]
  • 9. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures" , In IEEE Transactions on Computers, April 2020. [Bibtex & Downloads]
  • 8. S. Rai, M. Raitza, S. S. Sahoo, A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]
  • 2018

  • 6. S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning" , In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), pp. 230-233, Dec 2018. [doi] [Bibtex & Downloads]
  • 5. S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems" , In Integration, November 2018. [doi] [Bibtex & Downloads]
  • 4. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems" , In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 1-6, Jan 2018. [Bibtex & Downloads]
  • 3. Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems" , In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Jan 2018. [Bibtex & Downloads]
  • 2016

  • 2. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems" , In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016. [Bibtex & Downloads]
  • 1. Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults" , In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016. [Bibtex & Downloads]