Siva Satyendra Sahoo |
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Phone Fax Visitor's Address |
siva_satyendra.sahoo@tu-dresden.de +49 (0)351 463-43731 +49 (0)351 463-39995 Helmholtzstrasse 18, BAR-III78 |
Siva Satyendra is currently working as a Postdoctoral Researcher for the project "Predictive Self-learning Control for Building Facades Using FPGAs (PRÄKLIMA FASSADE)". He has obtained his Ph.D. from the National University of Singapore, Singapore. His doctoral thesis focused on Cross-layer Reliability for Heterogeneous Embedded Systems and spanned from 2015-2019. He completed his masters (M.Tech) from the Indian Institute of Science, Bangalore in 2010-2012 in the specialization Electronics Design Technology. His master's thesis focused on Hardware Accelerator for Support Vector Machines. He has also worked with Intel India, Bangalore during 2012-2014 in the domain of Physical Design. His work at Intel focused on improving reliability during SoC Integration of dense integrated circuits for smartphones/tablets. His research interests include Embedded Systems, Machine Learning, Reconfigurable Computing, Reliability-aware Computing Systems, and System-level Design.
Publications
2020
- 13. Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems" , In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi] [Bibtex & Downloads]
ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems
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Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar, "ReLAccS: A Multi-level Approach to Accelerator Design for Reinforcement Learning on FPGA-based Systems" , In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), pp. 1–1, 28 October 2020. [doi]
Bibtex
@article{Baranwal_2020,
doi = {10.1109/tcad.2020.3028350},
url = {https://doi.org/10.1109%2Ftcad.2020.3028350},
year = 2020,
month={28 October}
publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
pages = {1--1},
author = {Akhil Raj Baranwal and Salim Ullah and Siva Satyendra Sahoo and Akash Kumar},
title = {{ReLAccS}: A Multi-level Approach to Accelerator Design for Reinforcement Learning on {FPGA}-based Systems},
journal = {{IEEE} Transactions on Computer-Aided Design of Integrated Circuits and Systems}
}
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- 12. Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems" , 27 October 2020. [Bibtex & Downloads]
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
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Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar, "ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems" , 27 October 2020.
Bibtex
@misc{nambi2020expannd,
title={ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems},
author={Suresh Nambi and Salim Ullah and Aditya Lohana and Siva Satyendra Sahoo and Farhad Merchant and Akash Kumar},
year={2020},
month={27 October},
eprint={2010.12869},
archivePrefix={arXiv},
primaryClass={cs.AR}
}
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- 11. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems" , In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020. [Bibtex & Downloads]
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems
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Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems" , In Proceeding: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020, October 2020.
Bibtex
@InProceedings{SahooVK020,
author = {Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
title = ,
booktitle = {2020 {IEEE} {International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2020, ESA-ESRIN, Frascati (Rome) Italy, October 19-21, 2020}},
year = {2020},
month = {October},
}
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- 10. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems" , Proceedings of the 57th Annual Design Automation Conference 2020, Association for Computing Machinery, New York, NY, USA, July 2020. [Bibtex & Downloads]
CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems
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Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems" , Proceedings of the 57th Annual Design Automation Conference 2020, Association for Computing Machinery, New York, NY, USA, July 2020.
Bibtex
@inproceedings{SahooVK020_1,
author = {Sahoo, Siva Satyendra and Veeravalli, Bharadwaj and Kumar, Akash},
title = ,
year = {2020},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
booktitle = {Proceedings of the 57th Annual Design Automation Conference 2020},
numpages = {6},
keywords = {Reinforcement Learning, Cross-layer Reliability, Run-time Resource Management, Embedded Systems},
location = {DAC, A virtual experience},
series = {DAC ’20},
note = {(Accepted for publishing)},
month={July},
}
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CLRIntegTMap_DAC2020_CameraReady(1) [PDF]
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- 9. S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures" , In IEEE Transactions on Computers, April 2020. [Bibtex & Downloads]
Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures
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S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, A. Kumar, "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures" , In IEEE Transactions on Computers, April 2020.
Bibtex
@ARTICLE{9072581,
author={S. {Ullah} and H. {Schmidl} and S. S. {Sahoo} and S. {Rehman} and A. {Kumar}},
journal={IEEE Transactions on Computers},
title={Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures},
year={2020},
month={April},}
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TC_2019_Accurate_Approx_Multiplier [PDF]
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- 8. S. Rai, M. Raitza, S. S. Sahoo, A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020. [Bibtex & Downloads]
DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES
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S. Rai, M. Raitza, S. S. Sahoo, A. Kumar, "DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES" , In Proceeding: 2020 Design, Automation Test in Europe Conference Exhibition (DATE), March 2020.
Bibtex
@INPROCEEDINGS{date_Shubham,
author={S. Rai and M. Raitza and S. S. Sahoo and A. Kumar},
booktitle={2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
title={DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES},
year={2020},
month={March},}
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DiSCERN_DATE_2020 [PDF]
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2019
- 7. S. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems" , Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019. [doi] [Bibtex & Downloads]
A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems
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S. S. Sahoo, B. Veeravalli, A. Kumar, "A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems" , Proceedings of the 56th Annual Design Automation Conference, ACM, New York, NY, USA, June 2019. [doi]
Bibtex
@inproceedings{SahooVK019_1,
author = {S. S. Sahoo and B. Veeravalli and A. Kumar},
title = ,
booktitle = ,
series = {DAC '19},
year = {2019},
month={june},
isbn = {978-1-4503-6725-7/19/06},
location = {Las Vegas, NV, USA},
numpages = {6},
url = {http://doi.acm.org/10.1145/3316781.3317746},
doi = {10.1145/3316781.3317746},
acmid = {3317746},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {Cross-layer Reliability, Run-time Resource Management, Embedded Systems, Reinforcement Learning},
}
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a38-Sahoo [PDF]
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2018
- 6. S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning" , In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), vol. , no. , pp. 230-233, Dec 2018. [doi] [Bibtex & Downloads]
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning
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S. S. Sahoo, T. D. A. Nguyen, B. Veeravalli, A. Kumar, "QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning" , In Proceeding: 2018 International Conference on Field-Programmable Technology (FPT), vol. , no. , pp. 230-233, Dec 2018. [doi]
Bibtex
@INPROCEEDINGS{8742320,
author={S. S. {Sahoo} and T. D. A. {Nguyen} and B. {Veeravalli} and A. {Kumar}},
booktitle={2018 International Conference on Field-Programmable Technology (FPT)},
title={QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning},
year={2018},
volume={},
number={},
pages={230-233},
keywords={circuit optimisation;field programmable gate arrays;integrated circuit design;integrated circuit reliability;logic design;quality of service;Dynamic Partial Reconfiguration;QoS-aware cross-layer reliability-integrated design methodology;FPGA-based DPR systems;FPGA-based dynamic partially reconfigurable system;partially reconfigurable modules;quality of service;fault-mitigation;Conferences;Cross-layer Reliability;Dynamic Partial Reconfiguration;Field Programmable Gate Array;Embedded Systems},
doi={10.1109/FPT.2018.00041},
ISSN={},
month={Dec},}
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08742320 [PDF]
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- 5. S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems" , In Integration, November 2018. [doi] [Bibtex & Downloads]
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems
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S.S. Sahoo, T.D.A. Nguyen, B. Veeravalli, A. Kumar, "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems" , In Integration, November 2018. [doi]
Abstract
Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system s mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification.
Bibtex
@article{SAHOO2018,
title = "Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems",
journal = "Integration",
year = "2018",
month={November},
issn = "0167-9260",
doi = "https://doi.org/10.1016/j.vlsi.2018.10.006",
url = "http://www.sciencedirect.com/science/article/pii/S0167926018302608",
author = "S.S. Sahoo and T.D.A. Nguyen and B. Veeravalli and A. Kumar",
keywords = "Dynamic partial reconfiguration, Field programmable gate arrays, Lifetime-aware scheduling, Task-graphs, Reliability, Heterogeneous systems, Real-time systems",
abstract = "Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification."
}
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Multi-objective design_space_exploration [PDF]
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- 4. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems" , In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), vol. , no. , pp. 1-6, Jan 2018. [doi] [Bibtex & Downloads]
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems
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Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems" , In Proceeding: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), vol. , no. , pp. 1-6, Jan 2018. [doi]
Bibtex
@INPROCEEDINGS{VLSID2018-siva,
author={Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
booktitle={2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)},
title={CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems },
year={2018},
volume={},
number={},
pages={1-6},
keywords={Cross-layer Resilience, Real-time systems, FaultTolerance },
doi={},
ISSN={},
month={Jan},}
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VLSID-2018-siva [PDF]
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- 3. Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems" , In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), vol. , no. , pp. 1-6, Jan 2018. [Bibtex & Downloads]
Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems
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Siva Satyendra Sahoo, Tuan Duy Anh Nguyen, B. Veeravalli, Akash Kumar, "Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems" , In Proceeding: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), vol. , no. , pp. 1-6, Jan 2018.
Bibtex
@INPROCEEDINGS{dprLifeASPDAC,
author={Siva Satyendra Sahoo and Tuan Duy Anh Nguyen and B. Veeravalli and Akash Kumar},
booktitle={2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)},
title={Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems },
year={2018},
volume={},
number={},
pages={1-6},
keywords={Reconfigurable Computing, Dynamic Partial Reconfiguration, Integer Linear Programming, Network-on-Chip, FPGA Floorplanning},
month={Jan},}
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ASPDAC-2018-siva [PDF]
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2016
- 2. Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems" , In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016. [Bibtex & Downloads]
Cross-layer fault-tolerant design of real-time systems
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Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar, "Cross-layer fault-tolerant design of real-time systems" , In Proceeding: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, Sept 2016.
Bibtex
@INPROCEEDINGS{sssahooDFT16,
author={Siva Satyendra Sahoo and Bharadwaj Veeravalli and Akash Kumar},
booktitle={International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)},
title={Cross-layer fault-tolerant design of real-time systems},
year={2016},
pages={1--6},
month={Sept}}
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DFT_cam_ready_Certified [PDF]
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- 1. Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults" , In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016. [Bibtex & Downloads]
Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults
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Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli, "Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults" , In Proceeding: Design, Automation and Test in Europe Conference and Exhibition (DATE), Mar 2016.
Bibtex
@inproceedings{siva2016date,
title={Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs usingTime-Series Analysis of Intermittent faults},
author={Siva Satyendra Sahoo and Akash Kumar and Bharadwaj Veeravalli},
booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE)},
year={2016},
month={mar},
organization={IEEE}
}
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date-2016-385-camera ready [PDF]
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